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Features

•

Single 3.3V

10% Supply

•

Fast Read Access Time - 200 ns

•

Automatic Page Write Operation

– Internal Address and Data Latches for 128 Bytes

– Internal Control Timer

•

Fast Write Cycle Time

– Page Write Cycle Time - 10 ms Maximum

– 1 to 128-Byte Page Write Operation

•

Low Power Dissipation

– 15 mA Active Current

–20

µA CMOS Standby Current

•

Hardware and Software Data Protection

•

DATA Polling for End of Write Detection

•

High Reliability CMOS Technology

– Endurance: 100,000K Cycles

– Data Retention: 10 Years

•

JEDEC Approved Byte-Wide Pinout

•

Commercial and Industrial Temperature Ranges

Description

The AT28LV010 is a high-performance 3-volt only Electrically Erasable and Program-

mable Read Only Memory. Its 1 megabit of memory is organized as 131,072 words by

8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device

offers access times to 200 ns with power dissipation of just 54 mW. When the device

is deselected, the CMOS standby current is less than 20

µA.

1-Megabit

(128K x 8)

Low Voltage

Paged Parallel

EEPROMs

AT28LV010

Rev. 0395B–10/98

Pin Configurations

Pin Name Function

A0 - A16 Addresses

Chip Enable

Output Enable

WE Write Enable

I/O0 - I/O7 Data Inputs/Outputs

NC No Connect

DC Don’t Connect

PDIP

Top View

A16

A15

A12

I/O0

I/O1

I/O2

GND

VCC

A14

A13

A11

A10

I/O7

I/O6

I/O5

I/O4

I/O3

TSOP

Top View

A11

A13

A14

VCC

A16

A15

A12

A10

I/O7

I/O6

I/O5

I/O4

I/O3

GND

I/O2

I/O1

I/O0

PLCC

Top View

I/O0

A14

A13

A11

A10

I/O7

I/O1

I/O2

GND

I/O3

I/O4

I/O5

I/O6

A12

A15

A16

VCC

(continued)

Summary of content (12 pages)

PAGE 1
Features • Single 3.
PAGE 2
The AT28LV010 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 128-byte page register to allow writing of up to 128 bytes simultaneously. During a write cycle, the address and 1 to 128 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer.
PAGE 3
AT28LV010 Device Operation READ: The AT28LV010 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dualline control gives designers flexibility in preventing bus contention in their system.
PAGE 4
DC and AC Operating Range AT28LV010-20 AT28LV010-25 0°C - 70°C 0°C - 70°C -40°C - 85°C -40°C - 85°C 3.3V ± 5% 3.3V ± 10% Com. Operating Temperature (Case) Ind. VCC Power Supply Operating Modes Mode CE OE WE I/O Read VIL VIL VIH DOUT VIL VIH VIL DIN High Z Write (2) Standby/Write Inhibit (1) VIH X X Write Inhibit X X VIH Write Inhibit X VIL X Output Disable X VIH X Notes: High Z 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms.
PAGE 5
AT28LV010 AC Read Characteristics AT28LV010-20 Symbol Parameter tACC Min Max AT28LV010-25 Min Max Units Address to Output Delay 200 250 ns (1) CE to Output Delay 200 250 ns (2) OE to Output Delay 0 80 0 100 ns tDF(3)(4) CE or OE to Output Float 0 55 0 60 ns tOH Output Hold from OE, CE or Address, whichever occurred first 0 tCE tOE 0 ns AC Read Waveforms(1)(2)(3)(4) Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2.
PAGE 6
AC Write Characteristics(1) Symbol Parameter tAS, tOES Address, OE Set-up Time tAH Address Hold Time tCS Min Max Units 0 ns 100 ns Chip Select Set-up Time 0 ns tCH Chip Select Hold Time 0 ns tWP Write Pulse Width (WE or CE) 200 ns tDS Data Set-up Time 100 ns tDH, tOEH Data, OE Hold Time 10 ns Note: 1. All write operations must be preceded by the SDP command sequence.
PAGE 7
AT28LV010 Software Protected Write Characteristics Symbol Parameter Min tWC Write Cycle Time tAS Address Set-up Time tAH Max Units 10 ms 0 ns Address Hold Time 100 ns tDS Data Set-up Time 100 ns tDH Data Hold Time 10 ns tWP Write Pulse Width 200 ns tBLC Byte Load Cycle Time tWPH Write Pulse Width High 150 100 µs ns Programming Algorithm LOAD DATA AA TO ADDRESS 5555 Notes: LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA A0 TO ADDRESS 5555 1.
PAGE 8
Data Polling Characteristics(1) Symbol Parameter tDH Data Hold Time tOEH OE Hold Time Min Max OE to Output Delay tWR Write Recovery Time Units 10 ns 10 ns (2) tOE Notes: Typ ns 0 ns 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics Data Polling Waveforms Toggle Bit Characteristics(1) Symbol Parameter tDH Data Hold Time tOEH OE Hold Time tOE OE to Output Delay tOEHP OE High Pulse 1.
PAGE 9
AT28LV010 Ordering Information(1) ICC (mA) tACC (ns) Active Standby Ordering Code Package 200 15 0.02 AT28LV010-20JC AT28LV010-20PC AT28LV010-20TC 32J 32P6 32T Commercial (0° to 70°C) 15 0.02 AT28LV010-20JI AT28LV010-20PI AT28LV010-20TI 32J 32P6 32T Industrial (-40° to 85°C) 15 0.02 AT28LV010-25JC AT28LV010-25PC AT28LV010-25TC 32J 32P6 32T Commercial (0° to 70°C) 15 0.
PAGE 10
Packaging Information 32J, 32-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-016 AE .045(1.14) X 45° PIN NO. 1 IDENTIFY .025(.635) X 30 050(1.27) TYP 45 .012(.305) .008(.203) .030(.762) .015(3.81) .095(2.41) .060(1.52) .140(3.56) .120(3.05) .022(.559) X 45° MAX (3X) .453(11.5) .447(11.4) .495(12.6) 485(12 3) 32T, 32-Lead, Plastic Thin Small Outline Package (TSOP) Dimensions in Millimeters and (Inches)* JEDEC OUTLINE MO-142 DD INDEX MARK 7.50(.
PAGE 11
AT28LV010 11
PAGE 12
Atmel Headquarters Atmel Operations Corporate Headquarters Atmel Colorado Springs 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Europe 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Atmel Rousset Atmel U.K., Ltd.