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DS1215

Phantom Time Chip

DS1215

032697 1/15

FEATURES

• Keeps track of hundredths of seconds, seconds, min-

utes, hours, days, date of the month, months, and

years

• Adjusts for months with fewer than 31 days

• Leap year automatically corrected up to 2100

• No address space required

• Provides nonvolatile controller functions for battery

backup of RAM

• Supports redundant batteries for high–reliability

applications

• Uses a 32.768 KHz watch crystal

• Full ±10% operating range

• Operating temperature range 0°C to 70°C

• Space-saving, 16–pin DIP package and SOIC

• Optional industrial temperature range –40°C to +85°C

(IND)

DESCRIPTION

The DS1215 Phantom Time Chip is a combination of a

CMOS timekeeper and a nonvolatile memory controller.

In the absence of power, an external battery maintains

the timekeeping operation and provides power for a

CMOS static RAM. The watch keeps track of hun-

dredths of seconds, seconds, minutes, hours, day, date,

month, and year information. The last day of the month

is automatically adjusted for months with less than 31

days, including correction for leap year every four years.

The watch operates in one of two formats: a 12–hour

mode with an AM/PM indicator or a 24–hour mode. The

nonvolatile controller supplies all the necessary support

circuitry to convert a CMOS RAM to a nonvolatile

memory. The DS1215 can be interfaced with either

RAM or ROM without leaving gaps in memory.

PIN ASSIGNMENT

BAT1

GND

CCI

CCO

BAT2

RST

CEI

CEO

ROM/RAM

16–PIN DIP (300 MIL)

BAT1

GND

CCI

CCO

BAT2

RST

CEI

CEO

ROM/RAM

16–PIN SOIC (300 MIL)

PIN DESCRIPTION

X1, X2 – 32.768 KHz Crystal Connections

WE – Write Enable

BAT1 – Battery 1 Input

GND – Ground

D – Data In

Q – Data Out

ROM/RAM

– ROM/RAM Select

CEO

– Chip Enable Out

CEI – Chip Enable Input

OE – Output Enable

RST – Reset

BAT2 – Battery 2 Input

CCO

– Switched Supply Output

CCI

– +5 VDC Input

NOTE: Both pins 5 and 8 must be grounded.

ORDERING INFORMATION

DS1215 16–pin DIP

DS1215S 16–pin SOIC

DS1215N 16–pin DIP (IND)

DS1215SN 16–pin SOIC (IND)

Summary of content (15 pages)

PAGE 1
DS1215 DS1215 Phantom Time Chip FEATURES PIN ASSIGNMENT • Keeps track of hundredths of seconds, seconds, minutes, hours, days, date of the month, months, and years • Adjusts for months with fewer than 31 days • Leap year automatically corrected up to 2100 X1 1 16 VCCI X2 2 15 VCCO WE 3 14 BAT2 BAT1 4 13 RST GND 5 12 OE D 6 11 CEI Q 7 10 CEO GND 8 9 • No address space required • Provides nonvolatile controller functions for battery backup of RAM 16–PIN DIP (300 MIL) •
PAGE 2
DS1215 OPERATION CEO remains high during this time, disabling the connected memory. The block diagram of Figure 1 illustrates the main elements of the Time Chip. Communication with the Time Chip is established by pattern recognition of a serial bit stream of 64 bits which must be matched by executing 64 consecutive write cycles containing the proper data on data in (D). All accesses which occur prior to recognition of the 64-bit pattern are directed to memory via the chip enable output pin (CEO).
PAGE 3
DS1215 When the first write cycle is executed, it is compared to bit 1 of the 64–bit comparison register. If a match is found, the pointer increments to the next location of the comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison register pointer is reset.
PAGE 4
DS1215 NONVOLATILE CONTROLLER OPERATION TIME CHIP REGISTER INFORMATION The operation of the nonvolatile controller circuits within the Time Chip is determined by the level of the ROM/RAM select pin. When ROM/RAM is connected to ground, the controller is set in the RAM mode and performs the circuit functions required to make static CMOS RAM and the timekeeping function nonvolatile. A switch is provided to direct power from the battery inputs or VCCI to VCCO with a maximum voltage drop of 0.3 volts.
PAGE 5
DS1215 RAM/TIME CHIP INTERFACE Figure 3 CMOS STATIC RAM A0 – AN ADD DATA I/O D0 – D7 WE OE CE VCC DS1215 10 CEO 12 15 VCCO OE D WE Q 6 3 7 11 CE CEI 13 RST 4 BAT1 X1 + BAT1 +5 VDC VCCI 9 ROM/ RAM BAT2 X2 RST 1 14 OR TIE TO GND FOR ONE–BATTERY OPERATION + BAT2 2 32.
PAGE 6
DS1215 TIME CHIP REGISTER DEFINITION Figure 5 REGISTER RANGE (BCD) 7 6 0 5 4 3 0.1 SEC 2 1 0.
PAGE 7
DS1215 ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature –0.3V to +7.0V 0°C to 70°C –55°C to +125°C 260°C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
PAGE 8
DS1215 (0°C to 70°C; VCC = 4.5 to 5.
PAGE 9
DS1215 AC ELECTRICAL CHARACTERISTICS ROM/RAM = VCCO PARAMETER TYP (0°C to 70°C; VCC = 5V ± 10%) SYMBOL MIN MAX UNITS Read Cycle Time tRC 120 CEI Access Time tCO 100 ns OE Access Time tOE 100 ns CEI to Output in Low Z tCOE 10 ns OE to Output in Low Z tOEE 10 ns CEI to Output in High Z tOD 40 ns OE to Output in High Z tODO 40 ns NOTES ns Address Setup Time tAS 20 ns Address Hold Time tAH Read Recovery tRR 20 ns Write Cycle Time tWC 120 ns CEI Pulse Width tCW
PAGE 10
DS1215 TIMING DIAGRAM: READ CYCLE TO TIME CHIP ROM/RAM = GND WE = VIH tRC CEI tRR tCO tOD tOE OE tOEE tODO ÉÉÉ ÉÉÉ tCOE Q OUTPUT DATA VALID ÉÉÉ ÉÉÉ TIMING DIAGRAM: WRITE CYCLE TO TIME CHIP ROM/RAM = GND OE = VIH tWC WE tWR tWP tWR CEI ÉÉÉÉÉ ÉÉÉÉÉ tCW tDS D 032697 10/15 tDH tDH DATA IN STABLE ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ
PAGE 11
DS1215 TIMING DIAGRAM: READ CYCLE ROM/RAM = VCCO ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÉÉÉÉÉ ÉÉÉÉÉ tRC tCO tRR CEI tOD tRR tRC tOE OE tODO tAS tAS tAH tAH WE tOEE tCOE Q OUTPUT DATA VALID TIMING DIAGRAM: WRITE CYCLE ROM/RAM = VCCO tWC ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ tWR tCW CEI tWR tWC tOW OE tAS tAH tAS tAH WE D tDH tDS tDS tDH DATA IN STABLE 032697 11/15
PAGE 12
DS1215 TIMING DIAGRAM: POWER DOWN ÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇ tCE CEI VIH VIL tPD tPF VBAT - 0.2V tCE ROM/RAM = GND CEO VIH VIL ROM/RAM = VCCO CEO VCCI 4.5V tF 3V TIMING DIAGRAM: POWER UP ÇÇÇÇÇÇ ÇÇÇÇÇÇ VIH CEI VIL BAT - 0.2V ROM/RAM = GND CEO VIL tREC tPD ROM/RAM = VCCO CEO 4.
PAGE 13
DS1215 NOTES: 1. All voltages are referenced to ground. 2. Measured with load shown in Figure 6. 3. Input pulse rise and fall times equal 10 ns. 4. tWR is a function of the latter occurring edge of WE or CE in RAM mode, or OE or CE in ROM mode. 5. tDH and tDS are functions of the first occurring edge of WE or CE in RAM mode, or OE or CE in ROM mode. 6. Measured without RAM connected. 7. Trip point voltage for power–fail detect. VTP = 1.26 x VBAT. For 10% VCC= 5V + 10% operation VBAT = 3.5V max.
PAGE 14
DS1215 DS1215 TIME CHIP B D J H 1 A PKG C F K E G 032697 14/15 16–PIN DIM MIN MAX A IN. MM 0.740 0.780 B IN. MM 0.240 0.260 C IN. MM 0.120 0.140 D IN. MM 0.300 0.325 E IN. MM 0.015 0.040 F IN. MM 0.110 0.140 G IN. MM 0.090 0.110 H IN. MM 0.300 0.370 J IN. MM 0.008 0.012 K IN. MM 0.015 0.
PAGE 15
DS1215 DS1215S SERIAL TIMEKEEPER 16–PIN SOIC K G B H 1 A C F phi E J L 16–PIN PKG DIM MIN MAX A IN. MM 0.402 10.21 0.412 10.46 B IN. MM 0.290 7.37 0.300 7.65 C IN. MM 0.089 2.26 0.095 2.41 E IN. MM 0.004 0.102 0.012 0.30 F IN. MM 0.094 2.38 0.105 2.68 G IN. MM 0.050 BSC 1.27 BSC H IN MM 0.398 10.11 0.416 10.57 J IN MM 0.009 0.229 0.013 0.33 K IN. MM 0.013 0.33 0.019 0.48 L IN MM 0.016 0.40 0.040 1.