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1 of 17 060800

FEATURES

§ Real-time clock (RTC) keeps track of hundredths

of seconds, seconds, minutes, hours, days, date,

months, and years with automatic leap-year

compensation valid up to the year 2100

§ 2M x 8 NV SRAM

§ Watch function is transparent to RAM operation

§ Automatic data protection during power loss

§ Unlimited write-cycle endurance

§ Surface-mountable BGA module construction

§ Over 10 years of data retention in the absence of

power

§ Battery monitor checks remaining capacity daily

§ +3.3V or +5V operation

PACKAGE OUTLINE

ORDERING INFORMATION

PART DESCRIPTION

DS1254X 2M x 8 NV SRAM with Phantom Clock

W +3.3V operation

Y +5.0V operation

PIN DESCRIPTION

- Supply Voltage

A0–A20 - Address Inputs

DQ0–DQ7 - Data I/O

CE - Chip Enable Input

OE - Output Enable Input

WE - Write Enable Input

BW - Battery Warning Output (Open Drain)

GND - Ground

Side -A - Shown

(For Reference Only, Not to Scale)

BGA Module Base

Bottom View

DS1254

2M x 8 NV SRAM with

Phantom Clock

www.maxim

ic.com

Summary of content (17 pages)

PAGE 1
DS1254 2M x 8 NV SRAM with Phantom Clock www.maxim-ic.
PAGE 2
DS1254 DESCRIPTION The DS1254 is a fully static nonvolatile RAM (NV SRAM) (organized as 2M works by 8 bits) with builtin real-time clock. It has a self-contained lithium energy source and control circuitry that constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the DS1254 makes use of an attached DS3800 battery cap to maintain clock information and preserve stored data while protecting that data by disallowing all memory accesses.
PAGE 3
DS1254 RAM READ MODE The DS1254 executes a read cycle whenever WE is inactive (high) and CE is active (low). The unique address specified by the 21 address inputs (A0–A20) defines which of the 2MB of data is to be accessed. Valid data will be available to the eight data-output drivers within tACC (Access Time) after the last address input is stable, providing that CE and OE access times and states are also satisfied.
PAGE 4
DS1254 advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for a total of 64 write cycles as described above until all the bits in the comparison register have been matched (this bit pattern is shown in Figure 2).
PAGE 5
DS1254 Figure 3.
PAGE 6
DS1254 AM/PM/12/24 MODE Bit 7 of the hours register is defined as the 12-hour or 24- hour mode select bit. When high, the 12- hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10- hour bit (20–23 hours). OSCILLATOR BIT Bit 5 of the day register controls the oscillator. When set to logic 1, the oscillator is off. When set to logic 0, the oscillator turns on and the watch becomes operational.
PAGE 7
DS1254 ABSOLUTE MAXIMUM RATINGS* Voltage Range on Any Pin Relative to Ground Operating Temperature Range Storage Temperature Range Soldering Temperature Range -0.3V to +6.0V 0°C to +70°C -40°C to +70°C See J-STD-020A specification * This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied.
PAGE 8
DS1254 (T A = +25°C) CAPACITANCE PARAMETER Input Capacitance: A0–A18, OE , WE , CE Input Capacitance: A19–A20 I/O Capacitance: DQ0–DQ7 Output Capacitance: BW SYMBOL MIN TYP MAX UNITS CIN 25 50 pF CIN CIO COUT 5 25 5 10 50 10 pF pF pF (0°C to +70 °C; V CC = 5.
PAGE 9
DS1254 ° AC ELECTRICAL CHARACTERISTICS PARAMETER Read Cycle Time Address Access Time OE to Output Valid CE to Output Valid CE or OE to Output Active Output High- Z from Deselection Output Hold from Address Change Write Cycle Time WE , CE Pulse Width Address Setup Time Address Hold Time Output High- Z from WE Output Active from WE Data Setup Time Data Hold Time Read Recovery (Clock Access Only) Write Recovery (Clock Access Only) ° (0 C to +70 C; V CC = 3.
PAGE 10
DS1254 Figure 4. MEMORY READ CYCLE TIMING (Note 9) tRC ADDRESS tACC tOH tCO CE tOD tOE OE tCOE tCOE tOD OUTPUT DATA VALID DQ0–DQ7 Figure 5.
PAGE 11
DS1254 Figure 6. MEMORY WRITE CYCLE TIMING, CHIP-ENABLE CONTROLLED (Notes 5, 7, 8, 10, 11, 12, and 13) tWC ADDRESS tAW tAH2 tWP CE WE tODW tCOE tDH2 tDS DQ0–DQ7 DATA IN STABLE Figure 7. READ CYCLE TO PHANTOM CLOCK tRC WE = V IH tRR tCO CE tOD tOE OE tCOE tCOE tOD OUTPUT DATA VALID DQ0 Figure 8.
PAGE 12
DS1254 Figure 9.
PAGE 13
DS1254 Figure 10. BATTERY WARNING DETECTION (Note 3) V CC tBPU V BAT 2.6V tBTC tBTPW BATTERY TEST ACTIVE tBW BW (0°C to +70 °C; V CC = 5.0V±10%) BATTERY WARNING TIMING PARAMETER Battery Test Cycle Battery Test Pulse Width Battery Test to BW Active VCC Valid to BW Valid SYMBOL tBTC tBTPW tBW tBPU MIN TYP 24 MAX 1 1 1 AC TEST CONDITIONS Output Load: 100pF + 1 TTL Gate Input Pulse Levels: 0.0V to 3.0V Timing Measurement Reference Levels: Input: 1.5V Output: 1.
PAGE 14
DS1254 NOTES: 1) Voltage referenced to ground. 2) These parameters are sampled with a 50pF load and are not 100% tested. 3) BW is an open-drain output and, as such, cannot source current. An external pullup resistor should be connected to this pin for proper operation. BW can sink 10mA. 4) The DS3800 battery cap is a one-time use part, but can be removed and replaced.
PAGE 15
DS1254 DS1254 PACKAGE DIMENSIONS 15 of 17 PKG MIN MAX A IN MM B IN MM C IN MM D IN MM E IN MM F IN MM G IN MM H IN MM I IN MM J IN MM K IN MM 1.570 39.88 1.570 39.88 0.033 0.84 1.497 38.02 0.047 1.19 0.033 0.84 0.047 1.19 0.234 5.94 0.125 3.10 0.025 0.64 1.580 40.13 1.580 40.13 0.043 1.09 1.503 38.18 0.053 1.35 0.043 1.09 0.053 1.35 0.240 6.10 0.135 3.43 ? ? 0.030 0.
PAGE 16
DS1254 DS1254 PACKAGE DIMENSIONS (WITH ATTACHED DS3800 BATTERY CAP) 16 of 17 PKG MIN MAX A IN MM B IN MM C IN MM 1.656 42.06 1.656 42.06 - 1.668 42.37 1.668 42.37 0.485 12.
PAGE 17
DS1254 DS1254 RECOMMENDED LAND PATTERN (With Overlaid Package Outline) The DS1254 ball grid array (BGA) is a subset of the industry-standard 40mm BGA format, with all balls on a 50mil grid. Corner balls have been removed to provide space for the electrical and mechanical interface features that facilitate attachment of the DS3800 Battery Cap. NOTE 0.250 0.500 0.150 Note: Ground shield to isolate RTC XTAL from EMI.