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DS1258Y/AB

128K x 16 Nonvolatile SRAM

DS1258Y/AB

PRODUCT PREVIEW

100395 1/9

FEATURES

• 10 year minimum data retention in the absence of

external power

• Data is automatically protected during a power loss

• Separate upper byte and lower byte chip select inputs

• Unlimited write cycles

• Low–power CMOS

• Read and write access times as fast as 70 ns

• Lithium energy source is electrically disconnected to

retain freshness until power is applied for the first time

• Full ±10% operating range (DS1258Y)

• Optional ±5% operating range (DS1258AB)

• Optional industrial temperature range of –40°C to

85°C, designated IND

PIN ASSIGNMENT

40–PIN ENCAPSULATED PACKAGE

740 MIL EXTENDED

CEU

CEL WE

A16DQ15

DQ14

DQ13

DQ11

DQ10

DQ9

DQ8

GND

DQ7

DQ5

DQ4

DQ12

DQ3

DQ2

DQ1

DQ0

DQ6

A15

A14

A13

A12

A11

A10

GND

PIN DESCRIPTION

A0–A16 – Address Inputs

DQ0–DQ15 – Data In/Data Out

CEU

– Chip Enable Upper Byte

CEL

– Chip Enable Lower Byte

– Write Enable

OE – Output Enable

– Power Supply (+5V)

GND – Ground

DESCRIPTION

The DS1258 128K x 16 Nonvolatile SRAMs are

2,097,152 bit fully static, nonvolatile SRAMs, organized

as 131,072 words by 16 bits. Each NV SRAM has a self

contained lithium energy source and control circuitry

which constantly monitors V

for an out–of–tolerance

condition. When such a condition occurs, the lithium

energy source is automatically switched on and write

protection is unconditionally enabled to prevent data

corruption. DIP–package DS1258 devices can be used

in place of solutions which build nonvolatile 128K x 16

memory by utilizing a variety of discrete components.

There is no limit to the number of write cycles which the

DS12658Y/AB can accept, and no additional support

circuitry is required for microprocessor interfacing.

Summary of content (9 pages)

PAGE 1
DS1258Y/AB PRODUCT PREVIEW DS1258Y/AB 128K x 16 Nonvolatile SRAM FEATURES PIN ASSIGNMENT • 10 year minimum data retention in the absence of external power • Data is automatically protected during a power loss • Separate upper byte and lower byte chip select inputs • Unlimited write cycles • Low–power CMOS • Read and write access times as fast as 70 ns • Lithium energy source is electrically disconnected to retain freshness until power is applied for the first time • Full ±10% operating range (DS1258
PAGE 2
DS1258Y/AB READ MODE WRITE MODE The DS1258 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and either/both of CEU or CEL (Chip Enables) are active (low) and OE (Output Enable) is active (low). The unique address specified by the 17 address inputs (A0–A16) defines which of the 131,072 words of data is accessed. The status of CEU and CEL determines whether all or part of the addressed word is accessed.
PAGE 3
DS1258Y/AB DATA RETENTION MODE The DS1258AB provides full functional capability for VCC greater than 4.75 volts, and write protects by 4.5 volts. The DS1258Y provides full functional capability for VCC greater than 4.5 volts and write protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static RAMs constantly monitor VCC.
PAGE 4
DS1258Y/AB ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature –0.3V to +7.0V 0°C to +70°C, –40°C to +85°C for IND parts –40°C to +70°C, –40°C to +85°C for IND parts 260°C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied.
PAGE 5
DS1258Y/AB (VCC=5V ± 5% for DS1258AB) (tA: See Note 10) (VCC=5V ± 10% for DS1258Y) AC ELECTRICAL CHARACTERISTICS PARAMETER DS1258Y–70 DS1258AB–70 SYMBOL MIN MAX 70 DS1258Y–100 DS1258AB–100 MIN UNITS NOTES MAX Read Cycle Time tRC 100 ns Access Time tACC 70 100 ns OE to Output Valid tOE 35 50 ns 100 ns CE to Output Valid tCO OE or CE to Output Valid tCOE 70 Output High Z from Deselection tOD Output Hold from Address Change tOH 5 5 ns Write Cycle Time tWC 70 100 ns
PAGE 6
DS1258Y/AB WRITE CYCLE 1 tWC ADDRESSES VIH VIL VIH VIL VIH VIL tAW CEU, CEL VIL VIL tWP tWR1 WE VIH VIH VIL VIL tOEW tODW HIGH IMPEDANCE DOUT tDS tDH1 VIH VIH DIN DATA IN STABLE VIL VIL SEE NOTES 2, 3, 4, 6, 7, 8 AND 12 WRITE CYCLE 2 tWC ADDRESSES VIH VIH VIH VIL VIL VIL tAW CEU, CEL tWP tWR2 VIH VIH VIL VIL VIL VIH WE VIL VIL tCOE tODW DOUT tDS tDH2 VIH VIL SEE NOTES 2, 3, 4, 6, 7 AND 13 100395 6/9 VIH DATA IN STABLE DIN VIL
PAGE 7
DS1258Y/AB POWER-DOWN/POWER-UP CONDITION VCC DS1230Y 4.50V DS1230AB 4.75V 3.
PAGE 8
DS1258Y/AB 4. tDS is measured from the earlier of CEU or CEL or WE going high. 5. These parameters are sampled with a 5 pF load and are not 100% tested. 6. If the CEU or CEL low transition occurs simultaneously with or later than the WE low transition in the output buffers remain in a high impedance state during this period. 7. If the CEU or CEL high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in high impedance state during this period. 8.
PAGE 9
DS1258Y/AB DS1258Y/AB NONVOLATILE SRAM 40–PIN 740 MIL EXTENDED MODULE PKG 1 A C F D K G 40-PIN DIM MIN MAX A IN. MM 2.080 52.83 2.100 53.34 B IN. MM 0.715 18.16 0.740 18.80 C IN. MM 0.345 8.76 0.365 9.27 D IN. MM 0.085 2.16 0.115 2.92 E IN. MM 0.015 0.38 0.030 0.76 F IN. MM 0.120 3.05 0.160 4.06 G IN. MM 0.090 2.29 0.110 2.79 H IN. MM 0.590 14.99 0.630 16.00 J IN. MM 0.008 0.20 0.012 0.30 K IN. MM 0.015 0.43 0.025 0.