DS1315 PRELIMINARY DS1315 Phantom Time Chip FEATURES PIN ASSIGNMENT • Real time clock keeps track of hundredths of seconds, seconds, minutes, hours, days, date of the month, months, and years • Adjusts for months with fewer than 31 days • Automatic leap year correction valid up to 2100 X1 1 16 VCCI X2 2 15 VCCO WE 3 14 BAT2 BAT1 4 13 RST GND 5 12 OE D 6 11 CEI Q 7 10 CEO GND 8 9 • No address space required to communicate with RTC • Provides nonvolatile controller funct
DS1315 PIN DESCRIPTION X1, X2 WE BAT1 GND D Q ROM/RAM CEO CEI OE RST BAT2 VCCO VCCI – – – – – – – – – – – – – – In the absence of power, an external battery maintains the timekeeping operation and provides power for a CMOS static RAM. The watch keeps track of hundredths of seconds, seconds, minutes, hours, day, date, month, and year information. The last day of the month is automatically adjusted for months with less than 31 days, including leap year correction.
DS1315 Communication with the Time Chip is established by pattern recognition of a serial bit stream of 64 bits which must be matched by executing 64 consecutive write cycles containing the proper data on data in (D). All accesses which occur prior to recognition of the 64–bit pattern are directed to memory via the chip enable output pin (CEO).
DS1315 TIME CHIP COMPARISON REGISTER DEFINITION Figure 2 BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 BYTE 7 7 6 5 4 3 2 1 0 1 1 0 0 0 1 0 1 C5 0 0 1 1 1 0 1 0 3A 1 0 1 0 0 0 1 1 A3 0 1 0 1 1 1 0 0 5C 1 1 0 0 0 1 0 1 C5 0 0 1 1 1 0 1 0 3A 1 0 1 0 0 0 1 1 A3 0 1 0 1 1 1 0 0 5C NOTE: The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C.
DS1315 power fails. However, the Time Chip does retain the same internal nonvolatility and write protection as described in the RAM mode. A typical ROM/Time Chip interface is illustrated in Figure 4. When the ROM/RAM pin is connected to VCCO, the controller is set in the ROM mode. Since ROM is a read– only device that retains data in the absence of power, battery backup and write protection is not required.
DS1315 ROM/TIME CHIP INTERFACE Figure 4 ROM VCC A1, A3 – AN A0 – AN VCC DATA I/O D0 – D7 A2 OE OE A0 CE DS1315 D CEO OE Q WE VCCI CEI CE RST RST + BAT1 X1 VCC VCCO ROM/ RAM BAT2 X2 + BAT2 BAT1 32.768 KHz TIME CHIP REGISTER INFORMATION Time Chip information is contained in eight registers of 8 bits, each of which is sequentially accessed one bit at a time after the 64–bit pattern recognition sequence has been completed.
DS1315 TIME CHIP REGISTER DEFINITION Figure 5 REGISTER RANGE (BCD) 7 6 0 5 4 3 0.1 SEC 2 1 0.
DS1315 ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground Operating Temperature, commercial range Operating Temperature, industrial range Storage Temperature Soldering Temperature –0.3V to +7.0V 0°C to 70°C –45°C to +85°C –55°C to +125°C 260°C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied.
DS1315 (0°C to 70°C; VCC < 4.5V) DC POWER DOWN ELECTRICAL CHARACTERISTICS PARAMETER CEO Output Voltage VBAT1 or VBAT2 Battery Current Battery Backup Current @ VCCO = VBAT–0.2V SYMBOL MIN VCEO VCCI–0.2 or VBAT1,2 –0.2 TYP UNITS NOTES V 8 IBAT 0.5 µA 6 ICCO2 10 µA 9 AC ELECTRICAL OPERATING CHARACTERISTICS ROM/RAM = GND PARAMETER MAX (0°C to 70°C; VCC = 5.
DS1315 AC ELECTRICAL OPERATING CHARACTERISTICS ROM/RAM = VCCO PARAMETER (0°C to 70°C; VCC = 5.
DS1315 DC OPERATING ELECTRICAL CHARACTERISTICS (cont’d) PARAMETER SYMBOL MIN Output Logic 1 Voltage (IOUT = 0.4 mA) VOH 2.4 Output Logic 0 Voltage (IOUT = 1.6 mA) VOL Power–Fail Trip Point VPF Battery Switch Voltage VSW TYP 2.8 (0°C to 70°C; VCC = 3.3 ±10%) MAX UNITS NOTES V 2 0.4 V 2 3.0 V VBAT1, VBAT2 13 (0°C to 70°C; VCC < 2.7V) DC POWER DOWN ELECTRICAL CHARACTERISTICS PARAMETER CEO Output Voltage VBAT1 or VBAT2 Battery Current Battery Backup Current @ VCCO = VBAT –0.
DS1315 AC ELECTRICAL OPERATING CHARACTERISTICS ROM/RAM = GND PARAMETER (0°C to 70°C; VCC = 3.
DS1315 AC ELECTRICAL OPERATING CHARACTERISTICS ROM/RAM = VCCO PARAMETER (0°C to 70°C; VCC = 3.
DS1315 TIMING DIAGRAM: READ CYCLE TO TIME CHIP ROM/RAM = GND Figure 6 WE = VIH tRC CEI tRR tCO tCW tOD tOE OE tOW tOEE tODO ÉÉÉ ÉÉÉ tCOE Q OUTPUT DATA VALID ÉÉÉ ÉÉÉ TIMING DIAGRAM: WRITE CYCLE TO TIME CHIP ROM/RAM = GND Figure 7 OE = VIH tWC WE tWR tWP tWR CEI tCW tDH ÉÉÉÉÉ ÉÉÉÉÉ D 041697 14/22 tDS DATA IN STABLE tDH ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ
DS1315 TIMING DIAGRAM: READ CYCLE TO TIME CHIP ROM/RAM = VCCO Figure 8 ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÉÉÉÉÉ ÉÉÉÉÉ tRC tCO tRR CEI tCW tOD tRR tRC tOE OE tOW tODO tAS tAS tAH tAH WE tOEE tCOE Q OUTPUT DATA VALID TIMING DIAGRAM: WRITE CYCLE TO TIME CHIP ROM/RAM = VCCO Figure 9 tWC ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ tWR tCW CEI tWR tWC tOW OE tAS tAH tAS tAH WE D tDH tDS tDS tDH DATA IN STABLE 041697 15/22
DS1315 TIMING DIAGRAM: RESET PULSE Figure 10 tRST RST 5V DEVICE POWER–UP POWER–DOWN CHARACTERISTICS, ROM/RAM = VCCO OR GND PARAMETER SYMBOL Recovery Time at Power–Up tREC VCC>4.5 MIN TYP (0°C to 70°C) MAX UNITS NOTES 2 mS 11 VCC Slew Rate Power– Down tF 4.0 ≤ VCC ≤ 4.5 300 mS 11 VCC Slew Rate Power– Down tFB 3.0 ≤ VCC ≤ 4.0 10 mS 11 VCC Slew Rate Power– UP tR 4.5 ≤ VCC ≤ 4.
DS1315 5V DEVICE POWER–DOWN CONDITION Figure 12 ÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇ tCE CEI tPF tPD VBAT - 0.2V ROM/RAM = GND CEO ROM/RAM = VCCO CEO tCE VCCI 4.5V 4.25V 4.0V tF VBAT1,2 tFB 3.3V DEVICE POWER–UP POWER–DOWN CHARACTERISTICS, ROM/RAM = VCCO OR GND PARAMETER Recovery Time at Power–Up SYMBOL MIN tREC VCC>3 TYP (0°C to 70°C) MAX UNITS NOTES 2 ms 12 VCC Slew Rate Power– Down tF 2.9 ≤ VCC ≤ 3 300 ms 12 VCC Slew Rate Power– UP tR 3 ≤ VCC ≤ 2.
DS1315 ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ 3.3V DEVICE POWER–UP CONDITION Figure 13 tCE CEI VIL tREC 2.7V 2.6V 2.5V tR VCCI tPD BAT - 0.2V ROM/RAM = GND CEO ROM/RAM = VCCO CEO tCE 3.3V DEVICE POWER–DOWN CONDITION Figure 14 tCE CEI ÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇ tPF tPD VBAT - 0.2V ROM/RAM = GND CEO ROM/RAM = VCCO CEO tCE VCCI 2.7V 2.6V 2.
DS1315 NOTES: 1. All voltages are referenced to ground. 2. Measured with load shown in Figure 15. 3. Input pulse rise and fall times equal 10 ns. 4. tWR is a function of the latter occurring edge of WE or CE in RAM mode, or OE or CE in ROM mode. 5. tDH and tDS are functions of the first occurring edge of WE or CE in RAM mode, or OE or CE in ROM mode. 6. Measured without RAM connected. 7. ICC01 is the maximum average load current the DS1315 can supply to external memory. 8.
DS1315 DS1315 TIME CHIP 16–PIN DIP B D J H 1 A PKG C F K E G 041697 20/22 16–PIN DIM MIN MAX A IN. MM 0.740 0.780 B IN. MM 0.240 0.260 C IN. MM 0.120 0.140 D IN. MM 0.300 0.325 E IN. MM 0.015 0.040 F IN. MM 0.110 0.140 G IN. MM 0.090 0.110 H IN. MM 0.300 0.370 J IN. MM 0.008 0.012 K IN. MM 0.015 0.
DS1315 DS1315 TIME CHIP 16–PIN SOIC K G B H 1 A C F phi E PKG L 16–PIN DIM MIN MAX A IN. MM 0.402 10.21 0.412 10.46 B IN. MM 0.290 7.37 0.300 7.65 C IN. MM 0.089 2.26 0.095 2.41 E IN. MM 0.004 0.102 0.012 0.30 F IN. MM 0.094 2.38 0.105 2.68 G IN. MM J 0.050 BSC 1.27 BSC H IN MM 0.398 10.11 0.416 10.57 J IN MM 0.009 0.229 0.013 0.33 K IN. MM 0.013 0.33 0.019 0.48 L IN MM 0.016 0.40 0.040 1.
DS1315 DS1315 TIME CHIP 20–PIN TSSOP D n E H SEE DETAIL A c B e1 A2 A A1 phi L DETAIL A DIM MIN MAX A MM – 1.10 A1 MM 0.05 – A2 MM 0.75 1.05 C MM 0.09 0.18 L MM 0.50 0.70 e1 MM 0.65 BSC B MM 0.18 0.30 D MM 6.40 6.90 E MM 4.40 NOM G MM 0.25 REF H MM 6.25 6.
