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1 of 17 091300

FEATURES

 Keeps track of hundredths of seconds,

seconds, minutes, hours, days, date of the

month, months, and years with leap year

compensation valid up to 2100

 Watchdog timer restarts an out-of-control

processor

 Alarm function schedules real-time related

activities

 Programmable interrupts and square wave

outputs

 Bytewide RAM-like access

 50 bytes of on board user RAM

 Greater than 10 years timekeeping and data

retention in the absence of power with small

lithium coin cells

 Supports up to 128k x 8 of external static RAM

 All timekeeping registers and on board RAM

are individually addressable via the address

and data bus

ORDERING INFORMATION

DS 1384FP-12 44-Pin FP

PIN ASSIGNMENT

PIN DESCRIPTION

INTA - Interrupt Output A (open drain)

INTB (INTB) - Interrupt Output B (open drain)

A0-A16 - Address Inputs

DQ0-DQ7 - Data Input/Output

CE - Chip Enable

OE - Output Enable

WE - Write Enable

- +5V Input

GND - Ground

NC - No Connection

SQW - Square Wave Output

X1, X2 - 32.768 kHz Crystal Connections

PFO - Power Fail Output

CEO - Chip Enable RAM

OER - Output Enable RAM

CCO

- Voltage Out

BAT1

- +3V Battery Input

BAT2

- +3V Battery Input

DS1384

Watchdog Timekeeping Controlle

www.dalsemi.com

INTB/

(

INTB

)

A14

A12

A15

BAT1

A13

A11

A10

GND

CEO

GND

A16

INTA

CCO

SQW

PF0

BAT2

44 34

Summary of content (17 pages)

PAGE 1
DS1384 Watchdog Timekeeping Controller www.dalsemi.
PAGE 2
DS1384 DESCRIPTION The DS1384 Watchdog Timekeeping Controller is a self-contained real time clock, alarm, watchdog timer, and interval timer which provides control of up to 128k x 8 of external low power CMOS static RAM in a 44-pin quad flat pack package. An external crystal and battery are the only components required to maintain time of day and RAM memory contents in the absence of power. Access to all RTC functions and the external RAM is the same as conventional bytewide SRAM.
PAGE 3
DS1384 VCCO - Switched DC power for SRAM (output): This pin will be connected to VCC when VCC voltage is above VSO (the greater of VBAT1 or VBAT2). When VCC voltage falls below this level, VCCO will be connected to the higher voltage battery pin. CEO - RAM chip enable (output; active low): When power is good the CE input will be passed through to CEO . If VCC is below VPF, CEO will remain at an inactive high level.
PAGE 4
DS1384 For more information on crystal selection and crystal layout considerations, please consult Application Note 58, “Crystal Considerations with Dallas Real Time Clocks.” SQW - Square Wave (output): This pin can be programmed to output a 1024 Hz square wave signal. When the signal is turned off, the pin is high Z. PFO - Power Fail Signal (output; active low when VWP occurs): High state occurs tREC after power-up and VCC >4.5 volts.
PAGE 5
DS1384 When the address value presented to the DS1384 during the write is in the range of 00000H through 0003FH, one of the 64 on-chip registers will be selected and data will be written into the device. When the address value presented to the DS1384 during the write is in the range of 00040H through 1FFFFH, an external SRAM location will be selected. DATA RETENTION MODE When VCCI is within nominal limits (VCC > 4.5 volts) the DS1384 can be accessed as described above with read or write cycles.
PAGE 6
DS1384 DS1384 BLOCK DIAGRAM Figure 1 6 of 17
PAGE 7
DS1384 DS1384 WATCHDOG TIMEKEEPER REGISTERS Figure 2 7 of 17
PAGE 8
DS1384 TIME OF DAY ALARM MASK BITS Figure 3 REGISTER MINUTES HOURS 1 1 0 1 0 0 0 0 DAYS 1 1 1 0 ALARM ONCE PER MINUTE ALARM WHEN MINUTES MATCH ALARM WHEN HOURS AND MINUTES MATCH ALARM WHEN HOURS, MINUTES, AND DAYS MATCH NOTE: ANY OTHER BIT COMBINATIONS OF MASK BIT SETTINGS PRODUCE ILLOGICAL OPERATION. TIME OF DAY REGISTERS Registers 0, 1, 2, 4, 6, 8, 9 and A contain time of day data in BCD. Ten bits within these eight registers are not used and will always read 0 regardless of how they are written.
PAGE 9
DS1384 TIME OF DAY ALARM REGISTERS Registers 3, 5, and 7 contain the time of day alarm registers. Bits 3, 4, 5, and 6 of register 7 will always read 0 regardless of how they are written. Bit 7 of registers 3, 5, and 7 are mask bits (Figure 3). When all of the mask bits are logic 0, a time of day alarm will only occur when registers 2, 4, and 6 match the values stored in registers 3, 5, and 7. An alarm will be generated every day when bit 7 of register 7 is set to a logic 1.
PAGE 10
DS1384 WAM - Bit 3 Watchdog Alarm Mask - When this bit is set to a logic 0, the Watchdog Interrupt output will be activated. The activated state is determined by bits 1,4,5, and 6 of the Command Register. When this bit is set to a logic 1, the Watchdog interrupt output is deactivated. TDM - Bit 2 Time of Day Alarm Mask - When this bit is set to a logic 0, the Time of Day Alarm Interrupt output will be activated. The activated state is determined by bits 0, 4, 5, and 6 of the Command Register.
PAGE 11
DS1384 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -0.3V to +7.0V 0°C to 70°C -20°C to +70°C See J-STD-020A Specification ✻ This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
PAGE 12
DS1384 AC ELECTRICAL CHARACTERISTICS PARAMETER Read Cycle Time Address Access Time CE Access Time CE Data Off Time Output Enable Access Time Output Enable Data Off Time Output Enable to DQ Low-Z CE to DQ Low-Z Output Hold from Address CE to CEO Low or High OE Low to OER Low A0-A16 > 00040h OE High to OER High Time Address 00040h-1FFFFh to OER Low Address 00000h-0003Fh to OER High Write Cycle Time Address Setup Time CE Pulse Width Address Hold from End of Write Write Pulse Width CE Data Off Time WE Data Off
PAGE 13
DS1384 CAPACITANCE PARAMETER Capacitance on all pins (except DQ) Capacitance on DQ pins (tA = 25°C) SYMBOL CI MIN CDQ TYP 7 MAX 15 UNITS pF 7 15 pF AC ELECTRICAL CHARACTERISTICS PARAMETER CE at VIH before Power Down VPF (Max) to VPF (Min) VCC Fall Time VPF (Min) to VSO VCC Fall Time VPF (Min) to VPF (Max) VCC Rise Time Power Up Expected Data Retention Time (Oscillator On) NOTES (0°C to 70°C) SYMBOL tPD MIN 0 TYP MAX tF 300 µs tFB 10 µs tR 0 µs tREC tDR 10 10 150 UNITS µs ms ye
PAGE 14
DS1384 OER TIMING WHEN SWITCHING BETWEEN LOWER MEMORY (00000h- 0003Fh) AND UPPER MEMORY (00040h-1FFFFh) WRITE CYCLE TIMING: RTC AND EXTERNAL SRAM CONTROL SIGNALS 14 of 17
PAGE 15
DS1384 TIMING DIAGRAM: POWER UP TIMING DIAGRAM: POWER DOWN 15 of 17
PAGE 16
DS1384 TIMING DIAGRAM: INTERRUPT OUTPUTS PULSE MODE (SEE NOTES 8, 9) NOTES: 1. All voltages are referenced to ground. 2. Typical values are at 25°C and nominal supplies. 3. Outputs are open. 4. Value for voltage and currents is from the VCCI input pin to the VCCO pin. 5. Write protection trip point occurs during power fail prior to switchover from VCC to VBAT. 6. Value for voltage and currents is from the VBAT input pin to the VCCO pin. 7.
PAGE 17
DS1384 DS1384 FP PACKAGE OUTLINES NOTES: 1. DIMENSIONS D1 AND E1 INCLUDE MOLD MISMATCH, BUT DO NOT INCLUDE MOLD PROTRUSION; ALLOWABLE PROTRUSION IS 0.25 MM PER SIDE. 2. DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. 3. ALLOWABLE DAMPER PROTRUSION IS 0.08 MM TOTAL IN EXCESS OF THE B DIMENSION; AT MAXIMUM MATERIAL CONDITION. PROTRUSION NOT TO BE LOCATED ON LOWER RADIUS OF FOOT OF LEAD. 4. CONTROLLING DIMENSIONS: MILLIMETERS. PKG DS1384FP DIM MIN MAX A 2.45 A1 0.10 0.