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DS1667

Digital Resistor with OP AMP

DS1667

021492 1/11

FEATURES

• Two digitally controlled 256-position potentiometers

• Serial port provides means for setting and reading

both potentiometers

• Resistors can be connected in series to provide addi-

tional resolution

• Default wiper position on power up is 50%

• Resistive elements are temperature compensated to

20% end to end

• Two high gain wide bandwidth operational amplifiers

• Low power CMOS design

• Applications include analog–to–digital and digital–to–

analog converters, variable oscillators, and variable

gain amplifiers

• 20–pin DIP package or optional 20–pin SOIC surface

mount package

• Operating temperature range of 0°C to 70°C

• Resistance Values

RESOLUTION -3 dB POINT

DS1667-10: 10K 39 ohms 1.1 MHz

DS1667-50: 50K 195 ohms 200 kHz

DS1667-100: 100K 390 ohms 100 kHz

PIN ASSIGNMENT

OUT0

SOUT

COUT

INVI

NINVI

NINV0

INV0

RST

CLK

OUT1

GND

20-Pin DIP (300 Mil) and 20-Pin SOIC

PIN DESCRIPTION

- +5 Volt Supply

GND - Ground

L0, L1 - Low End of Resistor

H0, H1 - High End of Resistor

W0, W1 - Wiper End of Resistor

- Substrate Bias and OP AMP

Negative Supply

SOUT - Wiper for Stacked

Configuration

RST

- Serial Port Reset Input

DQ - Serial Port Input/Output

CLK - Serial Port Clock Input

COUT - Cascade Serial Port Output

NINV0, NINVI - Noninverting OP AMP Input

INV0, INVI - Inverting OP AMP Input

OUT0, OUT1 - OP AMP Outputs

DESCRIPTION

The DS1667 is a dual–solid state potentiometer that is

adjustable by digitally selected resistive elements.

Each potentiometer is composed of 256 resistive ele-

ments. Between each resistive section of each poten-

tiometer are tap points accessible to the wiper. The po-

sition of the wiper on the resistive array is set by an 8–bit

wiper output. Each 8–bit register can be read or written

by sending or receiving data bits over a 3–wire serial

port. In addition, the resistors can be stacked such that

a single potentiometer of 512 sections results. When

two separate potentiometers are used, the resolution of

the DS1667 is equal to the resistance value divided by

256. When the potentiometers are stacked end to end,

the resistance value is doubled while the resolution re-

mains the same. The DS1667 also contains two high

gain wide bandwidth operational amplifiers. Each am-

plifier has both the inverting and non-inverting inputs

and the output available for user configuration. The op-

erational amplifiers can be paired with the resistive ele-

Summary of content (11 pages)

PAGE 1
DS1667 DS1667 Digital Resistor with OP AMP FEATURES PIN ASSIGNMENT • Two digitally controlled 256-position potentiometers NINV0 1 20 VCC port provides means for setting and reading both potentiometers INV0 2 19 OUT0 VB 3 18 SOUT • Resistors can be connected in series to provide addi- W1 4 17 W0 H1 5 16 H0 L1 6 15 L0 RST 7 14 COUT CLK 8 13 DQ OUT1 9 12 INVI GND 10 11 NINVI • Serial tional resolution • Default wiper position on power up is 50% • Resistive elemen
PAGE 2
DS1667 ments to perform such functions as analog to digital conversion, digital to analog conversion, variable gain amplifiers, and variable oscillators. tiometer 0 is connected to the low end of potentiometer 1. When stacking potentiometers, the stack select bit is used to select which potentiometer wiper will appear at the stack multiplexer output (SOUT). A zero written to the stack multiplexer will connect wiper 0 to the SOUT pin.
PAGE 3
DS1667 Information is written to and read from the wiper 0 and wiper 1 registers and the stack select bit via the 17-bit I/O shift register. The I/O shift register is serially loaded by a 3 wire serial port consisting of RST, DQ, and CLK. It is updated by transferring all 17 bits (Figure 2). Data can be entered into the 17 bit shift register only when the RST input is at a high level. While at a high level, the RST function allows serial entry of data via the D/Q pin.
PAGE 4
DS1667 WRITING DATA Figure 2 RST DQ DON’T CARE BIT 16 BIT 15 BIT 14 BIT 0 DON’T CARE CLK PREVIOUS CONTROL REG. I/O SR WIPER 0 & 1 STACK SELECT +0 +0, 1 NEW CONTROL REG.
PAGE 5
DS1667 READING DATA Figure 4 RST COUT BIT 16 BIT 15 BIT 14 BIT 0 BIT 16 CLK CONTROL REGISTERS NO CHANGES CURRENT SETTINGS DS1667 LINEARITY MEASUREMENTS An important specification for the DS1667 is linearity, that is, for a given digital input, how close the analog output is to that which is expected. The test circuit used to measure the linearity of the DS1667 is shown in Figure 5.
PAGE 6
DS1667 LINEARITY MEASUREMENT CONFIGURATION Figure 5 X = 0 X = 1 +5V HX POTX WX RWX LX + –5V V0 I0 = 0 – DS1667 ABSOLUTE AND RELATIVE LINEARITY Figure 6 021492 6/11 POT0 POT1
PAGE 7
DS1667 TIMING DIAGRAM: RESISTOR SECTION Figure 7 RST tHHT tHLT tW tW CLK tH tH tSU DQ INPUTS tSU tPLH COUT 021492 7/11
PAGE 8
DS1667 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground (VB = GND) Voltage on Resistor Pins when VB = -5.5V Voltage on VB Operating Temperature Storage Temperature Soldering Temperature –0.5V to +7.0V -5.5V to +7.0V -5.5V to GND 0°C to 70°C –55°C to +125°C 260°C for 10 seconds *This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied.
PAGE 9
DS1667 (tA = 25°C) CAPACITANCE PARAMETER Input Capacitance Output Capacitance SYMBOL MIN TYP MAX UNITS CIN 5 pF COUT 7 pF AC ELECTRICAL CHARACTERISTICS RESISTOR SECTION PARAMETER CLK Frequency SYMBOL MIN TYP fCLK (0°C to 70°C, VCC = 5V ± 10%) MAX UNITS 10 MHz Width of CLK Pulse tW 50 ns Data Setup Time tSU 30 ns Data Hold Time tH 10 ns Propagation Delay Time Low to High Level Clock to Output tPLH RST High to Clock Input High tHHT 50 ns RST Low from Clock Input High
PAGE 10
DS1667 OPERATIONAL AMPLIFIER SECTION AC ELECTRICAL CHARACTERISTICS PARAMETER (0°C to 70°C; VCC = 5.0V ± 10%) SYMBOL MIN TYP Slew Rate VSL 0.7 Gain Bandwidth Product UNITS NOTES 2 V/µs 6 GBP 2.5 MHz 5 Phase Margin PM 75 deg 5 Gain Margin GM 20 dB 5 Amp–to–Amp Isolation AAI 130 dB Input Referred Voltage Noise IRVF 100 nVń ǸHz F=1 KHz Input Referred Current Noise IRV1 .0002 pAń ǸHz F=1 KHz HD 0.
PAGE 11
DS1667 LOAD SCHEMATIC Figure 8 +5 VOLTS 1.1K D.U.T.