DS1678 Real-Time Event Recorder www.maxim-ic.
DS1678 DESCRIPTION The DS1678 Real-Time Clock Event Recorder records the time and date of a non-periodic, asynchronous event each time the INT pin is activated. The device records the seconds, minutes, hours, date, day of the week, month, year, and century when the first event occurs. Subsequent events trigger the recording of the 16-bit elapsed time counter (ETC) into the 2048 bytes of event log memory. This allows for up to 1025 events to be logged.
DS1678 The block diagram in Figure 1 shows the main elements of the RTC event recorder. The device has four major components: 1) 64-bit RTC and control block, 2) 32-byte user NV RAM, 3) 2048 bytes of event log memory (1024 events), and 4) 2-wire serial interface.
DS1678 DS1678 BLOCK DIAGRAM Figure 1 32.768 kHz X1 X2 OSCILLATOR AND DIVIDER INT SCL SDA VCC VBAT CONTROL LOGIC RTC ADDRESS REGISTER USER RAM DATA LOG RAM PORT 2-WIRE SERIAL INTERFACE DATA LOG NV SRAM POWER CONTROL GND SIGNAL DESCRIPTIONS The following paragraphs describe the function of each pin. VCC – VCC is a +5V input supply. Communication with the DS1678 can take place only when VCC is connected to a +5V supply. VBAT – Battery input for standard lithium cell or other energy source.
DS1678 INT (Interrupt Input/Output) – The INT pin is an I/O that will be activated by an external device to signify an event has occurred and should be logged. Once the pin is activated, the event will be recorded in the event log memory and the event counter register will be incremented by one. The INT pin can be activated in three different ways depending on how the user programs the TRx bits.
DS1678 CLOCK ACCURACY The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error will be added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit may result in the clock running fast.
DS1678 Entering a value greater than 07FFh will result in the address location associated with the value of the lowest 11 bits of the address. The RTC and control registers (See Figure 2a for more detail.) are located in the main memory between addresses 00h and 0Fh. The user NV RAM resides in locations 10h through 2Fh. The event logging memory data port is located at locations 41h, 42h, and 43h. Memory locations 44h and up are reserved for future extensions and will read 00h.
DS1678 DS1678 RTC AND CONTROL PAGE Figure 2a ADDRESS 00 01 02 BIT 7 0 0 03 04 05 06 07 08 09 0 0 0 MS MM 0A MH 0B 0C 0D 0E MD 0F 0 10 11 12 ↓ 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 ↓ FF 0 ME BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 10 SECONDS SECONDS 10 MINUTES MINUTES AM/PM HOUR 12/24 10 HR 10 HR 0 0 0 0 DAY OF WEEK 0 10 DATE DATE 0 0 10 MO MONTH 10 YEAR YEAR 10 CENTURY CENTURY 10 SECONDS ALARM SECONDS ALARM 10 MINUTES ALARM MINUTES ALARM AM/PM 12/24 10 HR HOUR A
DS1678 DS1678 EVENT ELAPSED TIME DURATION Figure 2b ADDRESS 0000 0001 0002 0003 0004 ¯ 07FB 07FC 07FD 07FE 07FF REGISTER Event 1 Elapsed Time from Last Event Counter LSB Event 1 Elapsed Time from Last Event Counter MSB Event 2 Elapsed Time from Last Event Counter LSB Event 2 Elapsed Time from Last Event Counter MSB ¯ Event 1023 Elapsed Time from Last Event Counter LSB Event 1023 Elapsed Time from Last Event Counter MSB Event 1024 Elapsed Time from Last Event Counter LSB Event 1024 Elapsed Time from Last E
DS1678 once any events that are being recorded have completed. The value in the MIP and ME bits will remain a 1 until the mission has completed, even if they are written to a 0. Upon initiation of an event log mission by either method, the DS1678 will set the Mission-in-Progress (MIP) bit in the Control register to a one. It should be noted that the MEM CLR bit of the Status register must be a one in order to start an event log mission.
DS1678 written to the two event 0 elapsed time from last event registers, the subsequent event log will be written to address locations 0000h and 0001h, and the address pointer will be incremented with each successive data sample. When this rollover occurs, the roll over flag (ROF) in the control register will be set to one to indicate that the memory has rolled over at least one time.
DS1678 TIME-OF-DAY ALARM BITS Table 1 ALARM REGISTER MASK BITS (bit 7) SECONDS MINUTES HOURS DAYS (MS) (MM) (MH) (MD) 1 1 1 1 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0 ALARM ONCE PER SECOND ALARM WHEN SECONDS MATCH ALARM WHEN MINUTES AND SECONDS MATCH ALARM WHEN HOURS, MINUTES, AND SECONDS MATCH ALARM WHEN DAY, HOURS, MINUTES, AND SECONDS MATCH The DS1678 also contains a time-of-day alarm. The alarm registers are located in registers 08h to 0Bh.
DS1678 CLR - Clear Enable – This bit enables the memory to be cleared. When this bit is set to a one and the clear memory (CM) bit in the status register is subsequently written to a 1, the event log memory, event count, and start time stamp registers are all cleared to zeros. Following the writing of a 1 to the ME bit, the CLR bit is also cleared to zero.
DS1678 With the DIS0 bit set to a zero and the DIS1 bit set to a one, the ETC will increment every time the single minutes byte in the RTC is incremented. This will give a medium resolution between events, but will increase the largest possible interval between events that can be accurately measured without using additional memory space and reducing the total number of events able to be logged to 65,535 minutes or about 45.5 days. If the maximum time between events could be greater than 45.
DS1678 locations 0000h and 0001h, overwriting the original data. Likewise, subsequent samples will increment through the event log registers, overwriting their data. The event 0 elapsed time from last event bytes will have the elapsed time since the last event in the event log memory. This is to allow the user to recover the information prior to the rollover. At the start of a mission, the value in these 2 bytes will be all zeros since there was no previous event from which to have an elapsed time.
DS1678 MIP - Mission in Progress – This bit indicates the sampling status of the DS1678. If MIP is logic 1, the device is currently on a “mission” in which it is operating in the event logging mode. The MIP bit is changed to logic 1 immediately following the activation of the INT pin if the ME bit of the control register contains a 1.
DS1678 MSB (40h). These will be helpful in recovering all of the data if a rollover occurs. The address pointer will point to the oldest event in the memory after a rollover. This is the memory location that would be over written by the next event. Read the data from this point to the end of the memory and the start time stamp including the 2-byte ETC from last event in order to recover all of the data in the correct order.
DS1678 and generates the START and STOP conditions. The DS1678 operates as a slave on the 2-wire bus. Connections to the bus are made via the open-drain I/O lines SDA and SCL. The following bus protocol has been defined (See Figure 3): § Data transfer may be initiated only when the bus is not busy. § During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is high will be interpreted as control signals.
DS1678 Figure 4 details how data transfer is accomplished on the 2-wire bus. Depending upon the state of the R/ W bit, two types of data transfer are possible: 1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. 2. Data transfer from a slave transmitter to a master receiver.
DS1678 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -0.3V to +6V -40°C to +85°C -55°C to +125°C See J-STD-020A specification * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
DS1678 AC ELECTRICAL CHARACTERISTICS PARAMETER SCL Clock Frequency SYMBOL fscl Bus Free Time Between a STOP and START Condition Hold Time (Repeated) START Condition.
DS1678 2-WIRE SERIAL COMMUNICATION WITH DS1678 Figure 4 W rite to M e m o ry A d d re s s P o in te r SCL S SDA 1 S ta rt 0 0 1 0 1 0 W A7 A D S 16 78 D e vic e A d d re s s B y te A6 A5 A4 A3 A2 A1 A0 P D S 1 67 8 S to p M e m o ry A d d re s s B yte ACK A ACK W rite to M e m o ry L o c a tio n (S in g le B y te ) SCL SDA S 1 S ta rt 0 0 1 0 1 0 A W A7 D S 16 78 D e v ic e A d d re s s B y te A6 A5 A4 A3 A2 A1 M e m o ry A d d re s s B yte ACK A0 A D7
DS1678 EVENT RECOGNITION TIMING DIAGRAM Figure 6a G o od E ven ts tE VE NT /IN T t G L IT C H T ra nsitio n P oin t E ven t 1 E ven t 2 B a d E ven t 1 /IN T t G L IT C H T ra nsitio n P oin t B a d E ven t 2 tE VE NT /IN T T ra nsitio n P oin t E ven t 1 E ven t 2 is m issed EVENT RECOGNITION TIMING DIAGRAM Figure 6b G o od E ven ts tE VE NT /IN T t G L IT C H T ra nsitio n P oin t E ven t 1 E ven t 2 B a d E ven t 1 /IN T t G L IT C H T ra nsitio n P oin t B a d E ven t 2 tE VE NT /IN T T
DS1678 START MISSION FLOW CHART Figure 7 Start via External Event Start via Computer Mem Clr =1 no Clear Memory Mem Clr =1 yes no Clear Memory yes Write a 1 to the MIP bit Write a 1 to the ME bit. MIP = 0 The ME bit is Automatically Written to a 1 INT Input Activated Time/Date Stamp is Written no Continue to Monitor Input yes ETC Starts Incrementing MIP Automatically Written to a 1 EC is Incremented Time/Date Stamp is Written INT Input Activated no ETC Starts Incrementing.
DS1678 ROLL OVER FLOW CHART Figure 8 EC is Incremented no INT Input Activated Continue to Monitor Input yes Memory Full no Record Event in Event Memory yes Rollover Enable = 1 no yes ETC Written to Event 0 and Time/Date Stamp is Written ETC is Cleared 25 of 26
DS1678 NOTES: 1. After this period, the first clock pulse is generated. 2. A device must initially provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. The maximum thd:dat has only to be met if the device does not stretch the LOW period (tlow) of the SCL signal. 3. A fast mode device can be used in a standard mode system, but the requirement tsu:dat > 250ns must then be met.
