Instruction Manual

ManualsBrandsRainbow Electronics ManualsComputer HardwareDS1846

1 of 16 090800

FEATURES

 Three linear taper potentiometers

− Two 10 kΩ, 100 position

− One 100 kΩ, 256 position

 256 bytes of EEPROM memory

 Monitors microprocessor power supply,

voltage sense, and external override

 Access to data and potentiometer control via

a 2-wire interface

 External Write Protect pin to protect data and

potentiometer settings

 Nonvolatile wiper storage

 Operates from 3V or 5V supplies

 Packaging: 20-pin TSSOP

 Industrial operating temperature:

-40ºC to +85ºC

 Programming temperature: 0ºC to +70ºC

PIN ASSIGNMENT

PIN DESCRIPTION

- 3V or 5V Power Supply Input

GND - Ground

SDA - 2-wire Serial Data

Input/Output

SCL - 2-wire Serial Clock Input

WP - Write Protect Input

A0 - Address Input

H0, H1, H2 - High-End of Potentiometer

L 0, L1, L2 - Low-End of Potentiometer

W0, W1, W2 - Wiper Terminal of

Potentiometer

PBRST - Push Button Reset Button

NMI - Non-maskable Interrupt

IN - Voltage Input

RST - Active Low Reset Output

RST - Active High Reset Output

OVERVIEW

The DS1846 NV Tri-Potentiometer, Memory and MicroMonitor consists of two 10 kΩ,=100-position

linear taper potentiometer, one 100 kΩ,=256-position linear taper potentiometer, 256 bytes of EEPROM

memory, and a MicroMonitor. The device provides an ideal method for setting bias voltages and currents

in control applications using a minimum of circuitry.

DS1846

NV Tri-Potentiometer,

Memory and MicroMonito

www.dalsemi.com

SDA

SCL

NMI

GND

PBRST

RST

20-

in TSSOP

Summary of content (16 pages)

PAGE 1
DS1846 NV Tri-Potentiometer, Memory and MicroMonitor www.dalsemi.
PAGE 2
DS1846 The EEPROM memory allows a user to store configuration or calibration data for a specific system or device as well as provide control of the potentiometer wiper settings. Any type of user information may reside in the first 248 bytes of this memory. The next three bytes of memory are for potentiometer settings and the top five addresses of EEPROM memory are reserved. These reserved and potentiometer registers should not be used for data storage.
PAGE 3
DS1846 PIN DESCRIPTIONS VCC - Power Supply Terminal. +5.5 volts. The DS1846 will support supply voltages ranging from +2.7 to GND - Ground Terminal. SDA - 2-wire serial data interface. The serial data pin is for serial data transfer to and from the DS1846. The pin is open drain and may be wire-ORed with other open drain or open collector interfaces. SCL - 2-wire serial clock interface. The serial clock input is used to clock data into the DS1846 on rising edges and clock data out on falling edges.
PAGE 4
DS1846 MEMORY ORGANIZATION The DS1846’s serial EEPROM is internally organized with 32 pages. Each page contains 8 bytes. Each byte requires an 8-bit address for random byte addressing. The address bytes, starting at F8h, contain the wiper setting for the three potentiometers. The byte at address F8h determines the wiper setting for potentiometer 1, which contains 256 positions. The byte at address F9h determines the wiper setting for potentiometer 0, which contains 100 positions (00h to 63h).
PAGE 5
DS1846 Write Operations: After receiving a matching device address byte with the R/W bit set low, the device goes into the write mode of operation. The master must transmit an 8-bit EEPROM memory address to the device to define the address where the data is to be written. After the reception of this byte, the DS1846 will transmit a zero for one clock cycle to acknowledge the receipt of the memory address. The master must then transmit an 8-bit data word to be written into this memory address.
PAGE 6
DS1846 The sequential read operation is terminated when the master initiates a stop condition. The master does not respond with a zero. For a more detailed description of 2-wire theory of operation, refer to the following section. 2-WIRE SERIAL PORT OPERATION The 2-wire serial port interface supports a bi-directional data transmission protocol with device addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver.
PAGE 7
DS1846 Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account.
PAGE 8
DS1846 WRITE PROTECT An external pin WP (write protect) protects EEPROM data and potentiometer position from alteration in an application. This pin must be open or tied high to protect data from alteration. READING AND WRITING THE POTENTIOMETER VALUES Reading from and writing to the potentiometers consists of a standard read or write to EEPROM memory at the addresses F8h, F9h and FAh. The 8-bit value at address F8h controls the wiper setting for potentiometer 1, which has 256 positions.
PAGE 9
DS1846 When the supply being monitored decays to the voltage sense point, the DS1846 pulses the NMI output to the active state for a minimum 200 s. The NMI power-fail detection circuitry also has built-in hysteresis of 100 V. The supply must be below the voltage sense point for approximately 5 s before a low NMI will be generated. In this way, power supply noise is removed from the monitoring function, preventing false interrupts.
PAGE 10
DS1846 PUSHBUTTON RESET Figure 4 SDA SCL A0 WP NMI L0 W1 L1 L2 GND VCC IN PBRST RST RST H0 W0 H1 W2 H2 DS1846 8051 µp INTO 5V UPSTREAM SUPPLY VOLTAGE RST PUSHBUTTON RESET CONTROLLED BY NMI Figure 5 UPSTREAM SUPPLY VOLTAGE SDA SCL A0 WP NMI L0 W1 L1 L2 GND VCC IN 5V PBRST DS1846 RST RST RST H0 W0 H1 W2 H2 8051 µp 10 of 16 o
PAGE 11
DS1846 NON-MASKABLE INTERRUPT EXAMPLE Figure 6 SDA SCL A0 WP NMI VCC IN PBRST DS1846 L0 W1 L1 L2 GND VSENSE = RST RST H0 W0 H1 W2 H2 R1+ R2 X 1.25 R2 Example: Therefore: RST INTO 8051 µp VMAX = VSENSE X VCC VTP VSENSE = 4.70V at the trip point VCC = 3.3V 10 kΩ = R2 4.70 X 3.3 = 12.4V maximum 1.25 4.70 = R1 + 10k X 1.25 10k 11 of 16 o VSENSE 5V R1 = 27.
PAGE 12
DS1846 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Programming Temperature Storage Temperature Soldering Temperature -1.0V to +6.0V -40°C to +85°C; Industrial 0°C to +70°C -55°C to +125°C See J-STD-020A specification * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied.
PAGE 13
DS1846 DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Supply Current Active ICC Input Leakage ILI Wiper Resistance RW Wiper Current IW Input Logic 1 VIH Input Logic 0 VIL Input Logic levels A0, A1, A2 Input Current each I/O pin Standby Current 3V 5V Low Level Output Voltage (SDA) (-40°C to +85°C; VCC =2.7V to 5.5V) CONDITION MIN TYP -1 MAX UNITS NOTES 2 mA 17,18 +1 µA Ω 5V 250 500 3V 500 1000 1 mA 0.7 VCC VCC+0.5 V 1,2 GND-0.5 0.3VCC V 1,2 Input Logic 1 0.
PAGE 14
DS1846 (-40ºC to 85ºC, Vcc=2.7V to 5.5V) AC ELECTRICAL CHARACTERISTICS PARAMETER SCL clock frequency SYMBOL fSCL Bus free time between STOP and START condition Hold time (repeated) START condition Low period of SCL clock High period of SCL clock Data hold time tBUF tHD:DAT Data set-up time tSU:DAT Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Capacitive load for each bus line EEPROM write time CONDITION tHD:STA MIN 0 0 1.3 4.
PAGE 15
DS1846 NOTES: 1. All voltages are referenced to ground. 2. ISTBY specified with for VCC equal 3.0V and 5.0V and control port logic pins are driven to the appropriate logic levels. Appropriate logic levels specify that logic inputs are within a 0.5V of ground or VCC for the corresponding inactive state. 3. I/O pins of fast mode devices must not obstruct the SDA and SCL lines if VCC is switched off. 4.
PAGE 16
DS1846 17. Icc specified with SDA pin open. 18. Maximum ICC is dependent on clock rates. During serial port activity maximum ICC is specified for a clock rate of 5 MHz and worst case input levels. 19. Valid for Vcc = 5V only. 20. Valid at 25°C only. 21. Noise immunity - pulses < 2 µs at VCCTP minimum will not cause a reset. 22. tR = 5 µs 23. VCC >= 2.4V 24. VCC < 2.