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SECURITY FEATURES

• Single-chip, physically secure coprocessor

for non-secure host

• Arithmetic accelerator executes 1024-bit

public key cryptography in less than

1 second

• Unresettable True Time Clock self-imposes

expiration dates and date/time stamping

• Durable stainless steel case clearly shows

visual evidence of physical tampering

• 134 kbytes NV SRAM zeroes itself in

response to tampering or cooling below

-50°C

• 64 kbytes of ROM stores unalterable

validated firmware as Software ICs

• Unique, factory-lasered 64-bit registration

number (8-bit family code + 48-bit serial

number + 8-bit CRC tester) assures absolute

traceability because no two parts are alike

• Multi-drop controller supports multiple

iButtons on the same signal line for n-factor

security

• Signal path to the chip is limited to the lid of

the iButton to enhance security

• Communication protocol includes 16-bit

CRCs to insure error free packet transfers to

the buffer memory even with intermittent

connection

• The iButton can be accessed while affixed to

a wearable accessory to lower the chance of

being lost or stolen

• Only an authorized service provider can

install a transaction file which programs the

iButton for a specific application

• The transaction file contains scripts that call

on tested pre-fabricated cryptographic

functions

• Each file can be locked after installation so

that additional transaction files for new

services may be installed without

interference

GENERAL FEATURES

• Overdrive mode boosts communication

speed from 16.3 kbits to 142 kbits per second

• Operating temperature range from -20°C to

+70°C

• Over 5 years of data retention

• Timing accuracy better than ± 4

minutes/month at 25°C

• Button shape is insensitive to angular

orientation and self-aligning with the Dot

receptor

• The iButton is easily affixed with self-stick

adhesive backing, latched by its flange, or

locked with a ring pressed onto its rim

• Mechanical specification and 1-Wire

communication follow the iButton Book Of

Standards

SUPPORT

• Script tool kit speeds the development of

applications such as micro cash meters or

stored value purses

• Adapters for LPT port (parallel), COM Port

(serial), ETHERNET (10-base-T), or USB

connectivity

F5 MICROCAN

All dimensions are shown in millimeters.

6.25

GROUND

DATA

0.51

16.25

17.27

DS1957

Cryptographic Java-Powered iButton

www.iButton.com

Summary of content (25 pages)

PAGE 1
DS1957 Cryptographic Java-Powered iButtonTM www.iButton.
PAGE 2
DS1957 ISSUING AND ACTIVATION INFORMATION See www.ibutton.com EXAMPLES OF ACCESSORIES DS1410E DS1402D-DB8 DS9093F DS9096P DS9093RA DS9101 Parallel Port Button Holder iButton Dot Receptor Snap-In Fob Self-Stick Adhesive Pad Mounting Lock Ring Multi-Purpose Clip CRYPTO iButton DESCRIPTION The DS1957 Crypto iButton is a secure coprocessor residing in a stainless steel MicroCan with 1-Wire interface. The device is addressed by matching its individual 64-bit factory-lasered registration number.
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DS1957 64-BIT LASERED ROM Each DS1957 contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. (See Figure 3). The 64-bit ROM and ROM Function Control section allow the DS1957 to operate as a 1-Wire device and follow the 1-Wire protocol detailed in the section “1-Wire Bus System”.
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DS1957 DS1957 FUNCTIONAL BLOCK DIAGRAM Figure 1 INT VDD DATA DATA 1-WIRE FUNCTION CONTROL LID CONTACT DATA TRANSFER AND CONTROL FUNCTION CONTROL 16-BIT CRC GENERATOR 64-BIT LASERED ROM 128-BYTE INTERMEDIATE PRODUCT REGISTER 2 X 8-BYTE I/O BUFFER STATUS REGISTER TRUE TIME CLOCK ARITHMETIC ACCELERATOR MICROCOMPUTER TEMP.
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DS1957 HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2 BUS MASTER 1-WIRE BUS OTHER DEVICES DS1957 COMMAND LEVEL: 1-WIRE ROM FUNCTION COMMANDS (SEE FIGURE 6) DS1957 SPECIFIC DATA TRANSFER AND CONTROL FUNCTION COMMANDS (SEE FIGURE 4) AVAILABLE COMMANDS: DATA FIELD AFFECTED: READ ROM MATCH ROM SEARCH ROM SKIP ROM OVERDRIVE SKIP ROM OVERDRIVE MATCH ROM 64-BIT ROM 64-BIT ROM 64-BIT ROM N/A N/A 64-BIT ROM WRITE IPR READ IPR WRITE I/O BUFFER READ I/O BUFFER START PROGRAM CONTINUE PROGRAM RESET MICRO
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DS1957 WRITE INTERMEDIATE PRODUCT REGISTER (IPR) [0FH] The intermediate product register is used to transfer firmware command codes and data to the microcomputer inside the DS1957 and to read back the results of computations. After the command byte, the bus master transmits the length byte indicating the number of data bytes to be written to the IPR. The length byte may be in the range of 01H to 80H (1 to 128 decimal). The length byte is followed by the data bytes to be written.
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DS1957 DATA TRANSFER AND CONTROL FUNCTION FLOW CHART Figure 4 1) MASTER TX DATA TRANSFER OR CONTROL FUNCTION COMMAND FROM ROM FUNCTION FLOW CHART AAH READ IPR ? N 0FH WRITE IPR ? Y FLOW CHART PART 2 Y 1) BUS MASTER TX LENGTH BYTE BUS MASTER TX DATA BYTE BUS MASTER TX LENGTH BYTE BUS MASTER RX DATA BYTE 1) DS1957 INCREMENTS IPR ADDRESS N TO DATA TRANSFER AND CONTROL FUNCTION N 1) 1) SEE COMMAND DESCRIPTION FOR DETAILS DS1957 INCREMENTS IPR ADDRESS N LAST BYTE ? LAST BYTE ? Y Y BUS M
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DS1957 DATA TRANSFER AND CONTROL FUNCTION FLOW CHART Figure 4 (cont’d) FROM DATA TRANSFER AND CONTROL FUNCTION 2DH WRITE I/O BUFFER ? FLOW CHART PART 1 22H READ I/O BUFFER ? N FLOW CHART PART 3 Y Y BUS MASTER TX LENGTH BYTE TO DATA TRANSFER AND CONTROL FUNCTION N 1) BUS MASTER TX DATA BYTE BUS MASTER TX 1) LENGTH BYTE 1) BUS MASTER RX DATA BYTE 1) DS1957 DECREMENTS BUFFER ADDRESS DS1957 INCREMENTS BUFFER ADDRESS N N LAST BYTE ? LAST BYTE ? Y Y 1) BUS MASTER RX CRC 16 OF COMMAND, LENGTH
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DS1957 DATA TRANSFER AND CONTROL FUNCTION FLOW CHART Figure 4 (cont’d) FROM DATA TRANSFER AND CONTROL FUNCTION FLOW CHART PART 2 77H START PROGRAM ? Y N Y 1) BUS MASTER TX 6D43H RELEASE SEQUENCE N N 87H CONTINUE PROG.
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DS1957 DATA TRANSFER AND CONTROL FUNCTION FLOW CHART Figure 4 (cont’d) FROM DATA TRANSFER AND CONTROL FUNCTION FLOW CHART PART 3 N E1H READ STATUS ? N D2H WRITE STATUS ? Y Y BUS MASTER RX NUMBER OF FREE BYTES IN INPUT BUFFER 1) BUS MASTER TX OWUS STATUS BYTE BUS MASTER RX NUMBER OF USED BYTES IN OUTPUT BUFFER 1) BUS MASTER RX CRC 16 OF COMMAND AND OWUS BYTE BUS MASTER RX OWMS REGISTER CONTENTS 1) 1) 1) N CRC CORRECT ? BUS MASTER RX CPST REGISTER CONTENTS 1) BUS MASTER RX CRC 16 OF COMMA
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DS1957 When reading data from the IPR that has not been processed by the microcomputer inside the DS1957, the bus master already knows the actual value of the length byte. To read back data for optional verification, the bus master transmits the Read IPR command byte followed by the length byte and reads as many data bytes as specified by the length byte. After this, the DS1957 responds with an inverted CRC16 of the command code, length byte and all data bytes.
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DS1957 START PROGRAM [77H] The DS1957 Crypto iButton includes a microcomputer that performs logical and mathematical functions on data it receives from the bus master. During 1-Wire communication, this microcomputer is in a stop mode where it consumes virtually no power (see DC Characteristics). After the IPR and I/O buffer have been loaded with command, data and data management information, the microcomputer is started and power is provided through the 1-Wire line.
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DS1957 READ STATUS [E1H] In addition to the Intermediate Product Register (IPR) and the I/O buffer for data exchange and exchange management respectively, the DS1957 provides several bytes of status information. These status bytes manage the use of the I/O buffer, signal the availability of resources and the progress of numerical calculations, pass bit-level information to control the program flow within the microcomputer and return bit-level responses.
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DS1957 WRITE STATUS [D2H] The 1-Wire UART Status (OWUS) is the only status byte that can be written by the bus master. It resembles the counterpart of the OWMS register. The upper four bits of the OWUS are not assigned to any function. The lower bits, STAT0 to STAT3, are used to pass bit-level information to control the program flow within the microcomputer. The details on the use of these bits are explained in the “Crypto iButton Firmware Reference Manual.
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DS1957 HARDWARE CONFIGURATION Figure 5 VDD VPUP BUS MASTER 1.
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DS1957 READ ROM [33H] This command allows the bus master to read the DS1957’s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can be used only if there is a single DS1957 on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result). The resultant family code and 48-bit serial number will usually result in a mismatch of the CRC.
PAGE 17
DS1957 OVERDRIVE MATCH ROM [69H] The Overdrive Match ROM command, followed by a 64-bit ROM sequence transmitted at Overdrive Speed, allows the bus master to address a specific DS1957 on a multidrop bus and to simultaneously set it in Overdrive Mode. Only the DS1957 that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command. Slaves already in Overdrive mode from a previous Overdrive Skip or Match command will remain in Overdrive mode.
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DS1957 ROM FUNCTIONS FLOW CHART Figure 6 MASTER RESET FROM FIGURE 6 SECOND PART FROM DATA TRANSFER CONTROL FUNCTION FLOW (FIGURE 4) SHORT RESET PULSE ? N OD=0 Y 2) DS1954 TX PRESENC PULSE MASTER TX FUNCTION 33H READ COMMAN ? 55H MATCH COMMAN ? N 1) F0H SEARCH COMMAN ? N Y Y Y Y 1) 1) MASTER TX BIT 0 BIT 0 MATCH N DS1954 TX BIT 0 1) MASTER TX BIT 0 1) N BIT 0 MATCH DS1954 TX BIT 1 1) 1) MASTER TX BIT 1 BIT 1 MATCH ? N N 1) 1) DS1954 TX BIT 1 1) MASTER TX BIT 1 1) BIT 1
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DS1957 ROM FUNCTIONS FLOW CHART Figure 6 (cont’d) TO FIGURE 6 FIRST PART 3CH OVERDRIVE SKIP ? FROM FIGURE 6 FIRST PART N 69H OVERDRIVE MATCH ? Y OD=1 N Y OD=1 3) MASTER TX BIT 0 N BIT 0 MATCH ? Y MASTER TX BIT 1 BIT 1 MATCH ? 3) N Y Y MASTER TX RESET PULSE ? MASTER TX BIT 63 3) N BIT 63 MATCH ? FROM FIGURE 6 FIRST PART TO FIGURE 6 FIRST PART N Y 3) ALWAYS TO BE TRANSMITTED AT OVERDRIVE SPEED The initialization sequence required to begin any communication with the DS1957 is shown in
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DS1957 READ/WRITE TIME SLOTS The definitions of write and read time slots are illustrated in Figure 8. All time slots are initiated by the master driving the data line low. The falling edge of the data line synchronizes the DS1957 to the master by triggering a delay circuit in the DS1957. During write time slots, the delay circuit determines when the DS1957 will sample the data line.
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DS1957 WRITE-ZERO TIME SLOT tREC tSLOT VPULLUP VPULLUP MIN VIH MIN DS1954 VIL MAX SAMPLING WINDOW 0V 15 µs (OD: 2 µs) (OD: 6 µs) 60 µs tLOW0 Regular Speed 60 µs < tLOW0 < tSLOT < 120 µs 1 µs < tREC < 1 Overdrive Speed 6 µs < tLOW0 < tSLOT < 16 µs 1 µs < tREC < 1 RESISTOR MASTER READ-DATA TIME SLOT tSLOT tREC VPULLUP VPULLUP MIN VIH MIN MASTER SAMPLING VIL MAX WINDOW 0V tSU tRELEASE tLOWR tRDV RESISTOR MASTER Regular Speed 60 µs < tSLOT < 120 µs 1 µs < tLOWR < 15 µs 0 < tRELEASE < 45 µs
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DS1957 which is sufficient to operate the 1-Wire interface and to maintain the STOP mode of the microcomputer and accelerator. Once the initial data is loaded through the 1-Wire interface, the bus master will send either a Start Program or Continue Program command to the DS1957.
PAGE 23
DS1957 CRC GENERATION With the DS1957 there are two different types of CRCs (Cyclic Redundancy Checks). One CRC is an 8-bit type and is stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS1957 to determine if the ROM data has been received error-free by the bus master. The equivalent polynomial function of this CRC is: X8 + X5 + X4 + 1.
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DS1957 PHYSICAL SPECIFICATIONS Size Weight Humidity Altitude Expected Service Life See mechanical drawing 3.3 grams 90% RH at 50°C 10,000 feet 5 years at 25°C ABSOLUTE MAXIMUM RATINGS* Voltage on DATA to Ground Operating Temperature Storage Temperature -0.5V to +6.0V -20°C to +70°C -20°C to +70°C * This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operation sections of this specification is not implied.
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DS1957 AC ELECTRICAL CHARACTERISTICS OVERDRIVE SPEED PARAMETER Time Slot Write 1 Low Time Write 0 Low Time Read Low Time Read Data Valid Release Time Read Data Setup Recovery Time Reset Time High Reset Time Low Presence Detect High Presence Detect Low SYMBOL tSLOT tLOW1 tLOW0 tLOWR tRDV tRELEASE tSU tREC tRSTH tRSTL tPDHIGH tPDLOW MIN 6 1 6 1 0 (VPUP=4.0V to 5.5V; -20°C to +70°C) TYP exactly 2 1.5 1 48 48 2 8 MAX 16 2 16 2 4 1 80 6 24 UNITS µs µs µs µs µs µs µs µs µs µs µs µs NOTES 5 4 NOTES: 1.