DS2151Q DS2151Q T1 Single–Chip Transceiver FEATURES PIN ASSIGNMENT • Complete DS1/ISDN–PRI transceiver functionality can handle both long and short haul • 32–bit or 128–bit jitter attenuator • Generates DSX–1 and CSU line build outs • Frames to D4, ESF, and SLC–96R formats • Dual onboard two–frame elastic store slip buffers that FRAMER LONG & SHORT HAUL LINE INTERFACE trunks ELASTIC STORES • Line interface Functional Blocks connect to backplanes up to 8.
DS2151Q or 128 bits) can be placed in either the transmit or receive data paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also used for extracting and inserting Robbed–Bit signaling data and FDL data. The device contains a set of 64 eight bit internal registers which the user can access and control the operation of the unit. Quick access via the parallel control port allows a single micro to handle many T1 lines.
DS2151Q FDL INSERT LOGIC TLCLK TLINK TSYNC TCHCLK TCHBLK MUX TIMING CONTROL ELASTIC STORE LOSS OF TCLK DETECT TCLK TSER RSYNC SYSCLK ELASTIC STORE TIMING CONTROL RSER RCHCLK RCHBLK SYNCHRONIZER INT1/INT2 F–BIT INSERTION CRC GEN. FDL INSERTION YELLOW ALARM GEN. BPV COUNTER B8ZS ENCODE B8ZS DECODER AIS GEN.
DS2151Q PIN DESCRIPTION Table 1–1 PIN SYMBOL TYPE 1 2 3 4 AD4 AD5 AD6 AD7 I/O 5 RD(DS) I Read Input (Data Strobe). 6 CS I Chip Select. Must be low to read or write the port. 7 ALE(AS) I Address Latch Enable (Address Strobe). A positive going edge serves to demultiplex the bus. 8 WR(R/W) I Write Input (Read/Write). 9 RLINK O Receive Link Data. Updated with either FDL data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one RCLK before the start of a frame. See Section 13 for timing details.
DS2151Q PIN SYMBOL TYPE DESCRIPTION 20 BTS I Bus Type Select. Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the function of the RD(DS), ALE(AS), and WR(R/W) pins. If BTS=1, then these pins assume the function listed in parenthesis (). 21 22 RTIP RRING – Receive Tip and Ring. Analog inputs for clock recovery circuitry; connects to a 1:1 transformer (see Section 12 for details). 23 RVDD – Receive Analog Positive Supply. 5.0 volts.
DS2151Q PIN SYMBOL TYPE DESCRIPTION 40 TCHCLK O Transmit Channel Clock. 192 KHz clock which pulses high during the LSB of each channel. Useful for parallel to serial conversion of channel data, locating Robbed–Bit signaling bits, and for blocking clocks in DDS applications. See Section 13 for timing details. 41 42 43 44 AD0 AD1 AD2 AD3 I/O Address/Data Bus. A 8–bit multiplexed address/data bus. DS2151Q REGISTER MAP ADDRESS R/W 20 R/W 21 ADDRESS R/W Status Register 1.
DS2151Q 63 R Receive Signaling Register 4. 73 R/W Transmit Signaling Register 4. 64 R Receive Signaling Register 5. 74 R/W Transmit Signaling Register 5. 65 R Receive Signaling Register 6. 75 R/W Transmit Signaling Register 6. 66 R Receive Signaling Register 7. 76 R/W Transmit Signaling Register 7. 67 R Receive Signaling Register 8. 77 R/W Transmit Signaling Register 8. 68 R Receive Signaling Register 9. 78 R/W Transmit Signaling Register 9.
DS2151Q RCR1: RECEIVE CONTROL REGISTER 1 (Address=2B Hex) (MSB) LCVCRF (LSB) ARC OOF1 OOF2 SYNCC SYNCT SYNCE RESYNC SYMBOL POSITION NAME AND DESCRIPTION LCVCRF RCR1.7 Line Code Violation Count Register Function Select. 0=do not count excessive zeros 1=count excessive zeros ARC RCR1.6 Auto Resync Criteria. 0=Resync on OOF or RCL event 1=Resync on OOF only OOF1 RCR1.5 Out Of Frame Select 1. 0=2/4 frame bits in error 1=2/5 frame bits in error OOF2 RCR1.4 Out Of Frame Select 2.
DS2151Q RSDW RCR2.5 RSYNC Double–Wide. 0=do not pulse double–wide in signaling frames 1=do pulse double–wide in signaling frames (note: this bit must be set to zero when RCR2.4=1 or when RCR2.3=1) RSM RCR2.4 RSYNC Mode Select. 0=frame mode (see the timing in Section 13) 1=multiframe mode (see the timing in Section 13) RSIO RCR2.3 RSYNC I/O Select. 0=RSYNC is an output 1=RSYNC is an input (only valid if elastic store enabled) (note: this bit must be set to zero when CCR1.2=0) RD4YM RCR2.
DS2151Q TLINK TCR1.2 TLINK Select. (see note below) 0=source FDL or Fs bits from TFDL register 1=source FDL or Fs bits from the TLINK pin TBL TCR1.1 Transmit Blue Alarm. (see note below) 0=transmit data normally 1=transmit an unframed all one’s code at TPOS and TNEG TYEL TCR1.0 Transmit Yellow Alarm.
DS2151Q CCR1: COMMON CONTROL REGISTER 1 (Address=37 Hex) (MSB) TESE (LSB) LLB RSAO RLB SCLKM RESE PLB SYMBOL POSITION TESE CCR1.7 Transmit Elastic Store Enable. 0=elastic store is bypassed 1=elastic store is enabled LLB CCR1.6 Local Loopback. 0=loopback disabled 1=loopback enabled RSAO CCR1.5 Receive Signaling All One’s. 0=allow robbed signaling bits to appear at RSER 1=force all robbed signaling bits at RSER to one RLB CCR1.4 Remote Loopback.
DS2151Q DS2151Q. When PLB is enabled, the following will occur: 1. data will be transmitted from the TTIP and TRING pins synchronous with RCLK instead of TCLK in testing and debugging applications. In FLB, the DS2151Q will loop data from the transmit side back to the receive side. When FLB is enabled, the following will occur: 2. all of the receive side signals will continue to operate normally 1. unless the RLB is active, an unframed all one’s code will be transmitted at TTIP and TRING 3.
DS2151Q CCR3: COMMON CONTROL REGISTER 3 (Address=30 Hex) (MSB) ESMDM (LSB) ESR P16F RSMS PDE TLD TLU LIRST SYMBOL POSITION NAME AND DESCRIPTION ESMDM CCR3.7 Elastic Store Minimum Delay Mode. See Section 10.3 for details. 0=elastic stores operate at full two frame depth 1=elastic stores operate at 32–bit depth ESR CCR3.6 Elastic Store Reset. Setting this bit from a zero to a one will force the elastic stores to a known depth. Should be toggled after SYSCLK has been applied and is stable.
DS2151Q When the CCR3.3 is set to one, the DS2151Q will force the transmitted stream to meet this requirement no matter the content of the transmitted stream. When running B8ZS, the CCR3.3 bit should be set to zero since B8ZS encoded data streams cannot violate the pulse density requirements.
DS2151Q RESE RIR1.3 Receive Elastic Store Empty. Set when the receive elastic store buffer empties and a frame is repeated. SEFE RIR1.2 Severely Errored Framing Event. Set when 2 out of 6 framing bits (Ft or FPS) are received in error. B8ZS RIR1.1 B8ZS Code Word Detect. Set when a B8ZS code word is detected at RPOS and RNEG independent of whether the B8ZS mode is selected or not via CCR2.6. FBE RIR1.0 Frame Bit Error. Set when a Ft (D4) or FPS (ESF) framing bit is received in error.
DS2151Q SR1: STATUS REGISTER 1 (Address=20 Hex) (MSB) (LSB) LUP LDN LOTC RSLIP RBL RYEL RCL RLOS SYMBOL POSITION NAME AND DESCRIPTION LUP SR1.7 Loop Up Code Detected. Set when the repeating ...00001... loop up code is being received. LDN SR1.6 Loop Down Code Detected. Set when the repeating ...001... loop down code is being received. LOTC SR1.5 Loss of Transmit Clock. Set when the TCLK pin has not transitioned for one channel time (or 5.2us). Will force pin 16 high if enabled via CCR1.
DS2151Q LOOP UP/DOWN CODE DETECTION Bits SR1.7 and SR1.6 will indicate when either the standard “loop up” or “loop down” codes are being received by the DS2151Q. When a loop up code has been received for 5 seconds, the CPE is expected to loop the recovered data (without correcting BPVs) back to the source. The loop down code indicates that the loopback should be discontinued. See the AT&T publication TR 62411 for more details.
DS2151Q SLIP IMR1.4 Elastic Store Slip Occurrence. 0=interrupt masked 1=interrupt enabled RBL IMR1.3 Receive Blue Alarm. 0=interrupt masked 1=interrupt enabled RYEL IMR1.2 Receive Yellow Alarm. 0=interrupt masked 1=interrupt enabled RCL IMR1.1 Receive Carrier Loss. 0=interrupt masked 1=interrupt enabled RLOS IMR1.0 Receive Loss of Sync.
DS2151Q 5.0 ERROR COUNT REGISTERS There are a set of three counters in the DS2151Q that record bipolar violations, excessive zeros, errors in the CRC6 code words, framing bit errors, and number of multiframes that the device is out of receive synchronization. Each of these three counters are automatically updated on one second boundaries as determined by the one second timer in Status Register 2 (SR2.5). Hence, these registers contain performance data from the previous second.
DS2151Q PCVCR1: PATH VIOLATION COUNT REGISTER 1 (Address=25 Hex) PCVCR2: PATH VIOLATION COUNT REGISTER 2 (Address=26 Hex) (MSB) (LSB) (note 1) (note 1) (note 1) (note 1) CRC/FB11 CRC/FB10 CRC/FB9 CRC/FB8 PCVCR1 CRC/FB7 CRC/FB6 CRC/FB5 CRC/FB4 CRC/FB3 CRC/FB2 CRC/FB1 CRC/FB0 PCVCR2 SYMBOL POSITION NAME AND DESCRIPTION CRC/FB11 PCVCR1.3 MSB of the 12–Bit CRC6 Error or Frame Bit Error Count (note 2) CRC/FB0 PCVCR2.
DS2151Q NOTES: 1. The lower nibble of the counter at address 25 is used by the Path Code Violation Count Register. 2. MOSCR counts either errors in framing bit position (RCR2.0=0) or the number of multiframes out of sync (RCR2.0=1). MULTIFRAMES OUT OF SYNC COUNTING ARRANGEMENTS Table 5–3 FRAMING MODE (CCR2.3) COUNT MOS OR F–BIT ERRORS? (RCR2.
DS2151Q RFDLM1: RECEIVE FDL MATCH REGISTER 1 (Address=29 Hex) RFDLM2: RECEIVE FDL MATCH REGISTER 2 (Address=2A Hex) (MSB) RFDL7 (LSB) RFDL6 RFDL5 RFDL4 RFDL3 SYMBOL POSITION NAME AND DESCRIPTION RFDL7 RFDL.7 MSB of the FDL Match Code RFDL0 RFDL.0 LSB of the FDL Match Code When the byte in the Receive FDL Register matches either of the two Receive FDL Match Registers (RFDLM1/RFDLM2), SR2.2 will be set to a one and the INT2 will go active if enabled via IMR2.2. 6.
DS2151Q 7.0 SIGNALING OPERATION The Robbed–Bit signaling bits embedded in the T1 stream can be extracted from the receive stream and inserted into the transmit stream by the DS2151Q. There is a set of 12 registers for the receive side (RS1 to RS12) and 12 registers on the transmit side (TS1 to TS12). The signaling registers are detailed below. The CCR1.5 bit is used to control the robbed signaling bits as they appear at RSER. If CCR1.
DS2151Q TS1 TO TS12: TRANSMIT SIGNALING REGISTERS (Address=70 to 7B Hex) (MSB) (LSB) A(8) A(7) A(6) A(5) A(4) A(3) A(2) A(1) TS1 (70) A(16) A(15) A(14) A(13) A(12) A(11) A(10) A(9) TS2 (71) A(24) A(23) A(22) A(21) A(20) A(19) A(18) A(17) TS3 (72) B(8) B(7) B(6) B(5) B(4) B(3) B(2) B(1) TS4 (73) B(16) B(15) B(14) B(13) B(12) B(11) B(10) B(9) TS5 (74) B(24) B(23) B(22) B(21) B(20) B(19) B(18) B(17) TS6 (75) A/C(8) A/C(7) A/C(6) A/C(5) A/C(4) A/C(3)
DS2151Q TTR1/TTR2/TTR3: TRANSMIT TRANSPARENCY REGISTERS (Address=39 to 3B Hex) (MSB) (LSB) CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 TTR1 (39) CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 TTR2 (3A) CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 TTR3 (3B) SYMBOL POSITION CH24 TTR3.7 CH1 TTR1.0 NAME AND DESCRIPTION Transmit Transparency Registers.
DS2151Q made transparent by the Transmit Transparency Registers. 9.0 CLOCK BLOCKING REGISTERS The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking Registers (TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins respectively. The RCHBLK and TCHCLK pins are user programmable outputs that can be forced either high or low during individual channels. These outputs can be used to block clocks to a UART or LAPD controller in Fractional T1 or ISDN–PRI applications.
DS2151Q boundary, then RCR2.4 must be set to one. If the user selects to apply a 2.048 MHz clock to the SYSCLK pin, then the data output at RSER will be forced to all ones every fourth channel and the F–bit will be deleted. Hence channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be forced to a one. Also, in 2.048 MHz applications, the RCHBLK output will be forced high during the same channels as the RSER pin. See Section 13 for more details.
DS2151Q 12.0 LINE INTERFACE FUNCTIONS The line interface function in the DS2151Q contains three sections; (1) the receiver which handles clock and data recovery, (2) the transmitter which waveshapes and drives the T1 line, and (3) the jitter attenuator. Each of the these three sections is controlled by the Line Interface Control Register (LICR) which is described below.
DS2151Q clock is applied to the ACLKI pin, then it should be tied to RVSS to prevent the device from falsely sensing a clock. See Table 12–1. If the jitter attenuator is either placed in the transmit path or is disabled, the RCLK output can exhibit short high cycles of the clock. This is due to the highly oversampled digital clock recovery cir- cuitry.
DS2151Q TRANSFORMER SPECIFICATIONS Table 12–3 SPECIFICATION RECOMMENDED VALUE Turns Ratio 1:1 (receive) and 1:1.15 or 1:1.36 (transmit) ±5% Primary Inductance 600 µH minimum Leakage Inductance 1.0 µH maximum Interwinding Capacitance 40 pF maximum DC Resistance 1.2 ohms maximum 12.3 JITTER ATTENUATOR The jitter attenuator divides the clock provided by the 6.176 MHz crystal at the XTAL1 and XTAL2 pins to create an output clock that contains very little jitter.
DS2151Q DS2151Q EXTERNAL ANALOG CONNECTIONS Figure 12–1 +5V 0.47 µF (NON–POLARIZED) DS2151Q TTIP DVDD Rt T1 TRANSMIT PAIR 0.01 µF + 0.1 µF 68 µF DVSS TRING Rt 1.15:1 (Rt=0 ohms) or 1.36:1 (Rt=4.7 ohms) RVDD 0.1 µF RVSS NOTE: KEEP THE LINES TO RTIP AND RRING AS SHORT AS POSSIBLE AND ROUTE THEM VIA THE EXACT SAME PATH. TVDD 0.1 µF TVSS RTIP XTAL1 6.176 MHz T1 RECEIVE PAIR RRING XTAL2 1:1 R1 0.
DS2151Q DS2151Q TRANSMIT WAVEFORM TEMPLATE Figure 12–3 1.2 MAXIMUM CURVE UI Time Amp. 1.1 1.0 –0.77 –0.39 –0.27 –0.27 –0.12 0.00 0.27 0.35 0.93 1.16 0.9 0.8 0.7 –500 0.05 –255 0.05 –175 0.80 –175 1.15 –75 1.15 0 1.05 175 1.05 225 –0.07 600 0.05 750 0.05 NORMALIZED AMPLITUDE 0.6 MINIMUM CURVE UI Time Amp. –0.77 –0.23 –0.23 –0.15 0.00 0.15 0.23 0.23 0.46 0.66 0.93 1.16 –500 –150 –150 –100 0 100 150 150 300 430 600 750 –0.05 –0.05 0.50 0.95 0.95 0.90 0.50 –0.45 –0.45 –0.20 –0.05 –0.05 0.5 0.4 0.3 0.
DS2151Q 13.0 TIMING DIAGRAMS RECEIVE SIDE D4 TIMING Figure 13–1 1 FRAME# 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 RSYNC1 RSYNC2 RSYNC3 RLCLK RLINK4 NOTES: 1. RSYNC in the frame mode (RCR2.4=0) and double-wide frame sync is not enabled (RCR2.5=0). 2. RSYNC in the frame mode (RCR2.4=0) and double-wide frame sync is enabled (RCR2.5=1). 3. RSYNC in the multiframe mode (RCR2.4=1). 4. RLINK data (S–bit) is updated one bit prior to even frames and held for two frames.
DS2151Q RECEIVE SIDE BOUNDARY TIMING WITH ELASTIC STORE(S) DISABLED Figure 13–3 RCLK CHANNEL 23 RSER CHANNEL 24 LSB MSB RSYNC RCHCLK RCHBLK1 RLCLK RLINK NOTES: 1. RCHBLK is programmed to block channel 24. 2. An ESF boundary is shown.
DS2151Q 1.544 MHz BOUNDARY TIMING WITH ELASTIC STORE(S) ENABLED Figure 13–4 SYSCLK CHANNEL 23 TSER/ RSER CHANNEL 24 LSB MSB CHANNEL 1 LSB F MSB RSYNC1 RSYNC2 RCHCLK RCHBLK3 NOTES: 1. RSYNC is in the output mode (RCR2.3=0). 2. RSYNC is in the input mode (RCR2.3=1). 3. RCHBLK is programmed to block channel 24. 2.048 MHz BOUNDARY TIMING WITH ELASTIC STORE(S) ENABLED Figure 13–5 SYSCLK CHANNEL 31 TSER/ RSER1 CHANNEL 32 LSB MSB CHANNEL 1 LSB RSYNC2 RSYNC3 RCHCLK RCHBLK4 NOTES: 1.
DS2151Q TRANSMIT SIDE D4 TIMING Figure 13–6 FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 TSYNC1 TSYNC2 TSYNC3 TLCLK TLINK4 NOTES: 1. TSYNC in the frame mode (TCR2.3=0) and double-wide frame sync is not enabled (TCR2.4=0). 2. TSYNC in the frame mode (TCR2.3=0) and double-wide frame sync is enabled (TCR2.4=1). 3. TSYNC in the multiframe mode (TCR2.3=1). 4. TLINK data (S–bit) is sampled during the F–bit position of even frames for insertion into the outgoing T1 stream when enabled via TCR1.
DS2151Q 5. TLINK data (FDL bits) is sampled during the F-bit time of odd frame and inserted into the outgoing T1 stream if enabled via TCR1.2. 6. ZBTSI mode is enabled (TCR2.5=1). 7. TLINK data (Z bits) is sampled during the F-bit time of frame 1, 5, 9, 13, 17, and 21 and inserted into the outgoing stream if enabled via TCR1.2.
DS2151Q DS2151Q TRANSMIT DATA FLOW Figure 13–9 TSER TIDR 1 TIR1 TO TIR3 0 IDLE CODE MUX ROBBED BIT SIGNALING ENABLE (TCR1.4) TS1 TO TS12 0 1 SIGNALING MUX TTR1 TO TTR3 TTR1 TO TTR3 GLOBAL BIT 7 STUFFING (TCR1.3) BIT 7 STUFFING BIT 7 ZERO SUPPRESSION ENABLE (TCR2.0) TRANSMIT LOOP UP CODE (CCR3.1) TRANSMIT LOOP DOWN CODE (CCR3.2) LOOP CODE GENERATION FRAME MODE SELECT (CCR2.7) D4 YELLOW ALARM SELECT (TCR2.1) TRANSMIT YELLOW (TCR1.
DS2151Q ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature –1.0V to +7.0V 0°C to +70°C (–40°C to +85°C for DS2151QN) –55°C to +125°C 260°C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied.
DS2151Q AC CHARACTERISTICS - PARALLEL PORT PARAMETER (0°C to 70°C; VDD=5V + 5%) (–40°C to +85°C for DS2151QN) SYMBOL MIN tCYC 250 ns Pulse Width, DS Low or RD High PWEL 150 ns Pulse Width, DS High or RD Low PWEH 100 ns Cycle Time TYP MAX Input Rise/Fall Times tR, tF R/W Hold Time tRWH 10 ns R/W Setup Time Before DS High tRWS 50 ns CS Setup Time Before DS, WR or RD active tCS 20 ns CS Hold Time tCH 0 ns Read Data Hold Time tDHR 10 Write Data Hold Time tDHW 0 ns Mux
DS2151Q INTEL BUS WRITE AC TIMING tCYC PWASH ALE tASD RD tASED tASD PWEH PWEL WR tCH tCS CS tASL tDHW AD0-AD7 tAHL tDSW MOTOROLA BUS AC TIMING PWASH AS PWEH DS tASD tASED PWEL tCYC tRWS tRWH R/W tASL tDDR tDHR AD0-AD7 (READ) tAHL AD0-AD7 (WRITE) tCH tCS CS tASL tDSW tAHL tDHW 022697 41/46
DS2151Q (0°C to 70°C; VDD=5V ± 5%) (–40°C to +85°C for DS2151QN) AC CHARACTERISTICS – RECEIVE SIDE PARAMETER SYMBOL MIN ACLKI/RCLK Period tCP RCLK Pulse Width tCH tCL 230 230 RCLK Pulse Width tCH tCL 115 115 SYSCLK Period tSP tSP SYSCLK Pulse Width tSH tSL 75 75 RSYNC Set Up to SYSCLK Falling tSU 25 RSYNC Pulse Width tPW 50 SYSCLK Rise/Fall Times tR, tF TYP MAX UNITS 648 ns 324 324 ns ns 1 ns ns 2 ns ns 3 4 648 488 ns tSH–5 ns ns 25 ns Delay RCLK or SYSCLK to RSER
DS2151Q RECEIVE SIDE AC TIMING tCP tCL tCH tSL tSH RCLK tR tF SYSCLK tSP tDD F–BIT OR MSB OF CHANNEL 1 RSER tD1 RCHCLK tD2 RCHBLK tD3 RSYNC1 tPW tSU RSYNC2 tD4 RLCLK tD5 RLINK NOTES: 1. RSYNC is in the output mode (RCR2.3=0). 2. RSYNC is in the input mode (RCR2.3=1). 3. RLCLK and RLINK only have a timing relationship to RCLK. 4. RCLK can exhibit a short high time if the jitter attenuator is either disabled or in the transmit path.
DS2151Q AC CHARACTERISTICS – TRANSMIT SIDE PARAMETER SYMBOL TCLK Period tP (0°C to 70°C; VDD=5V + 5%) (–40°C to +85°C for DS2151QN) MIN TYP MAX 648 UNITS NOTES ns TCLK Pulse Width tCH tCL 75 75 ns ns TSER and TLINK Set Up to TCLK Falling tSU 25 ns 1 TSER and TLINK Hold from TCLK Falling tHD 25 ns 1 TSYNC Setup to TCLK Falling tSU 25 TSYNC Pulse Width tPW 50 TCLK Rise/Fall Times tR, tF tCH–5 25 ns Delay TCLK to TCHCLK tD1 10 60 ns Delay TCLK to TCHBLK tD2 10 70 n
DS2151Q TRANSMIT SIDE AC TIMING tP tCL tF tR tCH TCLK TSER3 F–BIT tHD tD1 tSU TCHCLK tD2 TCHBLK tD3 TSYNC1 tPW tSU TSYNC2 tD4 TLCLK tHD tSU TLINK NOTES: 1. TSYNC is in the output mode (TCR2.2=1). 2. TSYNC is in the input mode (TCR2.2=0). 3. TSER is sampled on the falling edge of SYSCLK if the transmit side elastic store is enabled.
DS2151Q DS2151Q T1 CONTROLLER 44–PIN PLCC E E1 B N 1 .075 MAX D1 D D2 NOTE 1 B1 CH1 .150 MAX e1 C E2 A2 NOTE1: PIN 1 IDENTIFIER TO BE LOCATED IN ZONE INDICATED. INCHES DIM MIN MAX A 0.165 0.180 A1 0.090 0.120 A2 0.020 – B 0.026 0.033 B1 0.013 0.021 C 0.009 0.012 CH1 0.042 0.048 D 0.685 0.695 D1 0.650 0.656 D2 0.590 0.630 E 0.685 0.695 E1 0.650 0.656 E2 0.590 0.630 e1 N 022697 46/46 0.
