DS2152 PRELIMINARY DS2152 Enhanced T1 Single Chip Transceiver FEATURES PIN ASSIGNMENT • Complete DS1/ISDN–PRI transceiver functionality • Line interface can handle both long and short haul trunks • 32–bit or 128–bit crystal–less jitter attenuator • Generates DSX–1 and CSU line build outs • Frames to D4, ESF, and SLC–96R formats • Dual onboard two–frame elastic store slip buffers that can connect to asynchronous backplanes up to 8.
DS2152 access and control the operation of the unit. Quick access via the parallel control port allows a single controller to handle many T1 lines. The device fully meets all of the latest T1 specifications including ANSI T1.403–1995, ANSI T1.231–1993, AT&T TR 62411 (12–90), AT&T TR54016, and ITU G.703, G.704, G.706, G.823, and I.431. 1.0 INTRODUCTION The DS2152 is a superset version of the popular DS2151 T1 Single–Chip Transceiver offering the new features listed below.
DS2152 Reader’s Note This data sheet assumes a particular nomenclature of the T1 operating environment. In each 125 us frame, there are 24 eight–bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by D4 SLC–96 ESF B8ZS CRC Ft Fs FPS MF BOC HDLC FDL channel 1. Each channel is made up of eight bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is the LSB and is transmitted last.
DS2152 TLCLK TLINK LIUC TPOSO TCLKO TNEGO Remote Loopback Filter LIU AIS Generation Wave Shaping CSU Filters TTIP TRING RTIP RRING RVSS DVSS TVSS 8 A0 to A6 ALE(AS)/A7 RD(DS) WR(R/W) BTS CS Line Drivers 3 4 4 Power Connections MUX 7 Local Loopback Clock/Data Recovery RVDD DVDD TVDD INT D0 to D7/AD0 to AD7 24.7MHz 1.
DS2152 PIN LIST Table 1–1 PIN SYMBOL TYPE DESCRIPTION 1 RCHBLK O Receive Channel Block 2 NC – No Connect 3 8MCLK O 8.
DS2152 PIN SYMBOL 35 TLINK I Transmit Link Data 36 NC – No Connect 37 TSYNC I/O 38 TPOSI I Transmit Positive Data Input 39 TNEGI I Transmit Negative Data Input 40 TCLKI I Transmit Clock Input 41 TCLKO O Transmit Clock Output 42 TNEGO O Transmit Negative Data Output 43 TPOSO O Transmit Positive Data Output 44 DVDD – Digital Positive Supply 45 DVSS – Digital Signal Ground 46 TCLK I Transmit Clock 47 TSER I Transmit Serial Data 48 TSIG I Transmit Signali
DS2152 PIN SYMBOL TYPE DESCRIPTION 70 A4 I Address Bus Bit 4 71 A5 I Address Bus Bit 5 72 A6 I Address Bus Bit 6 73 A7/ALE I Address Bus Bit 7 / Address Latch Enable 74 RD (DS) I Read Input (Data Strobe) 75 CS I Chip Select 76 NC – No Connect 77 WR (R/W) I Write Input (Read/Write) 78 RLINK O Receive Link Data 79 RLCLK O Receive Link Clock 80 DVSS – Digital SIgnal Ground 81 DVDD – Digital Positive Supply 82 RCLK O Receive Clock 83 DVDD – Digital Pos
DS2152 DS2152 PIN DESCRIPTION Table 1–2 TRANSMIT SIDE DIGITAL PINS Transmit Clock [TCLK]. A 1.544 MHz primary clock. Used to clock data through the transmit side formatter. this pin is set to output pulses at frame boundaries, it can also be set via TCR2.4 to output double–wide pulses at signaling frames. See Section 15 for details. Transmit Serial Data [TSER]. Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit side elastic store is disabled.
DS2152 onto the T1 line. Can be internally connected to TNEGO by tying the LIUC pin high. TPOSI and TNEGI can be tied together in NRZ applications. Transmit Clock Input [TCLKI]. Line interface transmit clock. Can be internally connected to TCLKO by tying the LIUC pin high. RECEIVE SIDE DIGITAL PINS Receive Link Data [RLINK]. Updated with either FDL data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one RCLK before the start of a frame. See Section 15 for details. pulses on signaling frames.
DS2152 and is used to clock data through the receive side framer. Receive Positive Data Output [RPOSO]. Updated on the rising edge of RCLKO with the bipolar data out of the line interface. This pin is normally tied to RPOSI. Address Bus [A0 to A6]. In non–multiplexed bus operation (MUX = 0), serves as the address bus. In multiplexed bus operation (MUX = 1), these pins are not used and should be tied low. Receive Negative Data Output [RNEGO].
DS2152 RCLKI pins. Tie high to connect the the line interface circuitry to the framer/formatter circuitry and deactivate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. When LIUC is tied high, the TPOSI/TNEGI/TCLKI/ RPOSI/RNEGI/RCLKI pins should be tied low. Receive Tip and Ring [RTIP & RRING]. Analog inputs for clock recovery circuitry. These pins connect via a 1:1 transformer to the T1 line. See Section 14 for details. Transmit Tip and Ring [TTIP & TRING]. Analog line driver outputs.
DS2152 ADDRESS R/W 13 R/W Transmit Code Definition 14 R/W Receive Up Code Definition RUPCD 15 R/W Receive Down Code Definition RDNCD 16 R/W Transmit Channel Control 1 TCC1 17 R/W Transmit Channel Control 2 TCC2 18 R/W Transmit Channel Control 3 TCC3 19 R/W Common Control 5 CCR5 1A R 1B R/W Receive Channel Control 1 RCC1 1C R/W Receive Channel Control 2 RCC2 1D R/W Receive Channel Control 3 RCC3 1E R/W Common Control 6 1F R 20 R/W Status 1 SR1 21 R/W Sta
DS2152 ADDRESS R/W REGISTER NAME REGISTER ABBREVIATION 34 R/W Transmit Channel Blocking 3 35 R/W Transmit Control 1 TCR1 36 R/W Transmit Control 2 TCR2 37 R/W Common Control 1 CCR1 38 R/W Common Control 2 CCR2 39 R/W Transmit Transparency 1 TTR1 3A R/W Transmit Transparency 2 TTR2 3B R/W Transmit Transparency 3 TTR3 3C R/W Transmit Idle 1 TIR1 3D R/W Transmit Idle 2 TIR2 3E R/W Transmit Idle 3 TIR3 3F R/W Transmit Idle Definition TIDR 40 R/W Transmit Cha
DS2152 ADDRESS R/W 55 R/W Transmit Channel 6 TC6 56 R/W Transmit Channel 7 TC7 57 R/W Transmit Channel 8 TC8 58 R/W Receive Channel 1 RC17 59 R/W Receive Channel 18 RC18 5A R/W Receive Channel 19 RC19 5B R/W Receive Channel 20 RC20 5C R/W Receive Channel 21 RC21 5D R/W Receive Channel 22 RC22 5E R/W Receive Channel 23 RC23 5F R/W Receive Channel 24 RC24 60 R Receive Signaling 1 RS1 61 R Receive Signaling 2 RS2 62 R Receive Signaling 3 RS3 63 R Rec
DS2152 ADDRESS R/W REGISTER NAME REGISTER ABBREVIATION 76 R/W Transmit Signaling 7 TS7 77 R/W Transmit Signaling 8 TS8 78 R/W Transmit Signaling 9 TS9 79 R/W Transmit Signaling 10 TS10 7A R/W Transmit Signaling 11 TS11 7B R/W Transmit Signaling 12 TS12 7C R/W Line Interface Control LICR 7D R/W Test 1 7E R/W Transmit FDL Register TFDL 7F R/W Interrupt Mask Register 1 IMR1 80 R/W Receive Channel 1 RC1 81 R/W Receive Channel 2 RC2 82 R/W Receive Channel 3
DS2152 3.0 CONTROL, ID AND TEST REGISTER The operation of the DS2152 is configured via a set of eleven control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS2152 has been initialized, the control registers will only need to be accessed when there is a change in the system configuration. There are two Receive Control Register (RCR1 and RCR2), two Transmit Control Registers (TCR1 and TCR2), and seven Common Control Registers (CCR1 to CCR7).
DS2152 OOF2 RCR1.4 Out Of Frame Select 2. 0 = follow RCR1.5 1 = 2/6 frame bits in error SYNCC RCR1.3 Sync Criteria. In D4 Framing Mode 0 = search for Ft pattern, then search for Fs pattern 1 = cross couple Ft and Fs pattern In ESF Framing Mode 0 = search for FPS pattern only 1 = search for FPS and verify with CRC6 SYNCT RCR1.2 Sync Time. 0 = qualify 10 bits 1 = qualify 24 bits SYNCE RCR1.1 Sync Enable. 0 = auto resync enabled 1 = auto resync disabled RESYNC RCR1.0 Resync.
DS2152 MOSCRF RCR2.0 Multiframe Out of Sync Count Register Function Select. 0 = count errors in the framing bit position 1 = count the number of multiframes out of sync TCR1: TRANSMIT CONTROL REGISTER 1 (Address=35 Hex) (MSB) LOTCMC (LSB) TFPT TCPT RBSE GB7S TFDLS TBL TYEL SYMBOL POSITION NAME AND DESCRIPTION LOTCMC TCR1.7 Loss Of Transmit Clock Mux Control.
DS2152 TCR2: TRANSMIT CONTROL REGISTER 2 (Address=36 Hex) (MSB) (LSB) TEST1 TEST0 TZBTSI TSDW TSM TSIO TD4YM TB7ZS SYMBOL POSITION NAME AND DESCRIPTION TEST1 TCR2.7 Test Mode Bit 1 for Output Pins. See Table 3–1. TEST0 TCR2.6 Test Mode Bit 0 for Output Pins. See Table 3–1. TZBTSI TCR2.5 Transmit Side ZBTSI Enable. 0 = ZBTSI disabled 1 = ZBTSI enabled TSDW TCR2.4 TSYNC Double–Wide. (note: this bit must be set to zero when TCR2.3=1 or when TCR2.
DS2152 ODF CCR1.6 Output Data Format. 0 = bipolar data at TPOSO and TNEGO 1 = NRZ data at TPOSO; TNEGO = 0 RSAO CCR1.5 Receive Signaling All One’s. This bit should not be enabled if hardware signaling is being utilized. See Section 7 for more details. 0 = allow robbed signaling bits to appear at RSER 1 = force all robbed signaling bits at RSER to one TSCLKM CCR1.4 TSYSCLK Mode Select. 0 = if TSYSCLK is 1.544 MHz 1 = if TSYSCLK is 2.048 MHz RSCLKM CCR1.3 RSYSCLK Mode Select. 0 = if RSYSCLK is 1.
DS2152 CCR2: COMMON CONTROL REGISTER 2 (Address=38 Hex) (MSB) TFM (LSB) TB8ZS TSLC96 TFDL RFM RB8ZS RSLC96 RFDL SYMBOL POSITION NAME AND DESCRIPTION TFM CCR2.7 Transmit Frame Mode Select. 0 = D4 framing mode 1 = ESF framing mode TB8ZS CCR2.6 Transmit B8ZS Enable. 0 = B8ZS disabled 1 = B8ZS enabled TSLC96 CCR2.5 Transmit SLC–96 / Fs–Bit Insertion Enable. Only set this bit to a one in D4 framing applications. Must be set to one to source the Fs pattern. See Section 11 for details.
DS2152 ESR CCR3.6 Elastic Store Reset. Setting this bit from a zero to a one will force the elastic stores to a known depth. Should be toggled after RSYSCLK and TSYSCLK have been applied and are stable. Must be cleared and set again for a subsequent reset. RLOSF CCR3.5 Function of the RLOS/LOTC Output. 0 = Receive Loss of Sync (RLOS) 1 = Loss of Transmit Clock (LOTC) RSMS CCR3.4 RSYNC Multiframe Skip Control. Useful in framing format conversions from D4 to ESF.
DS2152 RPCSI CCR4.6 Receive Per–Channel Signaling Insert. See Section 7.2 for more details. 0 = do not use RCHBLK to determine which channels should have signaling re–inserted 1 = use RCHBLK to determine which channels should have signaling re–inserted RFSA1 CCR4.5 Receive Force Signaling All Ones. See Section 7.2 for more details. 0 = do not force extracted robbed–bit signaling bit positions to a one 1 = force extracted robbed–bit signaling bit positions to a one RFE CCR4.4 Receive Freeze Enable.
DS2152 TCM4 CCR5.4 Transmit Channel Monitor Bit 4. MSB of a channel decode that determines which transmit channel data will appear in the TDS0M register. See Section 6 for details. TCM3 CCR5.3 Transmit Channel Monitor Bit 3. TCM2 CCR5.2 Transmit Channel Monitor Bit 2. TCM1 CCR5.1 Transmit Channel Monitor Bit 1. TCM0 CCR5.0 Transmit Channel Monitor Bit 0. LSB of the channel decode. Local Loopback When CCR5.6 is set to a one, the DS2152 will be forced into Local LoopBack (LLB).
DS2152 – CCR7.6 Remote Loopback. 0 = loopback disabled 1 = loopback enabled – CCR7.5 Not Assigned. Should be set to zero when written to. – CCR7.4 Not Assigned. Should be set to zero when written to. – CCR7.3 Not Assigned. Should be set to zero when written to. – CCR7.2 Not Assigned. Should be set to zero when written to. – CCR7.1 Not Assigned. Should be set to zero when written to. – CCR7.0 Not Assigned. Should be set to zero when written to.
DS2152 4.0 STATUS AND INFORMATION REGISTERS There is a set of nine registers that contain information on the current real time status of the DS2152, Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Registers 1 to 3 (RIR1/RIR2/RIR3) and a set of four registers for the onboard HDLC and BOC controller for the FDL. The specific details on the four registers pertaining to the FDL are covered in Section 11.
DS2152 16ZD RIR1.5 Sixteen Zero Detect. Set when a string of at least sixteen consecutive zeros (regardless of the length of the string) have been received at RPOSI and RNEGI. RESF RIR1.4 Receive Elastic Store Full. Set when the receive elastic store buffer fills and a frame is deleted. RESE RIR1.3 Receive Elastic Store Empty. Set when the receive elastic store buffer empties and a frame is repeated. SEFE RIR1.2 Severely Errored Framing Event.
DS2152 RL0 RIR3.6 Receive Level BIt 0. See Table 4–1. JALT RIR3.5 Jitter Attenuator Limit Trip. Set when the jitter attenuator FIFO reaches to within 4 bits of it’s limit; useful for debugging jitter attenuation operation. LORC RIR3.4 Loss of Receive Clock. Set when the RCLKI pin has not transitioned for at least 2 us (3 us ± 1 us). FRCL RIR3.3 Framer Receive Carrier Loss.
DS2152 ALARM CRITERIA Table 4–2 ALARM SET CRITERIA CLEAR CRITERIA Blue Alarm (AIS) (see note 1 below) when over a 3 ms window, 5 or less zeros are received when over a 3 ms window, 6 or more zeros are received Yellow Alarm (RAI) 1. D4 bit 2 mode(RCR2.
DS2152 IMR1: INTERRUPT MASK REGISTER 1 (Address=7F Hex) (MSB) LUP (LSB) LDN LOTC SLIP RBL RYEL SYMBOL POSITION LUP IMR1.7 Loop Up Code Detected. 0 = interrupt masked 1 = interrupt enabled LDN IMR1.6 Loop Down Code Detected. 0 = interrupt masked 1 = interrupt enabled LOTC IMR1.5 Loss of Transmit Clock. 0 = interrupt masked 1 = interrupt enabled SLIP IMR1.4 Elastic Store Slip Occurrence. 0 = interrupt masked 1 = interrupt enabled RBL IMR1.3 Receive Blue Alarm.
DS2152 5.0 RFDL IMR2.4 Receive FDL Buffer Full. 0 = interrupt masked 1 = interrupt enabled TFDL IMR2.3 Transmit FDL Buffer Empty. 0 = interrupt masked 1 = interrupt enabled RMTCH IMR2.2 Receive FDL Match Occurrence. 0 = interrupt masked 1 = interrupt enabled RAF IMR2.1 Receive FDL Abort. 0 = interrupt masked 1 = interrupt enabled RSC IMR2.0 Receive Signaling Change.
DS2152 LINE CODE VIOLATION COUNTING ARRANGEMENTS Table 5–1 COUNT EXCESSIVE ZEROS? (RCR1.7) B8ZS ENABLED? (CCR2.2) no no BPVs yes no BPVs + 16 consecutive zeros no yes BPVs (B8ZS code words not counted) yes yes BPV’s + 8 consecutive zeros 5.2 Path Code Violation Count Register (PCVCR) WHAT IS COUNTED IN THE LCVCRs matically count errors in the Ft framing bit position. Via the RCR2.1 bit, the DS2152 can be programmed to also report errors in the Fs framing bit position.
DS2152 errors in the FPS framing pattern (in the ESF mode). When the MOSCR is operated in this mode, it is disabled during receive loss of synchronization (RLOS = 1) conditions. See Table 5–3 for a detailed description of what the MOSCR is capable of counting.
DS2152 CCR5: COMMON CONTROL REGISTER 5 (Address=19 Hex) [repeated here from section 3 for convenience] (MSB) TJC (LSB) LLB LIAIS TCM4 TCM3 TCM2 TCM1 SYMBOL POSITION TJC CCR5.7 Transmit Japanese CRC Enable. See Section 3 for details. TCM0 NAME AND DESCRIPTION LLB CCR5.6 Local Loopback. See Section 3 for details. LIAIS CCR5.5 Line Interface AIS Generation Enable. See Section 3 for details. TCM4 CCR5.4 Transmit Channel Monitor Bit 4.
DS2152 – CCR5.6 Not Assigned. Should be set to zero when written. – CCR5.5 Not Assigned. Should be set to zero when written . RCM4 CCR5.4 Receive Channel Monitor Bit 4. MSB of a channel decode that determines which receive DS0 channel data will appear in the RDS0M register. RCM3 CCR5.3 Receive Channel Monitor Bit 3. RCM2 CCR5.2 Receive Channel Monitor Bit 2. RCM1 CCR5.1 Receive Channel Monitor Bit 1. RCM0 CCR5.0 Receive Channel Monitor Bit 0.
DS2152 7.0 SIGNALING OPERATION The DS2152 contains provisions for both processor based (i.e., software based) signaling bit access and for hardware based access. Both the processor based access and the hardware based access can be used simultaneously if necessary. The processor based signaling is covered in Section 7.1 and the hardware based signaling is covered in Section 7.2. 7.
DS2152 of a change in signaling by setting the IMR2.0 bit. Once a signaling change has been detected, the user has at least 2.75 ms to read the data out of the RS1 to RS12 registers before the data will be lost.
DS2152 the lower nibble of each channel. Hence, bits 5 and 6 contain the same data as bits 7 and 8 respectively in each channel. The RSIG data is updated once a multiframe (1.5 ms) unless a freeze is in effect. See the timing diagrams in Section 15 for some examples. The other hardware based signaling operating mode called signaling re–insertion can be invoked by setting the RSRE control bit high (CCR4.7=1).
DS2152 Each of the bit position in the Transmit Idle Registers (TIR1/TIR2/TIR3) represent a DS0 channel in the outgoing frame. When these bits are set to a one, the corresponding channel will transmit the Idle Code contained in the Transmit Idle Definition Register (TIDR). Robbed bit signaling and Bit 7 stuffing will occur over the programmed Idle Code unless the DS0 channel is made transparent by the Transmit Transparency Registers. Back (PCLB). If the TIRFS control bit (CCR4.
DS2152 TC1 TO TC24: TRANSMIT CHANNEL REGISTERS (Address=40 to 4F and 50 to 57 Hex) (for brevity, only channel one is shown; see Table 1–3 for other register address) (MSB) (LSB) C7 C6 SYMBOL POSITION C7 TC1.7 MSB of the Code (this bit is transmitted first) C0 TC1.
DS2152 RMR1/RMR2/RMR3: RECEIVE MARK REGISTERS (Address=2D to 2F Hex) (MSB) (LSB) CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 TCC1 (16) CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 TCC2 (17) CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 TCC3 (18) SYMBOL POSITION NAME AND DESCRIPTION CH24 RCBR3.7 CH1 RCBR1.0 Receive Channel Blocking Registers.
DS2152 9.0 CLOCK BLOCKING REGISTERS The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking Registers (TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins respectively. The RCHBLK and TCHCLK pins are user programmable outputs that can be forced either high or low during indi- vidual channels. These outputs can be used to block clocks to a USART or LAPD controller in Fractional T1 or ISDN–PRI applications.
DS2152 10.1 RECEIVE SIDE If the receive side elastic store is enabled (CCR1.2=1), then the user must provide either a 1.544 MHz (CCR1.3=0) or 2.048 MHz (CCR1.3=1) clock at the RSYSCLK pin. The the user has the option of either providing a frame/multiframe sync at the RSYNC pin (RCR2.3=1) or having the RSYNC pin provide a pulse on frame boundaries (RCR2.3=0). If the user wishes to obtain pulses at the frame boundary, then RCR2.
DS2152 Performance Report Messages (PRM) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC controller automatically generates and detects flags, generates and checks the CRC check sum, generates and detects abort sequences, stuffs and destuffs zeros (for transparency), and byte aligns to the FDL data stream. The 16–byte buffers in the HDLC controller are large enough to allow a full PRM to be received or transmitted without host intervention.
DS2152 interrupts are present) when the user reads the event bit that caused the interrupt to occur. 11.1.3 Basic Operation Details To allow the DS2152 to properly source/receive data from/to the HDLC and BOC controller the legacy FDL circuitry (which is described in Section 11.2) should be disabled and the following bits should be programmed as shown: TCR1.2 = 1 (source FDL data from the HDLC and BOC controller) TBOC.6 = 1 (enable HDLC and BOC controller) CCR2.
DS2152 11.1.4 HDLC/BOC Register Description FDLC: FDL CONTROL REGISTER (Address=00 Hex) (MSB) RBR (LSB) RHR TFS THR TABT TEOM TZSD TCRCD SYMBOL POSITION NAME AND DESCRIPTION RBR FDLC.7 Receive BOC Reset. A 0 to 1 transition will reset the BOC circuitry. Must be cleared and set again for a subsequent reset. RHR FDLC.6 Receive HDLC Reset. A 0 to 1 transition will reset the HDLC controller. Must be cleared and set again for a subsequent reset. TFS FDLC.5 Transmit Flag/Idle Select.
DS2152 RPS FDLS.5 Receive Packet Start. Set when the HDLC controller detects an opening byte. The setting of this bit prompts the user to read the RPRM register for details. RHALF FDLS.4 Receive FIFO Half Full. Set when the receive 16–byte FIFO fills beyond the half way point. The setting of this bit prompts the user to read the RPRM register for details. RNE FDLS.3 Receive FIFO Not Empty. Set when the receive 16–byte FIFO has at least one byte available for a read.
DS2152 TNF FIMR.1 Transmit FIFO Not Full. 0 = interrupt masked 1 = interrupt enabled TMEND FIMR.0 Transmit Message End. 0 = interrupt masked 1 = interrupt enabled RPRM: RECEIVE PRM REGISTER (Address=03 Hex) (MSB) RABT (LSB) RCRCE ROVR RVM REMPTY POK CBYTE OBYTE SYMBOL POSITION NAME AND DESCRIPTION RABT RPRM.7 Abort Sequence Detected. Set whenever the HDLC controller sees 7 or more ones in a row. RCRCE RPRM.6 CRC Error. Set when the CRC checksum is in error. ROVR RPRM.5 Overrun.
DS2152 BOC5 RBOC.5 BOC Bit 5. Last bit received of the 6–bit codeword. BOC4 RBOC.4 BOC Bit 4. BOC3 RBOC.3 BOC Bit 3. BOC2 RBOC.2 BOC Bit 2. BOC1 RBOC.1 BOC Bit 1. BOC0 RBOC.0 BOC Bit 0. First bit received of the 6–bit codeword. NOTE: 1. The LBD bit is latched and will be cleared when read. 2. The RBOC0 to RBOC5 bits display the last valid BOC code verified; these bits will be set to all ones on reset.
DS2152 TFULL TPRM.1 Transmit FIFO Full. A real–time bit that is set high when the FIFO is full. UDR TPRM.0 Underrun. Set when the transmit FIFO unwantedly empties out and an abort is automatically sent. NOTE: The UDR bit is latched and will be cleared when read. TBOC: TRANSMIT BOC REGISTER (Address=07 Hex) (MSB) SBOC (LSB) HBEN BOC5 BOC4 BOC3 BOC2 BOC1 BOC0 SYMBOL POSITION NAME AND DESCRIPTION SBOC TBOC.7 Send BOC. Rising edge triggered.
DS2152 11.2 LEGACY FDL SUPP0RT 11.2.1 Overview In order to provide backward compatibility to the older DS2151 device, the DS2152 maintains the circuitry that existed in the previous generation of T1 Single–Chip Transceivers. Section 11.2 covers the circuitry and operation of this legacy functionality. In new applications, it is recommended that the HDLC controller and BOC controller described in Section 11.1 be used.
DS2152 11.2.3 Transmit Section The transmit section will shift out into the T1 data stream, either the FDL (in the ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the Transmit FDL register (TFDL). When a new value is written to the TFDL, it will be multiplexed serially (LSB first) into the proper position in the outgoing T1 data stream.
DS2152 be selected via the IBCC register. The DS2152 will detect repeating pattern codes in both framed and unframed circumstances with bit error rates as high as 10**–2. The code detector has a nominal integration period of 48 ms. Hence, after about 48 ms of receiving either code, the proper status bit (RUP at SR1.7 and RDN at SR1.6) will be set to a one. Normally codes are sent for a period of 5 seconds.
DS2152 C5 TCD.5 Transmit Code Definition Bit 5. C4 TCD.4 Transmit Code Definition Bit 4. C3 TCD.3 Transmit Code Definition Bit 3. C2 TCD.2 Transmit Code Definition Bit 2. A Don’t Care if a 5 bit length is selected. C1 TCD.1 Transmit Code Definition Bit 1. A Don’t Care if a 5 or 6 bit length is selected. C0 TCD.0 Transmit Code Definition Bit 0. A Don’t Care if a 5, 6 or 7 bit length is selected.
DS2152 C4 RDNCD.4 Receive Down Code Definition Bit 4. A Don’t Care if a 1 to 3 bit length is selected. C3 RDNCD.3 Receive Down Code Definition Bit 3. A Don’t Care if a 1 to 4 bit length is selected. C2 RDNCD.2 Receive Down Code Definition Bit 2. A Don’t Care if a 1 to 5 bit length is selected. C1 RDNCD.1 Receive Down Code Definition Bit 1. A Don’t Care if a 1 to 6 bit length is selected. C0 RDNCD.0 Receive Down Code Definition Bit 0. A Don’t Care if a 1 to 7 bit length is selected. 13.
DS2152 LICR: LINE INTERFACE CONTROL REGISTER (Address=7C Hex) (MSB) L2 (LSB) L1 L0 EGL JAS JABDS DJA TPD LICR SYMBOL POSITION NAME AND DESCRIPTION L2 LICR.7 Line Build Out Select Bit 2. Sets the transmitter build out; see the Table 14–2 L1 LICR.6 Line Build Out Select Bit 1. Sets the transmitter build out; see the Table 14–2 L0 LICR.5 Line Build Out Select Bit 0. Table 14–2 EGL LICR.4 Receive Equalizer Gain Limit. 0 = –36 dB 1 = –30 dB JAS LICR.3 Jitter Attenuator Select.
DS2152 LINE BUILD OUT SELECT IN LICR Table 14.2 L2 L1 L0 LINE BUILD OUT APPLICATION 0 0 0 0 to 133 feet / 0dB DSX–1 / CSU 0 0 1 133 to 266 feet DSX–1 0 1 0 266 to 399 feet DSX–1 0 1 1 399 to 533 feet DSX–1 1 0 0 533 to 655 feet DSX–1 1 0 1 –7.5 dB CSU 1 1 0 –15 dB CSU 1 1 1 –22.5 dB CSU Due to the nature of the design of the transmitter in the DS2152, very little jitter (less then 0.
DS2152 DS2152 EXTERNAL ANALOG CONNECTIONS Figure 14–1 Rt 0.47 uF (non– polarized) DS2152 TTIP T1 TRANSMIT LINE Rt TRING 1.15:1 (Rt = 0 Ohms) or 1.36:1 (Rt = 4.7 Ohms) (larger winding toward the network) DVDD DVSS RVSS TVDD TVSS RTIP RRING 60 0. 01u F RVDD T1 RECEIVE LINE +5V 0. 1 uF 61 18 19 0. 1 uF 31 30 0. 1 uF XTALD 1.544 MHz MCLK C1/C2 1:1 50 50 0.1 uF –or– XTALD MCLK 1.544 MHz NOTES: 1. Resistor values are ± 1%. 2.
DS2152 DS2152 JITTER TOLERANCE Figure 14–2 1K DS2152 TOLERANCE UNIT INTERVALS (UIpp) 100 10 MINIMUM TOLERANCE LEVEL AS PER TR 62411 (DEC. 90) 1 0.1 1 10 100 1K FREQUENCY (Hz) 10K 100K DS2152 TRANSMIT WAVEFORM TEMPLATE Figure 14–3 1.2 MAXIMUM CURVE UI Time Amp. 1.1 –0.77 –0.39 –0.27 –0.27 –0.12 0.00 0.27 0.35 0.93 1.16 1.0 0.9 0.8 0.7 –0.77 –0.23 –0.23 –0.15 0.00 0.15 0.23 0.23 0.46 0.66 0.93 1.16 –500 0.05 –255 0.05 –175 0.80 –175 1.15 –75 1.15 0 1.05 175 1.05 225 –0.07 600 0.05 750 0.
DS2152 DS2152 JITTER ATTENUATION Figure 14–4 0 dB J I T T E R A T T E N U A T IO N ( d B ) TR 62411 (DEC. 90) PROHIBITED AREA CURVE A –20 dB CURVE B –40 dB DS2152 JITTER ATTENUATION CURVE –60 dB 1 10 100 1K 10K 100K FREQUENCY (Hz) 15.0 TIMING DIAGRAMS RECEIVE SIDE D4 TIMING Figure 15–1 FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 RSYNC1/ RFSYNC RSYNC2 RSYNC3 RLINK RLINK4 NOTES: 1. RSYNC in the frame mode (RCR2.4=0) and double–wide frame sync is not enabled (RCR2.5=0). 2.
DS2152 RECEIVE SIDE BOUNDARY TIMING (WITH ELASTIC STORE DISABLED) Figure 15–2 FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 RSYNC1/ RFSYNC RSYNC2 RSYNC3 RLCLK4 RLINK5 RLCLK6 RLINK7 NOTES: 1. RSYNC in the frame mode (RCR2.4=0) and double–wide frame sync is not enabled (RCR2.5=0). 2. RSYNC in the frame mode (RCR2.4=0) and double–wide frame sync is enabled (RCR2.5=1). 3. RSYNC in the multiframe mode (RCR2.4=1). 4. ZBTSI mode disabled (RCR2.6=0). 5.
DS2152 RECEIVE SIDE 1.544 MHz BOUNDARY TIMING (WITH ELASTIC STORE ENABLED) Figure 15–4 RSYSCLK CHANNEL 23 CHANNEL 24 RSER CHANNEL 1 LSB MSB LSB F MSB RSYNC1 RMSYNC RSYNC2 CHANNEL 23 RSIG A B CHANNEL 24 C/A D/B A B CHANNEL 1 C/A D/B A RCHCLK RCHBLK3 NOTES: 1. RSYNC is in the output mode (RCR2.3=0). 2. RSYNC is in the input mode (RCR2.3=1). 3. RCHBLK is programmed to block channel 24. RECEIVE SIDE 2.
DS2152 TRANSMIT SIDE D4 TIMING Figure 15–6 1 FRAME# 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 TSYNC1/ TFSYNC TSYNC2 TSYNC3 TLCLK RCHBLK4 NOTES: 1. TSYNC in the frame mode (TCR2.3=0) and double–wide frame sync is not enabled (TCR2.4=0). 2. TSYNC in the frame mode (TCR2.3=0) and double–wide frame sync is enabled (TCR2.4=1). 3. TSYNC in the multiframe mode (TCR2.3=1). 4.
DS2152 TRANSMIT SIDE BOUNDARY TIMING Figure 15–8 TCLK CHANNEL 1 TSER LSB F CHANNEL 2 MSB LSB MSB LSB MSB TSYNC1 ÉÉ ÉÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉÉ ÉÉ ÉÉ ÉÉ ÉÉ TSYNC2 CHANNEL 1 TSIG A ÉÉ ÉÉÉ ÉÉ ÉÉ ÉÉ ÉÉÉ ÉÉ ÉÉ CHANNEL 2 B C/A TCHCLK D/B A B C/A ÉÉ ÉÉ ÉÉ ÉÉ D/B TCHBLK3 TLCLK TLINK4 DON’T CARE NOTES: 1. TSYNC is in the output mode (TCR2.2=1). 2. TSYNC is in the input mode (TCR2.2=0). 3. TCHBLK is programmed to block channel 2. 4. Shown is TLINK/TLCLK in the ESF framing mode. TRANSMIT SIDE 1.
DS2152 TRANSMIT SIDE 2.048 MHz BOUNDARY TIMING(WITH ELASTIC STORE ENABLED) Figure 15–10 TSYSCLK CHANNEL 31 CHANNEL 32 TSER1 ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ TSSYNC TSIG TCHCLK CHANNEL 31 A B C/A ÉÉ ÉÉ ÉÉÉ ÉÉ ÉÉ ÉÉ ÉÉÉ ÉÉ D/B CHANNEL 32 A B ÉÉ ÉÉÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ CHANNEL 1 LSB LSB MSB F4 CHANNEL 1 C/A D/B TCHBLK2, 3 NOTES: 1. TSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 is ignored. 2.
DS2152 DS2152 TRANSMIT DATA FLOW Figure 15–11 TSER/ TDATA TC1 TO TC24 1 TCC1 TO TCC3 0 PER–CHANNEL CODE GENERATION IBCC IN–BAND LOOP TIR FUNCITON SELECT (CCR4.0) TDR CODE GENERATOR 0 CCR3.1 TIDR RSER 1 0 (note#1) 1 IDLE CODE/PER TIR1 to TIR3 CHANNEL LB TS1 to TS12 0 1 ROBBED BIT SIGNALING ENABLE (TCR1.4) SIGNALING MUX TIR1 to TTR3 TTR1 to TTR3 GLOBAL BIT 7 STUFFING (TCR1.3) BIT 7 ZERO SUPPRESSION ENABLE (TCR2.0) BIT 7 STUFFING FRAME MODE SELECT (CCR2.7) D4 YELLOW ALARM SELECT (TCR2.
DS2152 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature for DS2152L Operating Temperature for DS2152LN Storage Temperature Soldering Temperature –1.0V to +7.0V 0°C to 70°C –40°C to +85°C –55°C to +125°C 260°C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied.
DS2152 AC CHARACTERISTICS – MULTIPLEXED PARALLEL PORT (MUX=1) (0°C to 70°C; VDD=5V ± 5% for DS2152L; –40°C to +85°C; VDD=5V ± 5% for DS2152LN) PARAMETER SYMBOL MIN tCYC 200 ns Pulse Width, DS low or RD high PWEL 100 ns Pulse Width, DS high or RD low PWEH 100 ns Input Rise/Fall times tR, tF R/W Hold Time tRWH 10 ns R/W Set Up time before DS high tRWS 50 ns CS Set Up time before DS, WR or RD active tCS 20 ns CS Hold time tCH 0 ns Read Data Hold time tDHR 10 Write Data Hold
DS2152 (0°C to 70°C; VDD=5V ± 5% for DS2152L; –40°C to +85°C; VDD=5V ± 5% for DS2152LN) AC CHARACTERISTICS – RECEIVE SIDE PARAMETER SYMBOL RCLKO Period tLP RCLKO Pulse Width tLH tLL RCLKO Pulse Width tLH tCL RCLKI Period tCP RCLKI Pulse Width tCH tCL 75 75 RSYSCLK Period tSP tSP 122 122 RSYSCLK Pulse Width tSH tSL 50 50 RSYNC Set Up to RSYSCLK Falling tSU 20 RSYNC Pulse Width tPW 50 ns RPOSI/RNEGI Set UP to RCLKI Falling tSU 20 ns RPOSI/RNEGI Hold From RCLKI Falling tHD 20
DS2152 (0°C to 70°C; VDD=5V ± 5% for DS2152L; –40°C to +85°C; VDD=5V ± 5% for DS2152LN) AC CHARACTERISTICS – TRANSMIT SIDE PARAMETER SYMBOL TCLK Period tCP TCLK Pulse Width tCH tCL TCLKI Period tLP TCLKI Pulse Width tLH tLL 75 75 TSYSCLK Period tSP tSP 122 122 TSYSCLK Pulse Width tSH tSL 50 50 TSYNC or TSSYNC Set Up to TCLK or TSYSCLK falling tSU 20 TSYNC or TSSYNC Pulse Width tPW 50 ns TSER, TSIG, TDATA, TLINK, TPOSI, TNEGI Set Up to TCLK, TSYSCLK, TCLKI Falling tSU 20 ns TSER
DS2152 AC CHARACTERISTICS – NON–MULTIPLEXED PARALLEL PORT (MUX=0 ) (0°C to 70°C; VDD=5V ± 5% for DS2152L; –40°C to +85°C; VDD=5V ± 5% for DS2152LN) PARAMETER SYMBOL MIN Set Up Time for A0 to A7 Valid to CS Active t1 0 TYP MAX ns Set Up Time for CS Active to either RD, WR, or DS Active t2 0 ns Delay Time from either RD or DS Active to Data Valid t3 Hold Time from either RD, WR, or DS Inactive to CS Inactive t4 0 Hold Time from CS Inactive to Data Bus 3–state t5 5 Wait Time from either W
DS2152 INTEL BUS WRITE AC TIMING (BTS=0/MUX=1) Figure 16–2 tCYC PWASH ALE tASD RD tASED tASD PWEH PWEL WR tCH tCS CS tASL tDHW AD0-AD7 tAHL tDSW MOTOROLA BUS AC TIMING (BTS=1/MUX=1) Figure 16–3 PWASH AS PWEH DS tASD tASED PWEL tCYC tRWS tRWH R/W tASL tDDR tDHR AD0-AD7 (READ) tAHL tCH tCS CS AD0-AD7 (WRITE) tASL tDSW tAHL 031897 72/79 tDHW
DS2152 RECEIVE SIDE AC TIMING Figure 16–4 RCLK tD1 RSER/RDATA/RSIG tD2 RCHCLK tD2 RCHBLK tD2 RFSYNC/RMSYNC tD2 RSYNC1 tD2 RLCLK2 tD1 RLINK NOTES: 1. RSYNC is in the output mode (RCR2.3=0). 2. Shown is RLINK/RLCLK in the ESF framing mode. 3. No relationship between RCHCLK and RCHBLK and the other signals is implied.
DS2152 RECEIVE SYSTEM SIDE AC TIMING Figure 16–5 tR tSL tF tSH RSYSCLK tSP tD3 RSER/RSIG tD4 RCHCLK tD4 RCHBLK tD4 RMSYNC tD4 RSYNC1 tPW tSU RSYNC2 NOTES: 1. RSYNC is in the output mode (RCR2.3=0). 2. RSYNC is in the input mode (RCR2.3=1).
DS2152 TRANSMIT SIDE AC TIMING Figure 16–7 tCP tR tCL tF tCH TCLK tD1 TESO tSU TSER/TSIG/ TDATA tHD tD2 TCHCLK tD2 TCHBLK tD2 TSYNC1 tPW tSU TSYNC2 tD2 TLCLK5 tHD TLINK tSU NOTES: 1. TSYNC is in the output mode (TCR2.2=1). 2. TSYNC is in the input mode (TCR2.2=0). 3. TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled. 4. TCHCLK and TCHBLK are synchronous with TCLK when the transmit side elastic store is disabled. 5.
DS2152 TRANSMIT SYSTEM SIDE AC TIMING Figure 16–8 tSP tR tSL tF tSH TSYSCLK tSU TSER tHD tD3 TCHCLK tD3 TCHBLK tPW tSU TSSYNC NOTES: 1. TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled. 2. TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit side elastic store is enabled.
DS2152 INTEL BUS READ AC TIMING (BTS=0/MUX=0) Figure 16–10 A0 TO A7 ADDRESS VALID D0 TO D7 DATA VALID 5 ns min. / 20 ns max. WR t1 t5 0 ns min. CS 0 ns min. t2 t3 t4 0 ns min. 75 ns max. RD INTEL BUS WRITE AC TIMING (BTS=0/MUX=0) Figure 16–11 t9 10 ns min. A0 TO A7 ADDRESS VALID D0 TO D7 t7 RD t1 t8 10 ns 10 ns min. min. 0 ns min. CS 0 ns min. t2 t6 t4 0 ns min. 75 ns min.
DS2152 MOTOROLA BUS WRITE AC TIMING (BTS=1/MUX=0) Figure 16–13 t9 10 ns min. A0 TO A7 ADDRESS VALID D0 TO D7 t7 t8 10 ns 10 ns min. min. R/W t1 0 ns min. CS 0 ns min. t2 t6 75 ns min. DS 031897 78/79 t4 0 ns min.
DS2152 DS2152 100–PIN LQFP PKG 100–PIN DIM MIN MAX A – 1.60 A1 0.05 – A2 1.35 1.45 B 0.17 0.27 C 0.09 0.20 D 15.80 16.20 D1 E 14.00 BSC 15.80 16.20 E1 14.00 BSC e 0.50 BSC L 0.45 0.
