Owner's manual
DS2152
031897 16/79
3.0 CONTROL, ID AND TEST REGISTER
The operation of the DS2152 is configured via a set of
eleven control registers. Typically, the control registers
are only accessed when the system is first powered up.
Once the DS2152 has been initialized, the control regis-
ters will only need to be accessed when there is a
change in the system configuration. There are two
Receive Control Register (RCR1 and RCR2), two
Transmit Control Registers (TCR1 and TCR2), and
seven Common Control Registers (CCR1 to CCR7).
Each of the eleven registers are described in this
section.
There is a device IDentification Register (IDR) at
address 0Fh. The MSB of this read–only register is
fixed to a zero indicating that the DS2152 is present.
The E1 pin–for–pin compatible version of the DS2152 is
the DS2154 and it also has an ID register at address 0Fh
and the user can read the MSB to determine which chip
is present since in the DS2152 the MSB will be set to a
zero and in the DS2154 it will be set to a one. The lower
four bits of the IDR are used to display the die revision of
the chip.
IDR: DEVICE IDENTIFICATION REGISTER (Address=0F Hex)
(MSB) (LSB)
T1E1 0 0 0 ID3 ID2 ID1 ID0
SYMBOL POSITION NAME AND DESCRIPTION
T1E1 IDR.7 T1 or E1 Chip Determination Bit.
0=T1 chip
1=E1 chip
ID3 IDR.3 Chip Revision Bit 3. MSB of a decimal code that represents the chip revi-
sion.
ID2 IDR.1 Chip Revision Bit 2.
ID1 IDR.2 Chip Revision Bit 1.
ID0 IDR.0 Chip Revision Bit 0. LSB of a decimal code that represents the chip revi-
sion.
The two Test Registers at addresses 09 and 7D hex are used by the factory in testing the DS2152. On power–up, the
Test Registers should be set to 00 hex in order for the DS2152 to operate properly.
RCR1: RECEIVE CONTROL REGISTER 1 (Address=2B Hex)
(MSB) (LSB)
LCVCRF
ARC OOF1 OOF2 SYNCC SYNCT SYNCE RESYNC
SYMBOL POSITION NAME AND DESCRIPTION
LCVCRF RCR1.7 Line Code Violation Count Register Function Select.
0 = do not count excessive zeros
1 = count excessive zeros
ARC RCR1.6 Auto Resync Criteria.
0 = Resync on OOF or RCL event
1 = Resync on OOF only
OOF1 RCR1.5 Out Of Frame Select 1.
0 = 2/4 frame bits in error
1 = 2/5 frame bits in error