Instruction Manual

ManualsBrandsRainbow Electronics ManualsCommunicationDS2165Q

patents and other intellectual property rights, please refer to

Dallas Semiconductor data books.

DS2165/DS2165Q

16/24/32Kbps ADPCM Processor

DS2165/DS2165Q

041295 1/17

FEATURES

• Compresses/expands 64Kbps PCM voice to/from

either 32Kbps, 24Kbps, or 16Kbps

• Dual, fully independent channel architecture; device

can be programmed to perform either:

– two expansions

– two compressions

– one expansion and one compression

• Interconnects directly to combo-codec devices

• Input to output delay is less than 375 µs

• Simple serial port used to configure the device

• Onboard Time Slot Assigner Circuit (TSAC) function

allows data to be input/output at various time slots

• Supports Channel Associated Signaling

• Each channel can be independently idled or placed

into bypass

• Available hardware mode requires no host processor;

ideal for voice storage applications

• Backward-compatible with the DS2167 ADPCM

Processor Chip

• Single +5V supply; low-power CMOS technology

• Available in 24-pin DIP and 28-pin PLCC

PIN ASSIGNMENT

24-Pin DIP (600 MIL)

RST

TM0

TM1

SPS

MCLK

VSS

VDD

YIN

CLKY

FSY

YOUT

SDI

SCLK

XOUT

FSX

CLKX

XIN

432

12 13 14 15 16 17 18

FSY

YOUT

SCLK

SDI

XOUT

TM1

RST

VDD

YINCLKX

XIN

FSX

SPS

MCLK

VSS

TM0

CLKY

28-Pin PLCC

A 3–volt Operation Version

is Available (DS2165QL)

DESCRIPTION

The DS2165 ADPCM Processor Chip is a dedicated

Digital Signal Processing (DSP) chip that has been opti-

mized to perform Adaptive Differential Pulse Code Mod-

ulation (ADPCM) speech compression at three different

rates. The chip can be programmed to compress (ex-

pand) 64Kbps voice data down to (up from) either

32Kbps, 24Kbps, or 16Kbps. The compression to

32Kbps follows the algorithm specified by CCITT Rec-

ommendation G.721 (July 1986) and ANSI document

T1.301 (April 1987). The compression to 24Kbps fol-

lows ANSI document T1.303. The compression to

16Kbps follows a proprietary algorithm developed by

Dallas Semiconductor. The DS2165 can switch com-

pression algorithms on-the-fly. This allows the user to

make maximum use of the available bandwidth on a dy-

namic basis.

Summary of content (17 pages)

PAGE 1
DS2165/DS2165Q DS2165/DS2165Q 16/24/32Kbps ADPCM Processor PIN ASSIGNMENT • Compresses/expands 64Kbps PCM voice to/from either 32Kbps, 24Kbps, or 16Kbps RST 1 24 VDD TM0 2 23 YIN TM1 3 22 CLKY A0 4 FSY A1 5 21 20 A2 6 19 CS A3 7 18 SDI A4 8 9 17 SCLK SPS 10 15 FSX MCLK 11 CLKX VSS 12 14 13 • Dual, fully independent channel architecture; device can be programmed to perform either: – two expansions – two compressions – one expansion and one compression • Interconn
PAGE 2
DS2165/DS2165Q OVERVIEW The DS2165 contains three major functional blocks: a high performance (10 MIPS) DSP engine, two independent PCM interfaces (X and Y) which connect directly to serial Time Division Multiplexed (TDM) backplanes, and a serial port that can configure the device on-the-fly via an external controller. A 10 MHz master clock is required by the DSP engine. The DS2165 can be configured to perform either two expansions, two compressions, or one expansion and one compression.
PAGE 3
DS2165/DS2165Q PIN DESCRIPTION Table 1 PIN SYMBOL TYPE DESCRIPTION 1 RST I Reset. A high-low-high transition resets the algorithm. The device should be reset on power up and when changing to or from the hardware mode. 2 3 TM0 TM1 I Test Modes 0 and 1. Tie to VSS for normal operation. 4 5 6 7 8 9 A0 A1 A2 A3 A4 A5 I Address Select. A0 = LSB; A5 = MSB Must match address/command word to enable the serial port. 10 SPS I Serial Port Select.
PAGE 4
DS2165/DS2165Q DS2165 BLOCK DIAGRAM Figure 1 FSX CLKX XIN X SIDE PCM/ADPCM DATA INTERFACE XOUT MCLK SCLK SPS CS SDI ADPCM PROCESSING ENGINE SERIAL PORT CONTROL/ HARDWARE MODE LOGIC A0 - A5 FSY CLKY Y SIDE PCM/ADPCM DATA INTERFACE YIN YOUT VDD RST VSS RESET AND TEST LOGIC TM0 TM1 SERIAL PORT WRITE Figure 2 ÉÉ ÉÉ A0 A1 A2 A3 A4 A5 X/Y 0 ADDRESS/COMMAND CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 ÉÉ ÉÉ ÉÉ ÉÉ CONTROL NOTE: 1. A 2-byte write is shown.
PAGE 5
DS2165/DS2165Q ADDRESS/COMMAND BYTE Figure 3 (MSB) – (LSB) X/Y A5 SYMBOL – X/Y POSITION ACB.7 ACB.6 A5 A4 A3 A2 A1 A0 ACB.5 ACB.4 ACB.3 ACB.2 ACB.1 ACB.0 A4 A3 A2 A1 A0 NAME AND DESCRIPTION Reserved; must be 0 for proper operation X/Y Channel Select 0 = update channel Y characteristics 1 = update channel X characteristics MSB of Device Address LSB of Device Address CONTROL REGISTER Figure 4 (MSB) AS0 (LSB) AS1 IPD SYMBOL AS0 AS1 IPD POSITION CR.7 CR.6 CR.5 ALRST CR.4 BYP CR.
PAGE 6
DS2165/DS2165Q INPUT TIME SLOT REGISTER Figure 5 (MSB) – (LSB) – SYMBOL D5 D4 D3 D2 D1 D0 D5 D4 POSITION ITR.7 ITR.6 ITR.5 ITR.4 ITR.3 ITR.2 ITR.1 ITR.0 D3 D2 D1 D0 NAME AND DESCRIPTION Reserved; must be 0 for proper operation. Reserved; must be 0 for proper operation. MSB of input time slot register. LSB of input time slot register. OUTPUT TIME SLOT REGISTER Figure 6 (MSB) – SYMBOL D5 D4 D3 D2 D1 D0 (LSB) – D5 D4 POSITION OTR.7 OTR.6 OTR.5 OTR.4 OTR.3 OTR.2 OTR.1 OTR.
PAGE 7
DS2165/DS2165Q DS2165 µ-LAW PCM INTERFACE Figure 7 TIME SLOT 0 TIME SLOT N TIME SLOT 31 TIME SLOT 0 ...
PAGE 8
DS2165/DS2165Q DS2165 A-LAW ADPCM INTERFACE Figure 10 TIME SLOT 0 TIME SLOT 1 TIME SLOT N TIME SLOT 62 TIME SLOT 63 TIME SLOT 0 CLKX, CLKY FSX, FSY MSB LSB DON’T CARE XIN, YIN XOUT, YOUT 3-STATE DON’T CARE MSB LSB 3-STATE HARDWARE MODE The hardware mode is intended for applications that do not have an external controller available or do not require the extended features offered by the serial port.
PAGE 9
DS2165/DS2165Q ALGORITHM SELECT FOR HARDWARE MODE Table 4 ALGORITHM CONFIGURATION OF A1 AND A4 64Kbps to/from 32Kbps Tie both A1 and A4 to VSS. 64Kbps to/from 24Kbps Hold A1 and A4 low during a hardware reset; take both A1 and A4 high after the RST pin has returned high (allow 3 µs after RST returns high before taking A1 and A4 high). 64Kbps to/from 16Kbps Tie both A1 and A4 to VDD.
PAGE 10
DS2165/DS2165Q PCM AND ADPCM INPUT/OUTPUT Since the organization of the input and output time slots on the DS2165 does not depend on the algorithm selected, it always assumes that PCM input and output will be in 8-bit bytes and that ADPCM input and output will be in 4-bit bytes. Figure 12 demonstrates how the DS2165 handles the I/O for the three different algo- rithms. In the figure, it is assumed that channel X is in the compression mode (CP/EX = 1) and channel Y is in the expansion mode (CP/EX = 0).
PAGE 11
DS2165/DS2165Q TIME SLOT RESTRICTIONS Under certain conditions, the DS2165 does contain some restrictions on the output time slots that are available. These restrictions are covered in detail in a separate application note. No restrictions occur if the DS2165 is operated in the hardware mode. INPUT TO OUTPUT DELAY With all three compressions algorithms, the total delay, from the time the PCM data sample is captured by the DS2165 to the time it is output, is always less than 375 µs.
PAGE 12
DS2165/DS2165Q ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -1.0V to +7.0V 0°C to 70°C -55°C to +125°C 260°C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
PAGE 13
DS2165/DS2165Q PCM INTERFACE AC ELECTRICAL CHARACTERISTICS PARAMETER CLKX, CLKY Period CLKX, CLKY Pulse Width (0°C to 70°C; VDD=5V +10%) (VDD=3.
PAGE 14
DS2165/DS2165Q SERIAL PORT AC ELECTRICAL CHARACTERISTICS PARAMETER (0°C to 70°C; VDD=5V + 10%) (VDD=3.0V + 20% – 10% for DS2165QL) SYMBOL MIN SDI to SCLK Set Up tDC SCLK to SDI Hold SCLK Low Time SCLK High Time SCLK Rise and Fall Time TYP MAX UNITS NOTES 55 ns 1 tCDH 55 ns 1 tCL 250 ns 1 tCH 250 ns 1 ns 1 tR, tF 100 CS to SCLK Setup tCC 50 ns 1 SCLK to CS Hold tCCH 250 ns 1 CS Inactive Time tCWH 250 ns 1 SCLK Setup to CS Falling tSCC 50 ns 1 NOTE: 1.
PAGE 15
DS2165/DS2165Q MASTER CLOCK/RESET AC TIMING DIAGRAM Figure 14 tPM tFM tRM tWMH tWML MCLK tRST RST SERIAL PORT AC TIMING DIAGRAM Figure 15 tCWH CS tCWH tSCC tCC tR tCH tF tCCH SCLK tCL tDC SDI tCDH NOTE: 1. SCLK may be either high or low when CS is taken low.
PAGE 16
DS2165/DS2165Q DS2165 16/24/32KBPS ADPCM PROCESSOR 24–PIN DIP B 1 A D E C F K G PKG 24-PIN DIM MIN MAX A IN. MM 1.150 29.21 1.260 32.00 B IN. MM 0.250 6.35 0.270 6.86 C IN. MM 0.120 3.05 0.140 3.56 D IN. MM 0.300 7.62 0.325 8.26 E IN. MM 0.015 0.38 0.040 1.02 F IN. MM 0.125 3.18 0.135 3.48 G IN. MM 0.090 2.23 0.110 2.79 H IN MM 0.320 8.13 0.370 9.40 J IN MM 0.008 0.20 0.012 0.30 K IN. MM 0.015 0.38 0.022 0.
PAGE 17
DS2165/DS2165Q DS2165Q 16/24/32KBPS ADPCM PROCESSOR 28-PIN PLCC E E1 B L1 N 1 D1 D D2 B1 CH1 e1 C A E2 A2 A1 INCHES DIM MIN MAX A 0.165 0.180 A1 0.090 0.120 A2 0.020 – B 0.026 0.033 B1 0.013 0.021 C 0.009 0.012 D 0.485 0.495 D1 0.450 0.456 D2 0.390 0.430 E 0.485 0.495 E1 0.450 0.456 E2 0.390 0.430 L1 0.060 – N 28 – e1 CH1 This drawing controlled by drawing number 56–G4001–001. 0.050 BSC 0.042 0.