Manual

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FEATURES

§ 4096 bits of nonvolatile dual-port memory

including real time clock/calendar in binary

format, programmable interval timer, and

programmable power-on cycle counter

§ 1-Wire

interface for MicroLAN

communication at 16.3kbits/s

§ 3-wire host interface for high-speed data

communications at 2Mb/s

§ Unique, factory-lasered and tested 64-bit

registration number (8-bit family code +

48-bit serial number + 8-bit CRC tester)

assures absolute traceability because no two

parts are alike

§ Memory partitioned into 16 pages of 256-bits

for packetizing data

§ 256-bit scratchpad with strict read/write

protocols ensures integrity of data transfer

§ Programmable alarms can be set to generate

interrupts for interval timer, real time clock,

and/or cycle counter

§ 16-pin DIP, SO, and SSOP packages

§ Operating temperature range from -40°C to

+85°C

§ Operating voltage range from 2.8V to 5.5V

ORDERING INFORMATION

DS2404-001 16-pin DIP

DS2404S-001 16-pin SO

DS2404B 16-pin SSOP

DS2404S-001/T&R Tape and Reel of S2404S-001

DS2404B/T&R Tape and Reel of DS2404B

PIN ASSIGNMENT

PIN DESCRIPTION

– 2.8 to 5.5V

IRQ – Interrupt Output

RST – 3-Wire Reset Input

DQ – 3-Wire Input/Output

I/O – 1-Wire Input/Output

CLK – 3-Wire Clock Input

NC – No Connection

GND – Ground

BATB

– Battery Backup Input

BATO

– Battery Operate Input

1Hz – 1Hz Output

, X2 – Crystal Connections

DESCRIPTION

The DS2404 EconoRAM Time Chip offers a simple solution for storing and retrieving vital data and time

information with minimal hardware. The DS2404 contains a unique lasered ROM, real-time

clock/calendar, interval timer, cycle counter, programmable interrupts, and 4096-bits of SRAM. Two

separate ports are provided for communication: 1-Wire and 3-wire. Using the 1-Wire port, only one pin is

required for communication, and the lasered-ROM can be read even when the DS2404 is without power.

The 3-wire port provides high-speed communication using the traditional Dallas Semiconductor 3-wire

interface. With either interface, a strict protocol for accessing the DS2404 ensures data integrity. Utilizing

backup energy sources, the data is nonvolatile (NV) and allows for stand-alone operation.

VCC 1 16 VCC

IRQ 2 15 X1

RST 3 14 X2

DQ 4 13 GND

I/O 5 12 NC

CLK 6 11 1HZ

C 7 10VBATO

GND 8 9 VBATB

16-PIN DIP (300 MIL)

16-PIN SO (300 MIL)

16-PIN SSOP (208 MIL)

See Mechanical Drawings Section

DS2404

EconoRAM Time Chip

www.maxim-ic.com

Summary of content (29 pages)

PAGE 1
DS2404 EconoRAM Time Chip www.maxim-ic.com FEATURES § § § § § § § § § § PIN ASSIGNMENT 4096 bits of nonvolatile dual-port memory including real time clock/calendar in binary format, programmable interval timer, and programmable power-on cycle counter 1-Wire® interface for MicroLAN communication at 16.
PAGE 2
DS2404 The DS2404 features can be used to create a stopwatch, alarm clock, time and date stamp, logbook, hour meter, calendar, system power-cycle timer, expiration timer, and event scheduler. DETAILED PIN DESCRIPTION PIN 1,16 SYMBOL VCC 2 3 4 5 IRQ RST 6 7,12 8,13 9 CLK NC GND VBATB 10 VBATO 11 14,15 1Hz X1,X2 DQ I/O DESCRIPTION Power input pins for VCC operate mode. 2.8V to 5.5V operation. Either one can be used for VCC. Only one is required for normal operation.
PAGE 3
DS2404 4) skip ROM or 5) search interrupt. After a ROM function sequence has been successfully executed, the memory functions are accessible and the master may then provide any one of the four memory function commands (Figure 6). The “Power Control” section provides for two basic power configurations: battery operate mode and VCC operate mode. The battery operate mode utilizes one supply connected to VBATO.
PAGE 4
DS2404 Port selection is accomplished on a first-come, first-serve basis. Whichever port comes out of reset first will obtain control. For the 3-wire port, this is done by bringing RST high. For the 1-Wire port, this is done on the first falling edge of I/O after the reset and presence pulses. (See “1-Wire Signaling” section.) More information on how to arbitrate port access is found in section “Device Operation Modes” later in this document.
PAGE 5
DS2404 MEMORY MAP Figure 4 5 of 29
PAGE 6
DS2404 MEMORY The memory map in Figure 4 shows a page (32 bytes) called the scratchpad and 17 pages called memory. Pages 0 through 15 each contain 32 bytes which make up the 4096-bit SRAM. Page 16 has only 30 bytes which contain the timekeeping registers. The scratchpad is an additional page of memory that acts as a buffer when writing to memory. Data is first written to the scratchpad where it can be read back. After the data has been verified, a copy scratchpad command will transfer the data to memory.
PAGE 7
DS2404 Alarm Registers The alarm registers for the real-time clock, interval timer, and cycle counter all operate in the same manner. When the value of a given counter equals the value in its associated alarm register, the appropriate flag bit is set in the status register. If the corresponding interrupt enable bit(s) in the status register is set, an interrupt is generated. If a counter and its associated alarm register are write protected when an alarm occurs, access to the device becomes limited.
PAGE 8
DS2404 Setting a write protect bit to a logic 1 will permanently write protect the corresponding counter and alarm registers, all write protect bits, and additional bits in the control register. The write protect bits can not be written in a normal manner (see “Write Protect/Programmable Expiration” section). 3 RO Read Only If a programmable expiration occurs and the read only bit is set to a logic 1, then the DS2404 becomes read only.
PAGE 9
DS2404 The third register (E/S) is a read only register. The first five bits (E4: E0) of this register are called the ending offset. The ending offset is a byte offset within a page. Bit 5 (PF) is the partial byte flag. Bit 6 (OF) is the overflow flag. Bit 7 (AA) is the authorization accepted flag.
PAGE 10
DS2404 MEMORY FUNCTION FLOW CHART Figure 6 10 of 29
PAGE 11
DS2404 Read Memory [F0h] The read memory command may be used to read the entire memory. After issuing the command, the user must provide the 2-byte target address. After the two bytes, the user reads data beginning from the target address and may continue until the end of memory, at which point logic 1’s will be read. It is important to realize that the target address registers will contain the address provided. The ending offset/data status byte is unaffected.
PAGE 12
DS2404 Example 2: Write two data bytes to memory locations 0026h and 0027h (the seventh and eighth byte of page 1). Read entire memory (1-Wire port).
PAGE 13
DS2404 The write protect bits, once set, permanently write protects their corresponding counter and alarm registers, all write protect bits, and certain control register bits as shown in Figure 7. The time/count registers will continue to count if the oscillator is enabled. If the user wishes to set more than one write protect bit, the user must set them at the same time. Once a write protect bit is set it cannot be undone, and the remaining write protect bits, if not set, cannot be set.
PAGE 14
DS2404 HARDWARE CONFIGURATION Figure 8 See Note NOTE: Depending on 1-Wire communication speed and bus load characteristics, the optimal pull-up resistor value will be in the 1.5 kW range to 5 kW range. TRANSACTION SEQUENCE The protocol for accessing the DS2404 via the 1-Wire port is as follows: § Initialization § ROM Function Command § Memory Function Command § Transaction/Data INITIALIZATION All transactions on the 1-Wire bus begin with an initialization sequence.
PAGE 15
DS2404 Match ROM [55h] The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS2404 on a multidrop bus. Only the DS2404 that exactly matches the 64-bit ROM sequence will respond to the following memory function command. All slaves that do not match the 64-bit ROM sequence will wait for a reset pulse. This command can be used with a single or multiple devices on the bus.
PAGE 16
DS2404 ROM FUNCTIONS FLOW CHART (1-WIRE PORT ONLY) Figure 9 (See Figure 8) 16 of 29
PAGE 17
DS2404 1-WIRE SIGNALING The DS2404 requires strict protocols to ensure data integrity. The protocol consists of five types of signaling on one line: Reset Sequence with reset pulse and presence pulse, write 0, write 1, Read Data and interrupt pulse. All these signals except presence pulse and interrupt pulse are initiated by the bus master. The initialization sequence required to begin any communication with the DS2404 is shown in Figure 10.
PAGE 18
DS2404 READ/WRITE TIMING DIAGRAM Figure 11 Write-one Time Slot 60ms < tSLOT < 120ms 1ms £ tLOW1 < 15ms 1ms £ tREC < ¥ Write-zero Time Slot 60ms £ tLOW0 < tSLOT < 120ms 1ms £ tREC < ¥ Read-data Time Slot RESISTOR MASTER DS2404 60ms £ tSLOT < 120ms 1ms £ tLOWR < 15ms 0 £ tRELEASE < 45ms 1ms £ tREC < ¥ tRDV = 15ms tSU < 1ms 18 of 29
PAGE 19
DS2404 Interrupts If the DS2404 detects an alarm condition, it will automatically set the corresponding alarm flag (CCF, ITF or RTF) in the Status Register. If the flag’s corresponding interrupt bit ( RST , ITE or RTE ) is enabled (logic 0) an interrupt condition begins as the alarm goes off. The DS2404 signals the interrupt condition by pulling the open drain IRQ output low. The interrupt condition ceases when the alarm flags are cleared (i.e.
PAGE 20
DS2404 TYPE 1 INTERRUPT Figure 12 TYPE 1A INTERRUPT (SPECIAL CASE) Figure 13 DS2404 TYPE 2 INTERRUPT Figure 14 20 of 29
PAGE 21
DS2404 TYPE 2 INTERRUPT (SPECIAL CASE) Figure 15 3-WIRE I/O COMMUNICATIONS The 3–wire bus is comprised of three signals. These are the RST (reset) signal, the CLK (clock) signal, and the DQ (data) signal. All data transfers are initiated by driving the RST input high. Driving the RST input low terminates communication. (See Figures 19 and 20.) A clock cycle is a sequence of a falling edge followed by a rising edge. For data inputs, the data must be valid during the rising edge of a clock cycle.
PAGE 22
DS2404 VCC Operate Mode (Battery-Backed) Figure 16 shows the necessary connections for operating the DS2404 in VCC Operate mode. VCC OPERATE MODE Figure 16 VCC VBATB VBATO Pin 1 & 16 Pin 9 Pin 10 2.8V to 5.5V 2.8V to 5.5V must be unconnected To always allow communication through the 1-Wire or wire port, the voltage on VCC must be approximately 3-wire port, the voltage on VCC must be approximately 0.2V above the voltage on VBATB. Otherwise the DS2404 will retain data, but will not allow any access.
PAGE 23
DS2404 Battery Operate Mode Figure 17 shows the necessary connections for operating the DS2404 in Battery Operate mode. BATTERY OPERATE MODE Figure 17 VCC VBATB VBATO Pin 1 & 16 Pin 9 Pin 10 Ground Ground 2.8 to 5.5V The VBATO pin is normally connected to any standard 3 V lithium cell or other energy source. The Battery Operate mode also minimizes the power-consumption in applications where battery backup is not required and the VBATO lead is directly connected to the system’s 5V supply.
PAGE 24
DS2404 OPERATION MODES AND CONDITIONS Table 1 PORT USAGE BATTERY OPERATE MODE 1-Wire only 3-Wire only Float RST , DQ, CLK or tie to GND DQ Voltage (3-wire) £ VBATO DQ Voltage (3-wire) £ VCC +0.3V If unused: float I/O (1-Wire) or tie to GND; if used as counter input: see text DQ Voltage (3-wire) £ VBATO DQ Voltage (3-wire) £ VCC +0.
PAGE 25
DS2404 CRYSTAL PLACEMENT ON PCB Figure 18 3-WIRE WRITE DATA TIMING DIAGRAM Figure 19 3-WIRE READ DATA TIMING DIAGRAM Figure 20 25 of 29
PAGE 26
DS2404 ABSOLUTE MAXIMUM RATINGS* Voltage on DATA to Ground Operating Temperature Range Storage Temperature Range Soldering Temperature -0.5V to +7.0V -40°C to +85°C -55°C to +125°C See J-STD-020A Specification * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
PAGE 27
DS2404 CAPACITANCE PARAMETER Input Capacitance Output Capacitance I/O (1-Wire) (tA = 25°C) SYMBOL CIN COUT IIN/OUT MIN TYP 100 MAX 10 15 800 RESISTANCES PARAMETER RST Resistance to Ground DQ Resistance to Ground CLK Resistance to Ground SYMBOL ZRST ZDQ ZCLK MIN 8 SYMBOL tDC tCDH tCDD tCL tCH tCLK tR,tF tCC tCCH tCWH tCDZ SYMBOL tSLOT tLOW1 tLOW0 tLOWR tRDV tRELEASE tSU tREC tINT tRSTH tRSTL tPDH tPDL TYP 65 65 65 MAX UNITS kW kW kW NOTES (-40°C to +85°C; VCC = 5V+ 10%) MIN 35 40 TYP MAX 10
PAGE 28
DS2404 NOTES: 1. All voltages are referenced to ground. 2. VIH = 2.0V or VIL = 0.8V with 10ns maximum rise and fall time. 3. VDQH = 2.4V and VDQL = 0.4V, respectively. 4. Load capacitance = 50pF. 5. Measured with outputs open. 6. When battery is applied to VBATO input, VCC and VBATB must be 0V. 7. VBATB, or VBATO = 3.0V; all inputs inactive state. 8. Capacitance on the I/O pin could be 800pF when power is first applied.
PAGE 29
DS2404 20. The reset low time (tRSTL) should be restricted to a maximum of 960ms, to allow interrupt signaling, otherwise, it could mask or conceal interrupt pulses. 21. When the battery is attached, the oscillator powers up in the off state. 22. The optimal sampling point for the master is as close as possible to the end time of the 15ms tRDV period without exceeding tRDV. For the case of a Read-one time slot, this maximizes the amount of time for the pull-up resistor to recover the line to a high level.