Instruction Manual

DS2406
12 of 31
Memory Function Flow Chart (continued) Figure 7
Spare
Vertical
AAh
Read Status
?
TA1(T7:T0), TA2 (T15:T8)
Bus Master TX
Address = (T15:T0)
DS2406 sets Status
F5h
Channel
Access
?
S
Y
Y
NN
Master
TX Reset ?
Y
increments
DS2406
Address
Counter
End of
Status Mem.
?
Master
TX Reset ?
Y
N
N
Y
N
Command, Address, Data
Bus Master RX CRC16 of
Y
N
Bus Master
RX "1"s
Master
TX Reset ?
Control Bytes 1, 2
Bus Master TX Ch.-
from Status Memory
Bus Master RX Data
Presence Pulse
DS2406 TX
Y
From Figure 7
2nd Part
Master
TX Reset ?
Y
N
Master
TX Reset ?
R
Control, Data (1st pass)
Bus Master RX CRC16 of Command,
CRC16 of Data (subsequent passes)
CRC*
Enabled ?
CRC Due * ?
increments
DS2406
CRC Byte
Counter
N
Y
N
Y
Y
N
Master
TX Reset ?
Master
TX Reset ?
from PIOs
Bus Master
RX Data
Channel F/F
Bus Master
TX Data to
CRC Byte Counter
DS2406 clears
Y
N
R/W Toggle
Enabled ?
R/W Mode
DS2406 toggles
N
Bus Master RX
Channel Info Byte
Reset Pulse
Bus Master TX
Presence Pulse
DS2406 TX
* See Channel
Control Byte 1
and Figure 7A
Mode ?
Access
ReadWrite
*
*
Y
N