User Manual

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FEATURES

§ 256-bit Electrically Erasable Programmable

Read Only Memory (EEPROM) plus 64-bit

one-time programmable application register

§ Unique, factory-lasered and tested 64-bit

registration number (8-bit family code + 48-bit

serial number + 8-bit CRC tester) assures

absolute identity because no two parts are alike

§ Built-in multidrop controller ensures

compatibility with other MicroLAN products

§ EEPROM organized as one page of 32 bytes

for random access

§ Reduces control, address, data, and power to a

single data pin

§ Directly connects to a single port pin of a

microprocessor and communicates at up to

16.3kbits per second

§ 8-bit family code specifies DS2430A

communication requirements to reader

§ Presence detector acknowledges when reader

first applies voltage

§ Low cost TO-92 or 6-pin TSOC surface mount

package

§ Reads and writes over a wide voltage range of

2.8V to 6.0V from -40°C to +85°C

ORDERING INFORMATION

DS2430A TO-92 package

DS2430AP 6-pin TSOC package

DS2430A/T&R Tape & Reel version of

DS2430A

DS2430AP/T&R Tape & Reel version of

DS2430AP

DS2430AX Chip Scale Pkg., 10k Tape

& Reel

DS2430AX-S Chip Scale Pkg., 2.5k Tape

& Reel

PIN ASSIGNMENT

PIN DESCRIPTION

TO-92 TSOC

Pin 1 Ground Ground

Pin 2 Data Data

Pin 3 NC NC

Pin 4 –––– NC

Pin 5 –––– NC

Pin 6 ––––

DS2430

256-Bit 1-Wire EEPROM

www.maxim-ic.com

TOP VIEW

3.7mm x 4.0mm x 1.5mm

SIDE VIEW

See Mech.

Drawing Section

TSOC PACKAGE

BOTTOM VIEW

See Mech.

Drawings Section

TO-92

DALLAS

DS2430A

2 3

1 2 3

Summary of content (16 pages)

PAGE 1
DS2430A 256-Bit 1-Wire EEPROM www.maxim-ic.
PAGE 2
DS2430A SILICON LABEL DESCRIPTION The DS2430A 256-bit 1-Wire EEPROM identifies and stores relevant information about the product to which it is associated. This lot or product specific information can be accessed with minimal interface, for example a single port pin of a microcontroller.
PAGE 3
DS2430A DS2430A BLOCK DIAGRAM Figure 1 3 of 16
PAGE 4
DS2430A HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2 64-BIT LASERED ROM Figure 3 8-Bit CRC Code MSB 48-Bit Serial Number LSB MSB 8-Bit Family Code (14H) LSB MSB LSB 1-WIRE CRC GENERATOR Figure 4 8 5 4 Polynomial = X + X + X + 1 4 of 16
PAGE 5
DS2430A MEMORY The memory of the DS2430A consists of three separate sections, called data memory, application register, and status register (Figure 5). The data memory and the application register each has its own intermediate storage area called scratchpad that acts as a buffer when writing to the device. The data memory can be read and written as often as desired. The application register, however, is one-time programmable only.
PAGE 6
DS2430A MEMORY FUNCTION FLOW CHART Figure 6 COPY SCRATCHPAD [55h] After the data stored in the scratchpad has been verified the master may send the Copy Scratchpad command followed by a validation key of A5h to transfer data from the scratchpad to the EEPROM memory. This command will always copy the data of the entire scratchpad.
PAGE 7
DS2430A MEMORY FUNCTION FLOW CHART Figure 6 (cont’d) WRITE APPLICATION REGISTER [99h] This command is essentially the same as the Write Scratchpad command, but it addresses the 64-bit register scratchpad. After issuing the command code, the master must provide a 1-byte address, followed by the data to be written. The DS2430A will automatically increment the address after every byte it received.
PAGE 8
DS2430A MEMORY FUNCTION FLOW CHART Figure 6 (cont’d) READ APPLICATION REGISTER [C3h] This command is used to read the application register or the register scratchpad. As long as the application register is not yet locked, one will receive data from the register scratchpad. After the application register is locked the DS2430A will transmit data from the application register, making the register scratchpad inaccessible for reading.
PAGE 9
DS2430A 1-WIRE BUS SYSTEM The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances, the DS2430A is a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal type and timing).
PAGE 10
DS2430A ROM FUNCTIONS FLOW CHART Figure 8 10 of 16
PAGE 11
DS2430A Transaction Sequence The sequence for accessing the DS2430A via the 1-Wire port is as follows: § Initialization § ROM Function Command § Memory Function Command § Transaction/Data INITIALIZATION All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a Reset Pulse transmitted by the bus master followed by a Presence Pulse(s) transmitted by the slave(s).
PAGE 12
DS2430A After one complete pass, the bus master knows the contents of the ROM in one device. The remaining number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a search ROM, including an actual example. 1-Wire Signaling The DS2430A requires strict protocols to insure data integrity.
PAGE 13
DS2430A READ/WRITE TIMING DIAGRAM Figure 10 Write-1 Time Slot Write-0 Time Slot Read-data Time Slot 13 of 16
PAGE 14
DS2430A MEMORY FUNCTION EXAMPLE Example: Write 2 data bytes to data memory location 0006 and 0007. Read entire data memory.
PAGE 15
DS2430A ABSOLUTE MAXIMUM RATINGS* Voltage on DATA to Ground Operating Temperature Range Storage Temperature Range Soldering Temperature * -0.5V to +7.0V -40°C to +85°C -55°C to +125°C See J-STD-020A Specification This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
PAGE 16
DS2430A NOTES: 1) All voltages are referenced to ground. 2) VPUP = external pullup voltage. 3) Input load is to ground. 4) An additional reset or communication sequence cannot begin until the reset high time has expired. 5) Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is guaranteed to be valid within 1ms of this falling edge. 6) VIH is a function of the external pullup resistor and VPUP.