Instruction Manual

DS26504 T1/E1/J1/64KCC BITS Element
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8. T1 FRAMER/FORMATTER CONTROL REGISTERS......................................... 39
8.1 T1 CONTROL REGISTERS ......................................................................................................... 39
9. E1 FRAMER/FORMATTER CONTROL REGISTERS ........................................ 45
9.1 E1 CONTROL REGISTERS......................................................................................................... 45
9.2 E1 INFORMATION REGISTERS ................................................................................................... 48
10. I/O PIN CONFIGURATION OPTIONS....................................................................... 52
11. T1 SYNCHRONIZATION STATUS MESSAGE ..................................................... 55
11.1 T1 BIT-ORIENTED CODE (BOC) CONTROLLER .......................................................................... 55
11.2 TRANSMIT BOC....................................................................................................................... 55
11.3 RECEIVE BOC......................................................................................................................... 56
12. E1 SYNCHRONIZATION STATUS MESSAGE ..................................................... 64
12.1 SA/SI BIT ACCESS BASED ON CRC4 MULTIFRAME .................................................................... 64
12.1.1 Sa Bit Change of State......................................................................................................................... 65
12.2 ALTERNATE SA/SI BIT ACCESS BASED ON DOUBLE-FRAME ........................................................ 76
13. LINE INTERFACE UNIT (LIU) ...................................................................................... 79
13.1 LIU OPERATION....................................................................................................................... 80
13.2 LIU RECEIVER......................................................................................................................... 80
13.2.1 Receive Level Indicator........................................................................................................................ 80
13.2.2 Receive G.703 Section 10 Synchronization Signal ............................................................................. 81
13.2.3 Monitor Mode ....................................................................................................................................... 81
13.3 LIU TRANSMITTER ................................................................................................................... 81
13.3.1 Transmit Short-Circuit Detector/Limiter................................................................................................ 82
13.3.2 Transmit Open-Circuit Detector ........................................................................................................... 82
13.3.3 Transmit BPV Error Insertion ............................................................................................................... 82
13.3.4 Transmit G.703 Section 10 Synchronization Signal (E1 Mode)........................................................... 82
13.4 MCLK PRE-SCALER ................................................................................................................ 82
13.5 JITTER ATTENUATOR................................................................................................................ 82
13.6 CMI (CODE MARK INVERSION) OPTION..................................................................................... 83
13.7 LIU CONTROL REGISTERS........................................................................................................ 84
13.8 RECOMMENDED CIRCUITS ........................................................................................................ 92
13.9 COMPONENT SPECIFICATIONS .................................................................................................. 94
14. LOOPBACK CONFIGURATION.................................................................................. 98
15. 64KHZ SYNCHRONIZATION INTERFACE ............................................................ 99
15.1 RECEIVE 64KHZ SYNCHRONIZATION INTERFACE OPERATION...................................................... 99
15.2 TRANSMIT 64KHZ SYNCHRONIZATION INTERFACE OPERATION.................................................. 100
16. 6312KHZ SYNCHRONIZATION INTERFACE ..................................................... 101
16.1 RECEIVE 6312KHZ SYNCHRONIZATION INTERFACE OPERATION................................................ 101
16.2 TRANSMIT 6312KHZ SYNCHRONIZATION INTERFACE OPERATION.............................................. 101
17. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT.............. 102
17.1 INSTRUCTION REGISTER......................................................................................................... 106
17.2 TEST REGISTERS................................................................................................................... 107
17.3 BOUNDARY SCAN REGISTER .................................................................................................. 107
17.4 BYPASS REGISTER................................................................................................................. 107