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GENERAL DESCRIPTION

The DS2705 provides the master side of a Secure

Hash Algorithm (SHA) based token authentication

scheme. Hardware-based SHA authentication allows

for security without the added cost and complexity of

a microprocessor-based system. Batteries and other

accessories are authenticated using a single contact

through the Dallas 1-WireÒ interface. Authentication

is performed on demand or automatically, with the

pass/fail status reported on open-drain output pins to

signal the charge system and/or drive LEDs. The

DS2705 stores a predetermined challenge-and-

response pair in nonvolatile (NV) EEPROM. The

DS2705 works in conjunction with Dallas Battery

Management SHA-1 token products, including the

DS2703 and DS2704.

APPLICATIONS

Digital Cameras

Portable DVD and Media Players

Cradle and Accessory Chargers

Cell Phones/Smartphones

PIN CONFIGURATION

FEATURES

§ Initiates Challenge-and-Response

Authentication based on the SHA-1 Algorithm

§ Dallas 1-Wire Master/Slave Interface Operates

at Standard and Overdrive Speeds

§ Input and Output pins for Initiating Challenge

and Reporting Authentication Pass/Fail

§ Programmable Configuration

§ Operates from 2.5V to 5.5V Supply

§ Tiny mMAX Package (Pb-Free)

APPLICATION EXAMPLE

ORDERING INFORMATION

PART TEMP RANGE MARKING PIN-PACKAGE

DS2705U+

-40°C to +85°C

DS2705

mMAX

DS2705U+/T&R

-40°C to +85°C

DS2705 DS2705U+ in Tape-and-Reel

DS2705

SHA-1 Authentication Maste

www.maxim-ic.com

MAX

VDD

MDQ

SDQ

VPP

VSS

HAL

+ Denotes lead-free package.

1-Wire is a registered trademark of Dallas Semiconductor.

Summary of content (18 pages)

PAGE 1
DS2705 SHA-1 Authentication Master www.maxim-ic.com GENERAL DESCRIPTION PIN CONFIGURATION The DS2705 provides the master side of a Secure Hash Algorithm (SHA) based token authentication scheme. Hardware-based SHA authentication allows for security without the added cost and complexity of a microprocessor-based system. Batteries and other accessories are authenticated using a single contact through the Dallas 1-WireÒ interface.
PAGE 2
DS2705: SHA-1 Authentication Master ABSOLUTE MAXIMUM RATINGS Voltage Range on All Pins (except VPP), Relative to VSS Voltage Range on VPP Pin, Relative to VSS Continuous Source Current, MDQ Operating Temperature Range Storage Temperature Range Soldering Temperature -0.3V to +5.5V -0.3V to +18V 20mA -40°C to +85°C -55°C to +125°C See IPC/JEDEC J-STD-020A Specification Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
PAGE 3
DS2705: SHA-1 Authentication Master AC ELECTRICAL CHARACTERISTICS: MASTER 1-Wire INTERFACE (2.5V £ VDD £ 5.5V, TA = -20°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STANDARD BUS TIMING ms Time Slot tMSLOT (Note 10) 90 Recovery Time tMREC (Note 10) Write-0 Low Time tMLOW0 (Note 10) Write-1 Low Time tMLOW1 (Note 10) 1.05 1.5 2.25 ms Read-Data Sample Window tMRDV (Note 10) 4.0 5.5 7.
PAGE 4
DS2705: SHA-1 Authentication Master AC ELECTRICAL CHARACTERISTICS: SLAVE 1-Wire INTERFACE (2.5V £ VDD £ 5.5V, TA = -20°C to +85°C.
PAGE 5
DS2705: SHA-1 Authentication Master AC ELECTRICAL CHARACTERISTICS (2.5V £ VDD £ 5.5V, TA = -20°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX Programming Pulse Width tPPW Programming Pulse Rise Time tPPR (Note 8) 0.5 5 ms Programming Pulse Fall Time tPPF (Note 8) 0.
PAGE 6
DS2705: SHA-1 Authentication Master Figure 1. Block Diagram VDD EEPROM 64-bit Challenge 160-bit MAC 16-bit Configuration Pullup Control CHP = 0 CHAL Control FSM PASS FAIL tCHD + tAAT 1-Wire Master/ Slave MDQ SDQ VSS DETAILED DESCRIPTION The DS2705 orchestrates a challenge/response SHA-1 authentication procedure by accessing a Dallas Battery Management SHA-1 Token product, such as the DS2703 or DS2704. The remote SHA-1 token is accessed with the MDQ pin acting as the 1-Wire bus master.
PAGE 7
DS2705: SHA-1 Authentication Master Figure 2. Typical Application Circuit MDQ Contact Charge Supply BAT+ Contact 330 330 1K 150 DS2705 150 Control Charge Circuit VDD Contacts from Charger to Battery Pack Charge Circuit VSS Charge Circuit Enable VDD MDQ CHAL SDQ FAIL VPP PASS 150 SDQ Testpoint 150 VPP Testpoint VSS 5.6V 5.6V 18V DS2705 Assembly Programming Interface Charge Circuit 0.
PAGE 8
DS2705: SHA-1 Authentication Master Table 1.
PAGE 9
DS2705: SHA-1 Authentication Master AUTHENTICATION SEQUENCE Following the detection of the battery, the DS2705 initiates the authentication sequence. The sequence is executed in whole each time authentication is initiated. See Figure 4. 1. Test for presence with 1-Wire RESET. 2. Issue SKIP ROM (SKIP NET ADDRESS) command. 3. Issue Write Challenge command with 64-bit Challenge data. 4. Issue Compute MAC without ROMID command to SHA-1 token. 5. Provide strong pullup on DQ output. 6. Issue 8 write 0 timeslots.
PAGE 10
DS2705: SHA-1 Authentication Master MASTER PORT (MDQ) FUNCTION COMMANDS MASTER MODE WRITE CHALLENGE COMMAND Write Challenge [0Ch, XXXXXXXXXXXXXXXX]. The master mode Write Challenge command sends the 8-byte (64-bit) challenge to the remote token in preparation for a Compute MAC command. Figure 3.
PAGE 11
DS2705: SHA-1 Authentication Master MAC Comparison After the SHA-1 computation is completed by the remote token, the DS2705 and remote SHA-1 token both contain a MAC result based on the secret key. The results are compared by the DS2705 on a bit by bit basis as the MAC data is read in from the remote token. Note that the secret is never transmitted on the bus and thus cannot be captured by observing bus traffic.
PAGE 12
DS2705: SHA-1 Authentication Master Table 5. Configuration Register FIELD NAME DESCRIPTION DEFAULT Re-Tries Per Authentication Attempt Each re-try includes: OWR, PD, Skip ROM, Write Challenge, Read MAC, Compare MAC, Final OWR/PD CR[1:0] RTA1:0 00 0 Re-try (1 attempt per initiation) 01 1 Re-tries (2 attempts per initiation) 10 3 Re-tries (4 attempts per initiation) 11 7 Re-tries (8 attempts per initiation) 00b PASS output hi-Z until authentication complete.
PAGE 13
DS2705: SHA-1 Authentication Master MEMORY The DS2705 has a 256 byte linear memory space for the EEPROM memory block that stores the challenge, response and configuration parameters. Addresses designated as “Reserved” typically return FFh when read. These bytes should not be written. EEPROM memory consists of non-volatile EEPROM cells overlaying volatile shadow RAM. The Read Data and Write Data protocols allow the 1-Wire interface to directly accesses the shadow RAM.
PAGE 14
DS2705: SHA-1 Authentication Master Figure 6. 1-Wire Bus Interface Circuitry, DS2705 as Slave Vpullup (2.5 to 5.5V) Test System Bus Master 1.5kW - 4.7kW (approx.
PAGE 15
DS2705: SHA-1 Authentication Master Write Data [6Ch, XX]. This command writes data starting at memory address XX. The LSb of the data to be stored at address XX can be written immediately after the MSb of address has been entered. Because the address is automatically incremented after the MSb of each byte is written, the LSb to be stored at address XX + 1 can be written immediately after the MSb to be stored at address XX.
PAGE 16
DS2705: SHA-1 Authentication Master Table 7.
PAGE 17
DS2705: SHA-1 Authentication Master I/O SIGNALING The 1-Wire bus requires strict signaling protocols to ensure data integrity. The four protocols used in 1-Wire communication are as follows: the initialization sequence (reset pulse followed by presence pulse), write 0, write 1, and read data. The 1-Wire bus master initiates all these types of signaling except the presence pulse. The initialization sequence required to begin any 1-Wire communication is shown in Figure 8.
PAGE 18
DS2705: SHA-1 Authentication Master Figure 9.