DEMO KIT AVAILABLE DS31256 Envoy 256-Channel, High-Throughput HDLC Controller www.maxim-ic.com GENERAL DESCRIPTION The DS31256 Envoy is a 256-channel HDLC controller capable of handling up to 64 T1 or E1 data streams or two T3 data streams. Each of the 16 physical ports can handle one, two, or four T1 or E1 data streams. The Envoy is composed of the following blocks: Layer 1, HDLC processing, FIFO, DMA, PCI bus, and local bus.
DS31256 TABLE OF CONTENTS 1. 2. 3. MAIN FEATURES ........................................................................................................................ 6 DETAILED DESCRIPTION........................................................................................................ 7 SIGNAL DESCRIPTION ........................................................................................................... 13 3.1 3.2 3.3 3.4 3.5 3.6 3.7 4. OVERVIEW/SIGNAL LIST............................
DS31256 9.2.3 Free Queue ......................................................................................................................................... 92 9.2.4 Done Queue ........................................................................................................................................ 97 9.2.5 DMA Channel Configuration RAM .................................................................................................. 102 9.3 TRANSMIT SIDE................................
DS31256 LIST OF FIGURES Figure 2-1. Block Diagram ....................................................................................................................................... 10 Figure 5-1. Status Register Block Diagram for SM and SV54................................................................................. 36 Figure 6-1. Layer 1 Block Diagram.......................................................................................................................... 46 Figure 6-2.
DS31256 Figure 11-11. 16-Bit Read Cycle............................................................................................................................ 161 Figure 11-12. 8-Bit Write Cycle............................................................................................................................. 162 Figure 12-1. Block Diagram ................................................................................................................................... 163 Figure 12-2.
DS31256 1. MAIN FEATURES § § § § Layer 1 Can simultaneously support up to 64 T1 or E1 data streams, or two T3 data streams 16 independent physical ports capable of speeds up to 10MHz; three ports are also capable of speeds up to 52MHz Each port can be independently configured for either channelized or unchannelized operation Each physical channelized port can handle one, two, or four T1 or E1 data streams Supports N x 64kbps and N x 56kbps On-board V.
DS31256 Table 1-A. Data Sheet Definitions The following terms are used throughout this data sheet. Note: The DS31256’s ports are numbered 0 to 39; the HDLC channels are numbered 1 to 40. HDLC Channel 1 is always associated with Port 0, HDLC Channel 2 with Port 1, and so on. TERM BERT Descriptor Dword DMA FIFO HDLC Host n/a V.54 DEFINITION Bit Error-Rate Tester A message passed back and forth between the DMA and the host Double word; a 32-bit data entity Direct Memory Access First In, First Out.
DS31256 In the receive path, the following process occurs. The HDLC Engines collect the incoming data into 32-bit dwords and then signal the FIFO that the engine has data to transfer to the FIFO. The 16 ports are priority decoded (Port 0 gets the highest priority) for the transfer of data from the HDLC Engines to the FIFO Block.
DS31256 When the DMA begins burst writing data into the FIFO, it will try to completely fill the FIFO with HDLC packet data even if it that means writing multiple packets. Once the FIFO detects that the DMA has filled it to beyond the Low Water Mark (or an EOF is reached), the FIFO will begin transferring 32-bit dwords to the HDLC Engine. One of the unique attributes of the DS31256 is the structure of the DMA.
DS31256 Figure 2-1. Block Diagram RECEIVE DIRECTION INTERNAL CONTROL BUS BERT (SECT. 6) JTRST JTDI JTMS JTCLK JTDO PCI BLOCK (SECT. 10) PCLK PRST PAD[31:0] PCBE[3:0] PPAR PFRAME PIRDY PTRDY PSTOP PIDSEL PDEVSEL PREQ PGNT PPERR PSERR PXAS PXDS PXBLAST DS31256 JTAG TEST ACCESS LOCAL BUS BLOCK (SECT. 11) RC39 RD39 TC39 TD39 DMA BLOCK (SECT. 9) RC2 RD2 TC2 TD2 FIFO BLOCK (SECT. 8) RC1 RD1 TC1 TD1 LAYER 1 BLOCK (SECT. 6) RC0 RD0 TC0 TD0 40-BIT SYNCHRONOUS HDLC CONTROLLERS (SECT.
DS31256 Restrictions In creating the overall system architecture, the user must balance the port, throughput, and HDLC channel restrictions of the DS31256. Table 2-A lists all of the upper-bound maximum restrictions. Table 2-A.
DS31256 Table 2-B. Initialization Steps INITIALIZATION STEP COMMENTS 1) Initialize the PCI configuration registers 2) Initialize all indirect registers 3) Configure the device for operation 4) Enable the HDLC channels 5) Load the DMA descriptors 6) Enable the DMAs 7) Enable DMA for each HDLC channel Achieved by asserting the PIDSEL signal. It is recommended that all of the indirect registers be set to 0000h (Table 2-C).
DS31256 3. SIGNAL DESCRIPTION 3.1 Overview/Signal List This section describes the input and output signals on the DS31256. Signal names follow a convention that is shown in the Signal Naming Convention table below. Table 3-A lists all of the signals, their signal type, description, and pin location. Signal Naming Convention FIRST LETTER R T L J P SIGNAL CATEGORY Receive Serial Port Transmit Serial Port Local Bus JTAG Test Port PCI Bus SECTION 3.2 3.2 3.3 3.4 3.5 Table 3-A.
DS31256 PIN NAME TYPE FUNCTION T20 R18 P17 R19 R20 P18 P19 P20 N18 N19 N20 M17 L18 L19 M18 K20 M19 H18 K18 H19 A2, A8, A11, A19, B2, B18, J18, J19, K1, K2, K3, L1–L3, M20, U14, W2, W9, Y1, Y19 V17 U16 Y18 W17 V16 Y17 W16 V15 W15 V14 Y15 W14 Y14 V13 W13 Y13 V9 U9 Y8 W8 V8 Y7 W7 V7 U7 V6 Y5 LD4 LD5 LD6 LD7 LD8 LD9 LD10 LD11 LD12 LD13 LD14 LD15 LHLDA(LBG) LHOLD(LBR) LIM LINT LMS LRD (LDS) LRDY LWR (LR/W) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O I I/O I I/O I I/O Local Bus Data Bit 4 Local Bus
DS31256 PIN NAME TYPE W5 V5 Y4 Y3 U5 Y16 V12 Y9 W6 PAD27 PAD28 PAD29 PAD30 PAD31 PCBE0 PCBE1 PCBE2 PCBE3 I/O I/O I/O I/O I/O I/O I/O I/O I/O Y2 PCLK I Y11 W10 W4 Y6 W18 V10 W12 V11 V4 W3 Y12 W11 Y10 V18 Y20 W19 B1 D1 F2 H2 M1 P1 P4 V1 B17 B16 C14 D12 A10 B8 B6 C5 D2 E2 G3 J4 M3 R1 T2 U3 D16 PDEVSEL PFRAME PGNT PIDSEL PINT PIRDY PPAR PPERR PREQ PRST PSERR PSTOP PTRDY PXAS PXBLAST PXDS RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RC8 RC9 RC10 RC11 RC12 RC13 RC14 RC15 RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RD8 I/O I/O
DS31256 PIN NAME TYPE C15 A14 B12 C10 A7 D7 A3 C2 E3 F1 H1 M2 P2 R3 T4 C17 A16 B14 C12 B10 C8 A5 B4 D3 E1 G2 J3 N1 P3 U1 V2 A18 D14 C13 A12 A9 B7 C6 D5 C1 G4 H3 J1 N3 T1 U2 V3 C16 A15 A13 C11 C9 RD9 RD10 RD11 RD12 RD13 RD14 RD15 RS0 RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12 RS13 RS14 RS15 TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 TC8 TC9 TC10 TC11 TC12 TC13 TC14 TC15 TD0 TD1 TD2 TD3 TD4 TD5 TD6 TD7 TD8 TD9 TD10 TD11 TD12 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I O O O
DS31256 PIN NAME TYPE FUNCTION C7 A4 B3 C3 E4 F3 G1 J2 N2 R2 T3 W1 A17 B15 B13 B11 B9 A6 B5 C4 D6, D10, D11, D15, F4, F17, K4, K17, L4, L17, R4, R17, U6, U10, U11, U15 A1, D4, D8, D9, D13, D17, H4, H17, J17, M4, N4, N17, U4, U8, U13, U13, U17 TD13 TD14 TD15 TEST TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 O O O I I I I I I I I I I I I I I I I I Transmit Serial Data for Port 13 Transmit Serial Data for Port 14 Transmit Serial Data for Port 15 Test.
DS31256 3.2 Serial Port Interface Signal Description Signal Name: RC0 to RC15 Signal Description: Receive Serial Clock Signal Type: Input Data can be clocked into the device either on rising edges (normal clock mode) or falling edges (inverted clock mode) of RC. This is programmable on a per port basis. RC0–RC2 can operate at speeds up to 52MHz. RC3–RC15 can operate at speeds up to 10MHz. Unused signals should be wired low.
DS31256 Signal Name: TS0 to TS15 Signal Description: Transmit Serial Data Synchronization Pulse Signal Type: Input This is a one-TC clock-wide synchronization pulse that can be applied to the Envoy to force byte/frame alignment. The applied sync signal pulse can be either active high (normal sync mode) or active low (inverted sync mode). The TS signal can be sampled either on the falling edge or on rising edge of TC (Table 3-C).
DS31256 information about the device through these signals. Only the 16-bit bus width is allowed (i.e., byte addressing is not available). Signal Name: LA0 to LA19 Signal Description: Local Bus Nonmultiplexed Address Bus Signal Type: Input/Output (three-state capable) In the PCI bridge mode (LMS = 0), these signals are outputs that are asserted on the rising edge of LCLK to indicate which address to be written to or read from.
DS31256 Signal Name: LHLDA (LBG) Signal Description: Local Bus Hold Acknowledge (Local Bus Grant) (PCI Bridge Mode Only) Signal Type: Input This input signal is sampled on the rising edge of LCLK to determine when the device has been granted access to the bus. In Intel mode (LIM = 0), this is an active-high signal; in Motorola mode (LIM = 1) this is an active-low signal. This signal is ignored and should be connected high when the local bus is in configuration mode (LMS = 1).
DS31256 Signal Name: JTDI Signal Description: JTAG IEEE 1149.1 Test Serial-Data Input Signal Type: Input (with internal 10kΩ pullup) Test instructions and data are clocked into this signal on the rising edge of JTCLK. If unused, this signal should be pulled high. This signal has an internal pullup. Signal Name: JTDO Signal Description: JTAG IEEE 1149.1 Test Serial-Data Output Signal Type: Output Test instructions are clocked out of this signal on the falling edge of JTCLK.
DS31256 Signal Name: PCBE0/PCBE1/PCBE2/PCBE3 Signal Description: PCI Bus Command and Byte Enable Signal Type: Input/Output (three-state capable) Bus command and byte enables are multiplexed onto the same PCI signals. During an address phase, these signals define the bus command. During the data phase, these signals are used as bus enables. During data phases, PCBE0 refers to the PAD[7:0] and PCBE3 refers to PAD[31:24].
DS31256 signal is an input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, PSTOP is three-stated. Signal Name: PIDSEL Signal Description: PCI Initialization Device Select Signal Type: Input This input signal is used as a chip select during configuration read and write transactions. This signal is disabled when the local bus is set in configuration mode (LMS = 1).
DS31256 3.6 PCI Extension Signals These signals are not part of the normal PCI bus signal set. There are additional signals that are asserted when the Envoy is an initiator on the PCI bus to help users interpret the normal PCI bus signal set and connect them to a non-PCI environment like an Intel i960-type bus.
DS31256 4. MEMORY MAP 4.1 Introduction All addresses within the memory map are on dword boundaries, even though all internal device configuration registers are only one word (16 bits) wide. The memory map consumes an address range of 4kb (12 bits). When the PCI bus is the host (i.e.
DS31256 4.
DS31256 4.
DS31256 4.6 HDLC Registers (4xx) OFFSET/ ADDRESS 0400 0404 0410 0480 0484 NAME RHCDIS RHCD RHPL THCDIS THCD REGISTER Receive HDLC Channel Definition Indirect Select Receive HDLC Channel Definition Receive HDLC maximum Packet Length. One per device. Transmit HDLC Channel Definition Indirect Select Transmit HDLC Channel Definition SECTION 7.2 7.2 7.2 7.2 7.2 4.
DS31256 4.
DS31256 4.11 PCI Configuration Registers for Function 0 (PIDSEL/Axx) OFFSET/ ADDRESS 0x000/0A00 0x004/0A04 0x008/0A08 0x00C/0A0C 0x010/0A10 0x03C/0A3C NAME PVID0 PCMD0 PRCC0 PLTH0 PDCM PINTL0 REGISTER PCI Vendor ID/Device ID 0 PCI Command Status 0 PCI Revision ID/Class Code 0 PCI Cache Line Size/Latency Timer/Header Type 0 PCI Device Configuration Memory Base Address PCI Interrupt Line and Pin /Min Grant/Max Latency 0 SECTION 10.2 10.2 10.2 10.2 10.2 10.2 4.
DS31256 5. GENERAL DEVICE CONFIGURATION AND STATUS/INTERRUPT 5.1 Master Reset and ID Register Description The master reset and ID (MRID) register can be used to globally reset the device. When the RST bit is set to 1, all of the internal registers (except the PCI configuration registers) are placed into their default state, which is 0000h. The host must set the RST bit back to 0 before the device can be programmed for normal operation.
DS31256 Bit 0/Receive DMA Enable (RDE). This bit is used to enable the receive DMA. When it is set to 0, the receive DMA does not pass any data from the receive FIFO to the PCI bus, even if one or more HDLC channels is enabled. On device initialization, the host should fully configure the receive DMA before enabling it through this bit. 0 = receive DMA is disabled 1 = receive DMA is enabled Bit 1/Receive DMA Throttle Select Bit 0 (RDT0); Bit 2/Receive DMA Throttle Select Bit 1 (RDT1).
DS31256 Bits 7 to 11/BERT Port Select Bits 0 to 4 (BPS0 to BPS4). These bits select which port has the dedicated resources of the BERT.
DS31256 interrupt enable for the receive COFA (IERC) and interrupt enable for the transmit COFA (IETC) control bits in the RP[n]CR and TP[n]CR registers, respectively. The BERT receiver reports three events: a change in the receive synchronizer status, a bit error being detected, and if either the bit counter or the error counter overflows. Each of these events can be masked within the BERT function through the BERT control register (BERTC0).
DS31256 Figure 5-1.
DS31256 5.3.2 Status and Interrupt Register Description Register Name: Register Description: Register Address: SM Status Master Register 0020h Bit # Name Default 7 n/a 0 6 n/a 0 5 n/a 0 4 PPERR 0 3 PSERR 0 2 SBERT 0 1 STCOFA 0 0 SRCOFA 0 Bit # Name Default 15 LBINT 0 14 LBE 0 13 n/a 0 12 n/a 0 11 n/a 0 10 n/a 0 9 n/a 0 8 n/a 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/Status Bit for Change-of-Frame Alignment (SRCOFA).
DS31256 Bit 14/Status Bit for Local Bus Error (LBE). This status bit applies to the local bus when it is operated in PCI bridge mode. It is set to 1 when the local bus LRDY signal is not detected within nine LCLK periods. This indicates to the host that an aborted local bus access has occurred.
DS31256 Register Name: Register Description: Register Address: SV54 Status Register for the Receive V.54 Detector 0030h Bit # Name Default 7 SLBP7 0 6 SLBP6 0 5 SLBP5 0 4 SLBP4 0 3 SLBP3 0 2 SLBP2 0 1 SLBP1 0 0 SLBP0 0 Bit # Name Default 15 SLBP15 0 14 SLBP14 0 13 SLBP13 0 12 SLBP12 0 11 SLBP11 0 10 SLBP10 0 9 SLBP9 0 8 SLBP8 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 15/Status Bits for Change of State in Receive V.
DS31256 Register Name: Register Description: Register Address: SDMA Status Register for DMA 0028h Bit # Name Default 7 RLBRE 0 6 RLBR 0 5 ROVFL 0 4 RLENC 0 3 RABRT 0 2 RCRCE 0 1 n/a 0 0 n/a 0 Bit # Name Default 15 TDQWE 0 14 TDQW 0 13 TPQR 0 12 TUDFL 0 11 RDQWE 0 10 RDQW 0 9 RSBRE 0 8 RSBR 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 2/Status Bit for Receive HDLC CRC Error (RCRCE).
DS31256 Bit 8/Status Bit for Receive DMA Small Buffer Read (RSBR). This status bit is set to 1 each time the receive DMA completes a single read or a burst read of the small buffer free queue. The RSBR bit is cleared when read and is not set again, until another read of the small buffer free queue has occurred.
DS31256 Register Name: Register Description: Register Address: ISDMA Interrupt Mask Register for SDMA 002Ch Bit # Name Default 7 RLBRE 0 6 RLBR 0 5 ROVFL 0 4 RLENC 0 3 RABRT 0 2 RCRCE 0 1 n/a 0 0 n/a 0 Bit # Name Default 15 TDQWE 0 14 TDQW 0 13 TPQR 0 12 TUDFL 0 11 RDQWE 0 10 RDQW 0 9 RSBRE 0 8 RSBR 0 Note: Bits that are underlined are read-only; all other bits are read-write.
DS31256 Bit 13/Status Bit for Transmit DMA Pending-Queue Read (TPQR) 0 = interrupt masked 1 = interrupt unmasked Bit 14/Status Bit for Transmit DMA Done-Queue Write (TDQW) 0 = interrupt masked 1 = interrupt unmasked Bit 15/Status Bit for Transmit DMA Done-Queue Write Error (TDQWE) 0 = interrupt masked 1 = interrupt unmasked 5.
DS31256 6. LAYER 1 6.1 General Description Figure 6-1 shows the Layer 1 block. Each of the DS31256’s 16 Layer 1 ports can be configured to support either a channelized application or an unchannelized application. Users can mix the applications on the ports as needed. Some or all of the ports can be channelized, while the others can be configured as unchannelized.
DS31256 The DS31256 has a set of three registers per DS0 channel for each port that determine how each DS0 channel is configured. These three registers are defined in Section 6.3. If the fast (52Mbps) HDLC engine is enabled on port 0, then HDLC channel 1 is assigned to it. Likewise, HDLC channel 2 is assigned to the fast HDLC engine on port 1 if it is enabled, and HDLC channel 2 is assigned to the fast HDLC engine on port 2 if it is enabled. The Layer 1 block also contains a V.54 detector.
DS31256 Figure 6-1. Layer 1 Block Diagram 1 of 16 RC RS RD Local LoopBack (LLB) V.54 Detector Invert Clock / Data / Sync LLB TC TS TD Force All Ones Port 0&1 Only OverSample with PCLK Receive UNLB Invert Clock / Data / Sync BERT/ Fast HDLC Mux OverSample with PCLK Layer One State Machine PORT RAM (see Sec. 5.
DS31256 Figure 6-2.
DS31256 6.2 Port Register Descriptions Receive Side Control Bits (one each for all 16 ports) Register Name: Register Description: Register Address: RP[n]CR, where n = 0 to 15 for each port Receive Port [n] Control Register See the Register Map in Section 4.
DS31256 Bit 8/Port 0 High-Speed Mode (RP0 (1, 2) HS). If enabled, the port 0 (1, or 2) Layer 1 state machine logic is defeated, and RC0 (1, 2) and RD0 (1, 2) are routed to some dedicated high-speed HDLC processing logic. Only present in RP0CR, RP1CR and RP2CR. Bit 8 is not assigned in ports 3 through 15. 0 = disabled 1 = enabled Bit 9/Unchannelized Enable (RUEN). When enabled, this bit forces the port to operate in an unchannelized fashion. When disabled, the port operates in a channelized mode.
DS31256 Bit 0/Invert Clock Enable (TICE) 0 = do not invert clock (normal mode) 1 = invert clock (inverted mode) Bit 1/Invert Data Enable (TIDE) 0 = do not invert data (normal mode) 1 = invert data (inverted mode) Bit 2/Invert Sync Enable (TISE) 0 = do not invert sync (normal mode) 1 = invert sync pulse (inverted mode) Bit 3/Force Data All Ones (TFDA1) 0 = force all data at TD to be 1 1 = allow data to be transmitted normally Bit 4/Sync Delay Bit 0 (TSD0); Bit 5/Sync Delay Bit 1 (TSD1).
DS31256 Bit 14/Interrupt Enable for TCOFA (IETC) 0 = interrupt masked 1 = interrupt enabled Bit 15/COFA Status Bit (TCOFA). This latched read-only status bit is set if a COFA is detected. A COFA is detected by sensing that a sync pulse has occurred during a clock period that was not the first bit of the 193/256/512/1024-bit frame. This bit is reset when read and is not set again until another COFA has occurred. 6.
DS31256 Register Name: Register Description: Register Address: CP[n]RDIS, where n = 0 to 15 for each port Channelized Port [n] Register Data Indirect Select See the Register Map in Section 4, Bit # Name Default 7 n/a 0 6 CHID6 0 5 CHID5 0 4 CHID4 0 3 CHID3 0 2 CHID2 0 1 CHID1 0 0 CHID0 0 Bit # Name Default 15 IAB 0 14 IARW 0 13 n/a 0 12 n/a 0 11 n/a 0 10 n/a 0 9 CPRS1 0 8 CPRS0 0 Note: Bits that are underlined are read-only; all other bits are read-write.
DS31256 Register Name: Register Description: Register Address: CP[n]RD, where n = 0 to 15 for each port Channelized Port [n] Register Data See the Register Map in Section 4. Bit # Name Default 7 CHD7 0 6 CHD6 0 5 CHD5 0 4 CHD4 0 3 CHD3 0 2 CHD2 0 1 CHD1 0 0 CHD0 0 Bit # Name Default 15 CHD15 0 14 CHD14 0 13 CHD13 0 12 CHD12 0 11 CHD11 0 10 CHD10 0 9 CHD9 0 8 CHD8 0 Note: Bits that are underlined are read-only; all other bits are read-write.
DS31256 Bits 8 to 15/Transmit DS0 Data (TDATA). This register holds the most current DS0 byte transmitted. It is used by the receive side Layer 1 state machine when channelized local loopback (CLLB) is enabled.
DS31256 Bit 15/Receive DS0 Channel Enable (RCHEN). This bit must be set for each active DS0 channel in a channelized application. In a channelized application, although a DS0 channel is deactivated, the channel can still be set up to route data to the V.54 detector and/or the BERT block. In addition, although a DS0 channel is active, the loopback function (CLLB = 1) overrides this activation and routes transmit data back to the HDLC controller instead of the data coming in through the RD pin.
DS31256 Bit 14/Route Data from BERT (TBERT). Setting this bit routes DS0 data to the TD pin from the BERT block instead of from the HDLC controller. If the DS0 channel has been configured for 56kbps operation (T56 = 1), the LSB of each DS0 channel is not routed from the BERT block but instead is forced to 1. In order for the data to make it from the BERT block, the host must also configure the BERT for the proper port through the master control register (Section 5). This bit overrides TFAO and TCHEN.
DS31256 Table 6-B. Receive V.54 Search Routine STEP DIRECTION 1 Set up the channel search 2 Toggle VRST 3 Wait for SLBP 4 Read VTO and VLB FUNCTION By configuring the RV54 bit in the R[n]CFG[j] register, the host determines in which DS0 channels the V.54 search is to take place. If this search sequence does not detect the V.54 pattern, the host can pick some new DS0 channels and try again.
DS31256 Figure 6-5. Receive V.54 Host Algorithm ALGORITHM Set Up the DS0 Channel Search Toggle VRST Wait for SLBP = 1 Yes VTO = 1? NOTES DS0 channels can be configured to search for the V.54 loop pattern via the Receive Layer 1 Configuration Register (see Section 5.3) VRST is a control bit that is in the Receive Port Control Register (see Section 5.2) SLBP is a status bit that is reported in the SV54 register (see Section 4.
DS31256 Figure 6-6. Receive V.54 State Machine VRST = 1 VLB = 0 VTO = 0 SLBP = 0 CLK V.54 State Machine Data VRST (in RP[n]CR) Time Out (VTO) Loopback (VLB); both in RP[n]CR Change of State in Status (SLBP); in SV54 SYSCLK Search for Loop Up Pattern for 32 VCLKs Sysclk is used only to time a 4 second timer. It is run into a 2E27 counter which provides a 4.03 second time out with a 33MHz clock and a 5.
DS31256 6.5 BERT The BERT block is capable of generating and detecting the following patterns: § § § The pseudorandom patterns 2E7, 2E11, 2E15, and QRSS A repetitive pattern from 1 to 32 bits in length Alternating (16-bit) words that flip every 1 to 256 words The BERT receiver has a 32-bit bit counter and a 24-bit error counter. It can generate interrupts upon detecting a bit error, a change in synchronization, or if an overflow occurs in the bit and error counters.
DS31256 6.6 BERT Register Description Figure 6-8.
DS31256 Register Name: Register Description: Register Address: BERTC0 BERT Control Register 0 0500h Bit # Name Default 7 n/a 0 6 TINV 0 5 RINV 0 4 PS2 0 3 PS1 0 2 PS0 0 1 LC 0 0 RESYNC 0 Bit # Name Default 15 IESYNC 0 14 IEBED 0 13 IEOF 0 12 n/a 0 11 RPL3 0 10 RPL2 0 9 RPL1 0 8 RPL0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/Force Resynchronization (RESYNC).
DS31256 Repetitive Pattern Length Map Length 17 Bits 21 Bits 25 Bits 29 Bits Code 0000 0100 1000 1100 Length 18 Bits 22 Bits 26 Bits 30 Bits Code 0001 0101 1001 1101 Length 19 Bits 23 Bits 27 Bits 31 Bits Code 0010 0110 1010 1101 Length 20 Bits 24 Bits 28 Bits 32 Bits Code 0011 0111 1011 1111 Bit 13/Interrupt Enable for Counter Overflow (IEOF). Allows the receive BERT to cause an interrupt if either the bit counter or the error counter overflows.
DS31256 EIB2 0 0 0 0 1 1 1 1 EIB1 0 0 1 1 0 0 1 1 EIB0 0 1 0 1 0 1 0 1 Error Rate Inserted No errors automatically inserted 10E-1 10E-2 10E-3 10E-4 10E-5 10E-6 10E-7 Bits 8 to 15/Alternating Word Count Rate. When the BERT is programmed in the alternating word mode, the words repeat for the count loaded into this register, then flip to the other word and again repeat for the number of times loaded into this register. The valid count range is from 05h to FFh.
DS31256 Register Name: Register Description: Register Address: BERTBC0 BERT 32-Bit Bit Counter (lower word) 0510h Register Name: Register Description: Register Address: BERTBC1 BERT 32-Bit Bit Counter (upper word) 0514h BERTBC0: BERT Bit Counter 0 (lower word) Bit # 7 6 5 4 3 2 Name BERT 32-Bit Bit Counter (lower byte) Default 0 0 0 0 0 0 Bit # Name Default 15 14 13 0 0 0 12 11 BERT 32-Bit Bit Counter 0 0 1 0 0 0 10 9 8 0 0 0 18 17 16 BERTBC1: BERT Bit Counter 0 (upper word) Bit #
DS31256 Bit 1/BERT Error Counter Overflow (BECO). A latched bit that is set when the 24-bit BERT error counter (BEC) overflows. Cleared when read and is not set again until another overflow occurs. Bit 2/BERT Bit Counter Overflow (BBCO). A latched bit that is set when the 32-bit BERT bit counter (BBC) overflows. Cleared when read and is not set again until another overflow occurs. Bit 3/Bit Error Detected (BED). A latched bit that is set when a bit error is detected.
DS31256 7. HDLC 7.1 General Description The DS31256 contains two different types of HDLC controllers. Each port has a slow HDLC engine (type #1) associated with it that can operate in either a channelized mode up to 8.192Mbps or an unchannelized mode at rates up to 10Mbps. Ports 0 and 1 also have an additional fast HDLC engine (type #2) that can operate in only an unchannelized fashion up to 52Mbps. Through the Layer 1 registers (Section 6.
DS31256 Table 7-B. Receive HDLC Functions FUNCTION DESCRIPTION Zero Destuff This operation is disabled if the channel is set to transparent mode. Flag Detection and Byte Alignment Okay to have two packets separated by only one flag or by two flags sharing a 0. This operation is disabled if the channel is set to transparent mode. The minimum check is for 4 Bytes with CRC-16 and 6 Bytes with CRC-32 (packets with less than the minimum lengths are not passed to the PCI bus).
DS31256 7.2 HDLC Register Description Register Name: Register Description: Register Address: RHCDIS Receive HDLC Channel Definition Indirect Select 0400h Bit # Name Default 7 HCID7 0 6 HCID6 0 5 HCID5 0 4 HCID4 0 3 HCID3 0 2 HCID2 0 1 HCID1 0 0 HCID0 0 Bit # Name Default 15 IAB 0 14 IARW 0 13 n/a 0 12 n/a 0 11 n/a 0 10 n/a 0 9 n/a 0 8 n/a 0 Note: Bits that are underlined are read-only; all other bits are read-write.
DS31256 zero destuffing, and abort detection, octet length checking, or FCS checking. When in transparent mode, the device must not be configured to write done-queue descriptors only at the end of a packet, if it is desired that donequeue descriptors be written; there is not an end of packet on the receive side in transparent mode by definition. Please note that an end of packet does not occur on the receive side while in transparent mode.
DS31256 Register Name: Register Description: Register Address: RHPL Receive HDLC Maximum Packet Length 0410h Bit # Name Default 7 RHPL7 0 6 RHPL6 0 5 RHPL5 0 4 RHPL4 0 3 RHPL3 0 2 RHPL2 0 1 RHPL1 0 0 RHPL0 0 Bit # Name Default 15 RHPL15 0 14 RHPL14 0 13 RHPL13 0 12 RHPL12 0 11 RHPL11 0 10 RHPL10 0 9 RHPL9 0 8 RHPL8 0 Note: Bits that are underlined are read-only; all other bits are read-write. This is a globe control; only one per device, not one for each individual HDLC channel.
DS31256 Register Name: Register Description: Register Address: THCD Transmit HDLC Channel Definition 0484h Bit # Name Default 7 TABTE 6 TCFCS 5 TBF 4 TID 3 TCRC1 2 TCRC0 1 TIFS 0 TTRANS Bit # Name Default 15 n/a 14 n/a 13 n/a 12 TZSD 11 TFG3 10 TFG2 9 TFG1 8 TFG0 Note: Bits that are underlined are read only, all other bits are read-write. Bit 0/Transmit Transparent Enable (TTRANS).
DS31256 Bits 8 to 11/Transmit Flag Generation Bits 0 to 3 (TFG0/TFG1/TFG2/TFG3). These four bits determine how many flags and interfill bytes are sent between consecutive packets.
DS31256 8. FIFO 8.1 General Description and Example The DS31256 Envoy contains one 16kB FIFO for the receive path and another 16kB FIFO for the transmit path. Both of these FIFOs are organized into blocks. Since a block is defined as 4 dwords (16 Bytes), each FIFO is made up of 1024 blocks. Figure 8-1 shows an FIFO example. The FIFO contains a state machine that is constantly polling the 16 ports to determine if any data is ready for transfer to/from the FIFO from/to the HDLC engines.
DS31256 The host must set the watermarks for the receive and transmit paths. The receive path has a high watermark and the transmit path has a low watermark. Figure 8-1.
DS31256 8.1.1 Receive High Watermark The high watermark tells the device how many blocks the HDLC engines should write into the receive FIFO before the DMA sends data to the PCI bus, or rather, how full the FIFO should get before it should be emptied by the DMA. When the DMA begins reading the data from the FIFO, it reads all available data and tries to completely empty the FIFO even if one or more EOFs (end of frames) are detected.
DS31256 Bit 14/Indirect Access Read/Write (IARW). When the host wishes to write data to set the internal receive starting block pointer, the host should write this bit to 0. This causes the device to take data that is currently presetn in the RFSBP register and write it to the channel location indicated by the HCID bits. When the device completes the write, the IAB is set to 0. Note: The RFSBPIS is write-only memory.
DS31256 Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal receive block pointer RAM, the host should write this bit to 1. This causes the device to begin obtaining the data from the block location indicated by the BLKID bits. During the read access, the IAB bit is set to 1. Once the data is ready to be read from the RFBP register, the IAB bit is set to 0.
DS31256 Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal receive highwatermark RAM, this bit should be written to 1 by the host. This causes the device to begin obtaining the data from the channel location indicated by the HCID bits. During the read access, the IAB bit is set to 1. Once the data is ready to be read from the RFHWM register, the IAB bit is set to 0.
DS31256 Bits 0 to 7/HDLC Channel ID (HCID0 to HCID7) 00000000 (00h) = HDLC channel number 1 11111111 (FFh) = HDLC channel number 256 Bit 14/Indirect Access Read/Write (IARW). When the host wishes to write data to the internal transmit starting block pointer RAM, this bit should be written to 1 by the host. This causes the device to take the data that is in the TFSBP register and write it to the channel location indicated by the HCID bits. When the device has completed the write, the IAB is set to 0.
DS31256 Bits 0 to 9/Block ID (BLKID0 to BLKID9) 00000000000 (000h) = block number 0 01111111111 (1FFh) = block number 511 1111111111 (3FFh) = block number 1023 Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal transmit block pointer RAM, this bit should be written to 1 by the host. This causes the device to begin obtaining the data from the block location indicated by the BLKID bits. During the read access, the IAB bit is set to 1.
DS31256 Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal transmit lowwatermark RAM, this bit should be written to 1 by the host. This causes the device to begin obtaining the data from the channel location indicated by the HCID bits. During the read access, the IAB bit is set to 1. Once the data is ready to be read from the TFLWM register, the IAB bit is set to 0.
DS31256 9. DMA 9.1 Introduction The DMA block (Figure 2-1) handles the transfer of packet data from the FIFO block to the PCI block and vice versa. Throughout this section, the terms host and descriptor are used. Host is defined as the CPU or intelligent controller that sits on the PCI bus and instructs the device about how to handle the incoming and outgoing packet data.
DS31256 Table 9-A.
DS31256 9.2 Receive Side 9.2.1 Overview The receive DMA uses a scatter-gather technique to write packet data into main memory. The host keeps track of and decides where the DMA should place the incoming packet data. There are a set of descriptors that get handed back and forth between the DMA and the host. Through these descriptors the host can inform the DMA where to place the packet data and the DMA can tell the host when the data is ready to be processed.
DS31256 On an HDLC-channel basis in the receive DMA configuration RAM, the host instructs the DMA how to use the large and small buffers for the incoming packet data on that particular HDLC channel. The host has three options: (1) only use large buffers, (2) only use small buffers, or (3) first fill a small buffer, then, if the incoming packet requires more buffer space, use one or more large buffers for the remainder of the packet.
DS31256 Host Actions The host typically handles the receive DMA as follows: 1) The host is always trying to make free data buffer space available and therefore tries to fill the freequeue descriptor. 2) The host either polls, or is interrupted, when some incoming packet data is ready for processing. 3) The host then reads the done-queue descriptor circular queue to find out which channel has data available, what the status is, and where the receive packet descriptor is located.
DS31256 Figure 9-1. Receive DMA Operation Free Queue Descriptors (circular queue) 00h Free Data Buffer Address unused 08h Free Data Buffer Address unused 10h Free Desc. Ptr. Free Desc. Ptr. Free Data Buffer Address unused Free Desc. Ptr.
DS31256 Figure 9-2.
DS31256 9.2.2 Packet Descriptors A contiguous section of up to 65,536 quad dwords that make up the receive packet descriptors resides in main memory. The receive packet descriptors are aligned on a quad dword basis and can be placed anywhere in the 32-bit address space through the receive descriptor base address (Table 9-C). A data buffer is associated with each descriptor. The data buffer can be up to 8188 Bytes long and must be a contiguous section of main memory.
DS31256 Figure 9-4. Receive Packet Descriptors dword 0 Data Buffer Address (32) dword 1 BUFS (3) dword 2 Byte Count (13) Next Descriptor Pointer (16) Timestamp (24) 00b HDLC CH#(8) dword 3 unused (32) Note: The organization of the receive descriptor is not affected by the enabling of Big Endian. dword 0; Bits 0 to 31/Data Buffer Address. Direct 32-bit starting address of the data buffer that is associated with this receives descriptor. dword 1; Bits 0 to 15/Next Descriptor Pointer.
DS31256 9.2.3 Free Queue The host writes the 32-bit addresses of the available (free) data buffers and their associated packet descriptors to the receive free queue. The descriptor space is indicated through a 16-bit pointer, which the DMA uses along with the receive packet descriptor base address to find the exact 32-bit address of the associated receive packet descriptor. Figure 9-5.
DS31256 Empty Case The receive free queue is considered empty when the read and write pointers are identical. Receive Free-Queue Empty State read pointer > empty descriptor empty descriptor empty descriptor empty descriptor empty descriptor empty descriptor empty descriptor < write pointer Full Case The receive free queue is considered full when the read pointer is ahead of the write pointer by one descriptor. Therefore, one descriptor must always remain empty.
DS31256 Figure 9-6.
DS31256 Status/Interrupts On each read of the free queue by the DMA, the DMA sets either the status bit for receive DMA large buffer read (RLBR) or the status bit for receive DMA small buffer read (RSBR) in the status register for DMA (SDMA). The DMA also checks the receive free-queue large-buffer host write pointer and the receive free-queue small-buffer host write pointer to ensure that an underflow does not occur.
DS31256 Register Name: Register Description: Register Address: RDMAQ Receive DMA Queues Control 0780h Bit # Name Default 7 n/a 0 6 n/a 0 5 RDQF 0 4 RDQFE 0 3 RFQSF 0 2 RFQLF 0 1 n/a 0 0 RFQFE 0 Bit # Name Default 15 n/a 0 14 n/a 0 13 n/a 0 12 n/a 0 11 n/a 0 10 RDQT2 0 9 RDQT1 0 8 RDQT0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/Receive Free-Queue FIFO Enable (RFQFE).
DS31256 9.2.4 Done Queue The DMA writes to the receive done queue when it has filled a free data buffer with packet data and has loaded the associated packet descriptor with all the necessary information. The descriptor location is indicated through a 16-bit pointer that the host uses with the receive descriptor base address to find the exact 32-bit address of the associated receive descriptor. Figure 9-7.
DS31256 The host reads from the receive done queue to find which data buffers and their associated descriptors are ready for processing. The receive done queue is circular. A set of internal addresses within the device that are accessed by the host and the DMA keep track of the queue’s addresses. On initialization, the host configures all of the registers, as shown in Table 9-F. After initialization, the DMA only writes to (changes) the write pointer and the host only writes to the read pointer.
DS31256 Figure 9-8.
DS31256 buffers have been filled or wait until the completed packet data has been written. The DMA always writes to the done queue when it has finished receiving a packet, even if the threshold has not been met. Done-Queue Burst Writing The DMA has the ability to write to the done queue in bursts, which allows for a more efficient use of the PCI bus. The DMA can hand off descriptors to the done queue in groups rather than one at a time, freeing up the PCI bus for more time-critical functions.
DS31256 Register Name: Register Description: Register Address: RDQFFT Receive Done-Queue FIFO Flush Timer 0744h Bit # Name Default 7 TC7 0 6 TC6 0 5 TC5 0 4 TC4 0 3 TC3 0 2 TC2 0 1 TC1 0 0 TC0 0 Bit # Name Default 15 TC15 0 14 TC14 0 13 TC13 0 12 TC12 0 11 TC11 0 10 TC10 0 9 TC9 0 8 TC8 0 Note: Bits that are underlined are read-only, all other bits are read-write. Bits 0 to 15/Receive Done-Queue FIFO Flush Timer Control Bits (TC0 to TC15).
DS31256 Bits 8 to 10/Receive Done-Queue Status-Bit Threshold Setting (RDQT0 to RDQT2). These bits determine when the DMA sets the receive DMA done-queue write (RDQW) status bit in the status register for DMA (SDMA) register.
DS31256 - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 0; Bits 0 to 31/Current Data Buffer Address. The current 32-bit address of the data buffer that is being used. This address is used by the DMA to keep track of where data should be written to as it comes in from the receive FIFO. - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 1; Bits 0 to 15/Current Descriptor Pointer.
DS31256 - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 2; Bits 16 to 28/Byte Count. The DMA uses these 13 bits to keep track of the number of bytes stored in the data buffer. Maximum is 8188 Bytes (0000h = 0 Bytes / 1FFCh = 8188 Bytes). - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 2; Bits 29 to 31/Threshold Count. These bits keep track of the number of data buffers that have been filled so that the receive DMA knows when, based on the host-controlled threshold, to write to the done queue.
DS31256 ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the write operation has completed. Register Name: Register Description: Register Address: RDMAC Receive DMA Channel Configuration 0774h Bit # Name Default 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 Bit # Name Default 15 D15 14 D14 13 D13 12 D12 11 D11 10 D10 9 D9 8 D8 Note: Bits that are underlined are read-only, all other bits are read-write.
DS31256 Table 9-G. Transmit DMA Main Operational Areas DESCRIPTORS Packet Pending Queue Done Queue FUNCTION A dedicated area of memory that describes the location and attributes of the packet data. A dedicated area of memory that the host writes to inform the DMA that packet data is queued and ready for transmission. A dedicated area of memory that the DMA writes to inform the host that the packet data has been transmitted. SECTION 9.3.2 9.3.3 9.3.
DS31256 1) Priority packets are transmitted as soon as the current standard packet (not packet chain) finishes transmission. 2) All priority packets are transmitted before any more standard packets are transmitted. 3) Priority packets are ordered on a first come, first served basis. Figure 9-13 shows an example of a set of priority packets interrupting a set of standard packets.
DS31256 Figure 9-10. Transmit DMA Operation EOF = 1 Data Buffer Address EOF CV # Bytes Next Desc. Ptr. unused CH #5 unused PV Next Pend. Desc. Done-Queue Descriptors (circular queue) 00h Status CH#5 Free Desc. Ptr. 04h Status CH#1 Free Desc. Ptr. 08h Status CH# Free Desc. Ptr. 0Ch Status CH# Free Desc. Ptr. 10h Status CH# Free Desc. Ptr. 14h Status CH# Free Desc. Ptr. EOF = 0 Data Buffer Address EOF CV # Bytes Next Desc. Ptr. unused CH #1 unused PV Next Pend. Desc.
DS31256 Figure 9-11.
DS31256 Figure 9-12.
DS31256 Figure 9-13.
DS31256 DMA Updates to the Done Queue The host has two options for when the transmit DMA should write descriptors that have completed transmission to the done queue. On a channel-by-channel basis, through the done-queue select (DQS) bit in the transmit DMA configuration RAM, the host can condition the DMA to: 1) Write to the done queue only when the complete HDLC packet has been transmitted (DQS = 0). 2) Write to the done queue when each data buffer has been transmitted (DQS = 1).
DS31256 descriptor pointer and PV fields in the packet descriptor to 0 to ready them for transmission). The second option allows the software a cleaner error-recovery technique. See Figure 9-14 for more details. Figure 9-14.
DS31256 9.3.2 Packet Descriptors A contiguous section of up to 65,536 quad dwords that make up the transmit packet descriptors resides in main memory. The transmit packet descriptors are aligned on a quad-dword basis and can be placed anywhere in the 32-bit address space through the transmit descriptor base address (Table 9-I). A data buffer is associated with each descriptor. The data buffer can be up to 8188 Bytes long and must be a contiguous section of main memory.
DS31256 Figure 9-16. Transmit Packet Descriptors dword 0 Data Buffer Address (32) dword 1 EOF dword 2 CV unused Byte Count (13) Next Descriptor Pointer (16) unused (24) HDLC CH# (8) dword 3 unused (15) PV Next Pending Descriptor Pointer (16) Note 1: The organization of the transmit descriptor is not affected by the enabling of Big Endian.
DS31256 9.3.3 Pending Queue The host writes to the transmit pending queue the location of the readied descriptor, channel number, and control information. The descriptor space is indicated through a 16-bit pointer, which the DMA uses with the transmit packet-descriptor base address to find the exact 32-bit address of the associated transmit packet descriptor. Figure 9-17.
DS31256 The transmit DMA reads from the transmit pending-queue descriptor circular queue which data buffers and their associated descriptors are ready for transmission. A set of internal addresses within the device that are accessed by both the host and the DMA keep track of the circular queue addresses in the transmit pending queue. On initialization, the host configures all of the registers shown in Table 9-J.
DS31256 Figure 9-18.
DS31256 read pointer, and sets the status bit for transmit DMA pending-queue read (TPQR) in the status register for DMA (SDMA). See Section 5 for more details about status bits.
DS31256 9.3.4 Done Queue The DMA writes to the transmit done queue when it has finished either transmitting a complete packet chain or a complete data buffer. This option is selected by the host when it configures the DQS field in the transmit DMA configuration RAM (Section 9.3.5). The descriptor location is indicated in the done queue through a 16-bit pointer that the host uses along with the transmit descriptor base address to find the exact 32-bit address of the associated transmit descriptor.
DS31256 The host reads from the transmit done queue to find which data buffers and their associated descriptors have completed transmission. The transmit done queue is circular. A set of internal addresses within the device that are accessed by both the host and the DMA keep track of the circular queue addresses in the transmit done queue. On initialization, the host configures all of the registers, as shown in Table 9-K.
DS31256 Figure 9-20.
DS31256 When enabled through the transmit done-queue FIFO-enable (TDQFE) bit, the done-queue FIFO does not write to the done queue until it reaches the high watermark. When the done-queue FIFO reaches the high watermark (which is six descriptors), it attempts to empty the done-queue FIFO by burst writing to the done queue. Before it writes to the done queue, it checks (by examining the transmit done-queue host read pointer) to ensure the done queue has enough room to empty.
DS31256 Register Name: Register Description: Register Address: TDMAQ Transmit DMA Queues Control 0880h Bit # Name Default 7 n/a 0 6 n/a 0 5 n/a 0 4 n/a 0 3 TDQF 0 2 TDQFE 0 1 TPQF 0 0 TPQFE 0 Bit # Name Default 15 n/a 0 14 n/a 0 13 n/a 0 12 n/a 0 11 n/a 0 10 TDQT2 0 9 TDQT1 0 8 TDQT0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/Transmit Pending-Queue FIFO Enable (TPQFE). See Section 9.3.3 for details.
DS31256 9.3.5 DMA Configuration RAM The device contains an on-board set of 1536 dwords (6 dwords per channel times 256 channels) that are used by the host to configure the DMA and used by the DMA to store values locally when it is processing a packet. Most of the fields within the DMA configuration RAM are for DMA use and the host never writes to these fields. The host is only allowed to write (configure) to the lower word of dword 1 for each HDLC channel.
DS31256 - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 0; Bits 0 to 31/Current Data Buffer Address. This is the current 32-bit address of the data buffer that is being used. This address is used by the DMA to keep track of where data should be read from as it is passed to the transmit FIFO. - HOST MUST CONFIGURE dword 1; Bit 0/Channel Enable (CHEN). This bit is controlled by both the host and the transmit DMA to enable and disable a HDLC channel.
DS31256 - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 1; Bits 20 to 21/Priority State (PRIST). This field is used by the transmit DMA to keep track of queued priority descriptors as they arrive from the pending queue, and for the DMA to know when it should create a horizontal linked list of transmit priority descriptors and where it can find the next valid priority descriptor. This field handles priority packets and the PENDST field handles standard packets.
DS31256 - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 5; Bits 16 to 31/Next Priority Pending Descriptor Pointer. This 16-bit value is the offset from the transmit descriptor base address of the first transmit priority packet descriptor for the packet priority that is queued up next for transmission.
DS31256 Register Name: Register Description: Register Address: TDMAC Transmit DMA Configuration 0874h Bit # Name Default 7 D7 0 6 D6 0 5 D5 0 4 D4 0 3 D3 0 2 D2 0 1 D1 0 0 D0 0 Bit # Name Default 15 D15 0 14 D14 0 13 D13 0 12 D12 0 11 D11 0 10 D10 0 9 D9 0 8 D8 0 Note: Bits that are underlined are read only, all other bits are read-write. Bits 0 to 15/Transmit DMA Configuration RAM Data (D0 to D15). Data that is written to or read from the transmit DMA configuration RAM.
DS31256 10. PCI BUS 10.1 General Description of Operation The PCI block interfaces the DMA block to an external high-speed bus. The PCI block complies with Revision 2.1 (June 1, 1995) of the PCI Local Bus Specification. HDLC packet data always passes to and from the Envoy through the PCI bus. The user has the option to configure and monitor the internal device registers either through the PCI bus (local bus bridge mode) or through the local bus (local bus configuration mode).
DS31256 10.1.1 PCI Read Cycle A read cycle on the PCI bus is shown in Figure 10-2. During clock cycle #1, the initiator asserts the PFRAME signal and drives the address onto the PAD signal lines and the bus command (which would be a read) onto the PCBE signal lines. The target reads the address and bus command and, if the address matches its own, it then asserts the PDEVSEL signal and begins the bus transaction.
DS31256 10.1.2 PCI Write Cycle A write cycle on the PCI bus is shown in Figure 10-3. During clock cycle #1, the initiator asserts the PFRAME signal and drives the address onto the PAD signal lines and the bus command (which would be a write) onto the PCBE signal lines. The target reads the address and bus command and, if the address matches its own, it then asserts the PDEVSEL signal and begins the bus transaction.
DS31256 10.1.3 PCI Bus Arbitration The PCI bus can be arbitrated as shown in Figure 10-4. The initiator requests bus access by asserting PREQ. A central arbiter grants the access some time later by asserting PGNT. Once the bus has been granted, the initiator waits until both PIRDY and PFRAME are deasserted (i.e., an idle cycle) before acquiring the bus and beginning the transaction.
DS31256 10.1.5 PCI Target Retry Targets can terminate the requested bus transaction before any data is transferred because the target is busy and temporarily unable to process the transaction. Such a termination is called a target retry and no data is transferred. A target retry is signaled to the initiator by the assertion of PSTOP and not asserting PTRDY on the initial data phase (Figure 10-6). When the Envoy is a target, it only issues a target retry when the host is accessing the local bus.
DS31256 10.1.7 PCI Target Abort Targets can also abort the current transaction, which means they do not wish for the initiator to attempt the request again. No data is transferred in a target abort scenario. A target abort is signaled to the initiator by the simultaneous assertion of PSTOP and deassertion of PDEVSEL (Figure 10-8). When the Envoy is a target, it only issues a target abort when the host is accessing the local bus.
DS31256 10.1.8 PCI Fast Back-to-Back Fast back-to-back transactions are two consecutive bus transactions without the usually required idle cycle (PFRAME and PIRDY deasserted) between them. This can only occur when there is a guarantee that there is not any contention on the signal lines. The PCI specification allows two types of fast backto-back transactions—those that access the same agent (Type 1) and those that do not (Type 2).
DS31256 10.2 PCI Configuration Register Description Register Name: Register Description: Register Address: PVID0 PCI Vendor ID/Device ID Register 0 0x000 LSB Vendor ID (Read Only/Set to EAh) Vendor ID (Read Only/Set to 13h) Device ID (Read Only/Set to 34h) MSB Device ID (Read Only/Set to 31h) Bits 0 to 15/Vendor ID. These read-only bits identify Dallas Semiconductor as the device’s manufacturer. The vendor ID was assigned by the PCI Special Interest Group and is fixed at 13EAh. Bits 16 to 31/Device ID.
DS31256 10.2.1 Command Bits (PCMD0) Bit 0/I/O Space Control (IOC). This read-only bit is forced to 0 by the device to indicate that it does not respond to I/O space accesses. Bit 1/Memory Space Control (MSC). This read/write bit controls whether or not the device responds to accesses by the PCI bus to the memory space (the internal device configuration registers). When this bit is set to 0, the device ignores accesses attempted to the internal configuration registers.
DS31256 10.2.2 Status Bits (PCMD0) The upper word in the PCMD0 register is the status portion, which reports events as they occur. As previously mentioned, reads of the status portion occur normally but writes are unique in that bits can only be reset (i.e., forced to 0). This occurs when 1 is written to a bit position. Writes with a 0 to a bit position have no affect. This allows individual bits to be reset. Bits 16 to 20/Reserved. These read-only bits are forced to 0 by the device.
DS31256 Register Name: Register Description: Register Address: PRCC0 PCI Revision ID/Class Code Register 0 0x008h LSB Revision ID (Read Only/Set to 00h) Class Code (Read Only/Set to 00h) Class Code (Read Only/Set to 80h) MSB Class Code (Read Only/Set to 02h) Bits 0 to 7/Revision ID. These read-only bits identify the specific device revision, which is selected by Dallas Semiconductor. Bits 8 to 15/Class Code Interface.
DS31256 Register Name: Register Description: Register Address: PDCM PCI Device Configuration Memory Base Address Register 0x010h Base Address (Read Only/Set to 0h) TYPE1 PF Base Address TYPE0 LSB MSI Base Address (Read Only/Set to 0h) Base Address MSB Base Address Note: Read-only bits in the PDCM register are underlined; all other bits are read-write. Bit 0/Memory Space Indicator (MSI).
DS31256 Register Name: Register Description: Register Address: PVID1 PCI Vendor ID/Device ID Register 1 0x100h LSB Vendor ID (Read Only/Set to EAh) Vendor ID (Read Only/Set to 13h) Device ID (Read Only/Set to 34h) MSB Device ID (Read Only/Set to 31h) Bits 0 to 15/Vendor ID. These read-only bits identify Dallas Semiconductor as the device’s manufacturer. The vendor ID was assigned by the PCI Special Interest Group and is fixed at 13EAh. Bits 16 to 31/Device ID.
DS31256 10.2.3 Command Bits (PCMD1) Bit 0/I/O Space Control (IOC). This read-only bit is forced to 0 by the device to indicate that it does not respond to I/O space accesses. Bit 1/Memory Space Control (MSC). This read/write bit controls whether or not the device responds to accesses by the PCI bus to the memory space, which is the local bus. When this bit is set to 0, the device ignores accesses attempted to the local bus. When set to 1, the device allows accesses to the local bus.
DS31256 10.2.4 Status Bits (PCMD1) The upper word in the PCMD1 register is the status portion, which reports events as they occur. As mentioned earlier, reads of the status portion occur normally, but writes are unique in that bits can only be reset (i.e., forced to 0). This occurs when 1 is written to a bit position. Writes with a 0 to a bit position have no affect. This allows individual bits to be reset. Bits 16 to 20/Reserved. These read-only bits are forced to 0 by the device.
DS31256 Register Name: Register Description: Register Address: PRCC1 PCI Revision ID/Class Code Register 1 0x108h LSB Revision ID (Read Only/Set to 00h) Class Code (Read Only/Set to 00h) Class Code (Read Only/Set to 80h) MSB Class Code (Read Only/Set to 06h) Bits 0 to 7/Revision ID. These read-only bits identify the specific device revision, selected by Dallas Semiconductor. Bits 8 to 15/Class Code Interface. These read-only bits identify the subclass interface value for the device and are fixed at 00h.
DS31256 Register Name: Register Description: Register Address: PLBM PCI Local Bus Memory Base Address Register 0x110h LSB Base Address (Read Only/Set to 0h) PF TYPE1 Base Address TYPE0 MSI Base Address (Read Only/Set to 0h) Base Address MSB Base Address Note: Read-only bits in the PLBM register are underlined; all other bits are read-write. Bit 0/Memory Space Indicator (MSI). This read-only bit is forced to 0 to indicate that the local bus is mapped to memory space.
DS31256 11. LOCAL BUS 11.1 General Description The local bus can operate in two modes, either as a PCI bridge (master mode) or as a configuration bus (slave mode). This selection is made in hardware by connecting the LMS pin high or low. Figure 11-1 shows an example of the local bus operating in the PCI bridge mode. In this example, the host can access the control ports on the T1/E1 devices through the local bus.
DS31256 Figure 11-1. Bridge Mode T1 / E1 Framer or Transceiver PCI / Custom Bus T1 / E1 Framer or Transceiver DS31256 ENVOY Host Processor and Main Memory T1 / E1 Framer or Transceiver T1 / E1 Framer or Transceiver Local Bus Figure 11-2. Bridge Mode with Arbitration Enabled T1 / E1 Framer or Transceiver DS31256 ENVOY PCI / Custom Bus T1 / E1 Framer or Transceiver T1 / E1 Framer or Transceiver 1 2 T1 / E1 Framer or Transceiver 3 1. Request Bus Access 2. Bus Access Granted 3.
DS31256 Figure 11-3. Configuration Mode T1 / E1 Framer or Transceiver DS31256 ENVOY PCI / Custom Bus No Access Allowed T1 / E1 Framer or Transceiver T1 / E1 Framer or Transceiver Host Processor and Main Memory Only Used to Transfer HDLC Data T1 / E1 Framer or Transceiver Local Bus CPU Configures and Monitors DS3134 11.1.1 Local RAM & ROM PCI Bridge Mode In PCI bridge mode, data from the PCI bus can be transferred to the local bus.
DS31256 Table 11-B. Local Bus 8-Bit Width Address, LBHE Setting PCBE [3:0] 1110 1101 1011 0111 A1 0 0 1 1 A0 0 1 0 1 LBHE 1 1 1 1 Note 1: All other possible states for PCBE cause the device to return a target abort to the host. Note 2: The 8-bit data picked from the PCI bus is routed/sampled to/from the LD[7:0] signal lines. Note 3: If no PCBE signals are asserted during an access, a target abort is not returned and no transaction occurs on the local bus.
DS31256 Bridge Mode Bus Transaction Timing When the local bus is operated in PCI bridge mode, the bus transaction time can be determined either from an external ready signal (LRDY) or from the PCI bridge mode control register (LBBMC), which allows a bus transaction time of 1 to 11 LCLK cycles. If the total access time to the local bus exceeds 16 PCLK cycles, the PCI access times out and a PCI target retry is sent to the host. This only occurs when LRDY has not been detected within 9 clocks.
DS31256 Figure 11-4.
DS31256 11.2 Local Bus Bridge Mode Control Register Description Register Name: Register Description: Register Address: LBBMC Local Bus Bridge Mode Control 0040h Note: This register can only be accessed through the PCI bus and therefore only in the PCI bridge mode. In configuration mode, this register cannot be accessed. It is set to all zeros upon a hardware reset issued through the PRST pin.
DS31256 Bit 6/Local Bus Width (LBW) 0 = 16 bits 1 = 8 bits Bits 8 to 11/Local Bus Arbitration Timer Setting (LAT0 to LAT3). These four bits determine the total time the local bus seizes the bus when it has been granted in the arbitration mode (LARBE = 1). This period is measured from LHLDA (LBG) being detected to LBGACK inactive.
DS31256 11.3 Examples of Bus Timing for Local Bus PCI Bridge Mode Operation Figure 11-5. 8-Bit Read Cycle Intel Mode (LIM = 0) Arbitration Enabled (LARBE = 1) Bus Transaction Time = 4 LCLK (LRDY = 0100) An attempted access by the host causes the local bus to request the bus. If bus access has not been granted (LBGACK deasserted), the timing shown at the top of the page applies, with LHOLD being asserted. Once LHLDA is detected, the local bus grabs the bus for 32 to 1,048,576 clocks and then releases it.
DS31256 Figure 11-6. 16-Bit Write Cycle Intel Mode (LIM = 0) Arbitration Enabled (LARBE = 1) Bus Transaction Time = 4 LCLK (LRDY = 0100) An attempted access by the host causes the local bus to request the bus. If bus access has not been granted (LBGACK deasserted), the timing shown at the top of the page applies, with LHOLD being asserted. Once LHLDA is detected, the local bus grabs the bus for 32 to 1,048,576 clocks and then releases it.
DS31256 Figure 11-7. 8-Bit Read Cycle Intel Mode (LIM = 0) Arbitration Disabled (LARBE = 0) Bus Transaction Time = Timed from LRDY (LRDY = 0000) LCLK LA[19:0] 1 2 3 4 5 6 7 8 9 Address Valid LD[7:0] LD[15:8] LBHE LWR LRD LRDY Note: The LRDY signal must be detected by the 9th LCLK or the bus access attempted by the host is unsuccessful and the LBE status bit is set.
DS31256 Figure 11-8. 16-Bit Write (Only Upper 8 Bits Active) Cycle Intel Mode (LIM = 0) Arbitration Disabled (LARBE = 0) Bus Transaction Time = Timed from LRDY (LRDY = 0000) LCLK LA[19:0] 1 2 3 4 5 6 7 8 9 10 Address Valid LD[7:0] LD[15:8] Data Valid LBHE LRD LWR LRDY Note: The LRDY signal must be detected by the 9th LCLK or the bus access attempted by the host is unsuccessful and the LBE status bit is set.
DS31256 Figure 11-9. 8-Bit Read Cycle Motorola Mode (LIM = 1) Arbitration Enabled (LARBE = 1) Bus Transaction Time = 6 LCLK (LRDY = 0110) An attempted access by the host causes the local bus to request the bus. If bus access has not been granted (LBGACK deasserted), the timing shown at the top of the page applies, with LBR being asserted. Once LBG is detected, the local bus grabs the bus for 32 to 1,048,576 clocks and then releases it.
DS31256 Figure 11-10. 8-Bit Write Cycle Motorola Mode (LIM = 1) Arbitration Enabled (LARBE = 1) Bus Transaction Time = 6 LCLK (LRDY = 0110) An attempted access by the host causes the local bus to request the bus. If bus access has not been granted (LBGACK deasserted), the timing shown at the top of the page applies, with LBR being asserted. Once LBG is detected, the local bus grabs the bus for 32 to 1,048,576 clocks and then releases it.
DS31256 Figure 11-11. 16-Bit Read Cycle Motorola Mode (LIM = 1) Arbitration Disabled (LARBE = 0) Bus Transaction Time = Timed from LRDY (LRDY = 0000) LCLK LA[19:0] 1 2 3 4 5 6 7 8 9 10 Address Valid LD[7:0] LD[15:8] LBHE LR/W LDS LRDY Note: The LRDY signal must be detected by the 9th LCLK or the bus access attempted by the host is unsuccessful and the LBE status bit is set.
DS31256 Figure 11-12. 8-Bit Write Cycle Motorola Mode (LIM = 1) Arbitration Disabled (LARBE = 0) Bus Transaction Time = Timed from LRDY (LRDY = 0000) LCLK LA[19:0] LD[7:0] 1 2 3 4 5 6 7 8 9 10 Address Valid Data Valid Three-State LD[15:8] LBHE LR/W LDS LRDY Note: The LRDY signal must be detected by the 9th LCLK or the bus access attempted by the host is unsuccessful and the LBE status bit is set.
DS31256 12. JTAG 12.1 JTAG Description The DS31256 supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. Figure 12-1 is a block diagram. The DS31256 contains the following items, which meet the requirements set by the IEEE 1149.
DS31256 12.2 TAP Controller State Machine Description This section details the operation of the TAP controller state machine. See Figure 12-2 for details about each of the states. The TAP controller is a finite state machine, which responds to the logic level at JTMS on the rising edge of JTCLK. Figure 12-2.
DS31256 Test-Logic-Reset. The TAP controller is in the Test-Logic-Reset state upon DS31256 power-up. The instruction register contains the IDCODE instruction. All system logic on the DS31256 operates normally. Run-Test-Idle. Run-Test-Idle is used between scan operations or during specific tests. The instruction and test registers remain idle. Select-DR-Scan. All test registers retain their previous state.
DS31256 well as all test registers remain at their previous states. A rising edge on JTCLK with JTMS high moves the controller to the Exit1-IR state. A rising edge on JTCLK with JTMS low keeps the controller in the Shift-IR state while moving data one stage through the instruction shift register. Exit1-IR. A rising edge on JTCLK with JTMS low puts the controller in the Pause-IR state. If JTMS is high on the rising edge of JTCLK, the controller enters the Update-IR state and terminates the scanning process.
DS31256 BYPASS. When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO through the 1-bit bypass test register. This allows data to pass from JTDI to JTDO without affecting the device’s normal operation. IDCODE. When the IDCODE instruction is latched into the parallel instruction register, the identification test register is selected.
DS31256 13. AC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Voltage on Any Lead with Respect to VSS (except VDD) Supply Voltage (VDD) with Respect to VSS Operating Temperature/Ambient Temperature Under Bias Junction Temperature Under Bias Storage Temperature Range Soldering Temperature Range ESD Tolerance (Note 1) -0.3V to 5.5V -0.3V to 3.63V 0°C to +70°C £125°C -55°C to +125°C See IPC/JEDEC J-STD-020A Class 2 (2000V→4000V HBM: 1.
DS31256 AC CHARACTERISTICS: LAYER 1 PORTS (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.
DS31256 AC CHARACTERISTICS: LOCAL BUS IN BRIDGE MODE (LMS = 0) (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.
DS31256 AC CHARACTERISTICS: LOCAL BUS IN CONFIGURATION MODE (LMS = 1) (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.
DS31256 Figure 13-3.
DS31256 Figure 13-4.
DS31256 AC CHARACTERISTICS: PCI BUS INTERFACE (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.
DS31256 AC CHARACTERISTICS: JTAG TEST PORT INTERFACE (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.) PARAMETER JTCLK Clock Period JTCLK Clock Low Time JTCLK Clock High Time JTMS/JTDI Setup Time to the Rising Edge of JTCLK JTMS/JTDI Hold Time from the Rising Edge of JTCLK Delay Time from the Falling Edge of JTCLK to Data Valid on JTDO SYMBOL t1 t2 t3 CONDITIONS MIN 1000 400 400 TYP MAX UNITS ns ns ns t4 50 ns t5 50 ns t6 2 Figure 13-6.
DS31256 14. MECHANICAL DIMENSIONS 14.
DS31256 15. APPLICATIONS This section describes some possible applications for the DS31256. There are numerous potential configurations but only a few are shown. Users are encouraged to contact the factory for support of their particular application. Email telecom.support@dalsemi.com or visit our website at www.maxim-ic.com/telecom for more information. The T1 and E1 channelized application examples in this section are one of two types.
DS31256 Figure 15-3. Quad T1/E1 Connection 15.1 16 Port T1 or E1 with 256 HDLC Channel Support Figure 15-4 shows an application where 16 T1 or E1 links are framed and interfaced to a single DS31256. The T1 lines can be either clear-channel or channelized. The DS21Q55 quad T1/E1/J1 single-chip transceiver performs the line interface function and frames to the T1/E1/J1 line. Figure 15-4.
DS31256 15.2 Dual T3 with 256 HDLC Channel Support Figure 15-5 shows an application where two T3 lines are interfaced to a single DS31256. The T3 lines are demultiplexed by DS3112 M13 devices and passed to the DS21FF42 4 x 4 16-channel T1 framer and DS21FT42 4 x 3 12-channel T1 framer devices. The T1 framers locate the frame and multiframe boundaries and interface to the DS31256 by aggregating four T1 lines into a single 8.192MHz data stream, which then flows into and out of the DS31256.
DS31256 15.3 Single T3 with 512 HDLC Channel Support Figure 15-6 shows an application where a T3 line is interfaced to two DS31256s. The T3 line is demultiplexed by the M13 block and passed to the DS21FF42 and DS21FT42 devices. The T1 framers locate the frame and multiframe boundaries and interface to the DS31256. Aggregating four T1 lines into a single 8.
DS31256 15.4 Single T3 with 672 HDLC Channel Support Figure 15-7 shows an application where a fully channelized T3 line is interfaced to three DS31256s. The T3 line is demultiplexed by the M13 block and passed to the DS21FF42 and DS21FT42 devices. The T1 framers locate the frame and multiframe boundaries and interface to the DS31256. Aggregating four T1 lines into a single 8.
