DEMO KIT AVAILABLE DS3131 BoSS 40-Port, Unchannelized Bit-Synchronous HDLC www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS3131 bit-synchronous (BoSS) HDLC controller can handle up to 40 channels of highspeed, unchannelized, bit-synchronous HDLC. The on-board DMA has been optimized for maximum flexibility and PCI bus efficiency to minimize host processor intervention in the data path. Diagnostic loopbacks and an on-board BERT remove the need for external components.
DS3131 TABLE OF CONTENTS 1. 2. 3. MAIN FEATURES .......................................................................................................................... 6 DETAILED DESCRIPTION .......................................................................................................... 7 SIGNAL DESCRIPTION.............................................................................................................. 14 3.1 3.2 3.3 3.4 3.5 3.6 3.7 4. OVERVIEW/SIGNAL LIST......................
DS3131 9.2.4 Done Queue.........................................................................................................................................87 9.2.5 DMA Configuration RAM ...................................................................................................................93 9.3 TRANSMIT SIDE........................................................................................................................................97 9.3.1 Overview ...............................
DS3131 LIST OF FIGURES Figure 2-1. Block Diagram ........................................................................................................................ 10 Figure 2-2. Configuration Options............................................................................................................. 11 Figure 3-1. Signal Floorplan ...................................................................................................................... 19 Figure 5-1.
DS3131 Figure 11-9. 8-Bit Read Cycle ................................................................................................................. 151 Figure 11-10. 8-Bit Write Cycle .............................................................................................................. 152 Figure 11-11. 16-Bit Read Cycle ............................................................................................................. 153 Figure 11-12. 8-Bit Write Cycle ...............................
DS3131 1.
DS3131 Table 1-A. Data Sheet Definitions The following terms are used throughout this data sheet. Note: The DS3131’s ports are numbered 0 to 39; the HDLC channels are numbered 1 to 40. HDLC Channel 1 is always associated with Port 0, HDLC Channel 2 with Port 1, and so on. TERM BERT Descriptor Dword DMA FIFO HDLC Host n/a DEFINITION Bit Error-Rate Tester A message passed back and forth between the DMA and the host Double word; a 32-bit data entity Direct Memory Access First In, First Out.
DS3131 The FIFO transfers data from the HDLC engines into the FIFO and checks to see if the FIFO has filled to beyond the programmable high watermark. If it has, the FIFO signals to the DMA that data is ready to be burst read from the FIFO to the PCI bus. The FIFO block controls the DMA block and it tells the DMA when to transfer data from the FIFO to the PCI bus.
DS3131 The DMA uses a set of descriptors to know where to store the incoming HDLC packet data and where to obtain HDLC packet data ready to be transmitted. The descriptors are fixed-size messages that are handed back and forth from the DMA to the host. Since this descriptor transfer uses bus cycles, the DMA has been structured to minimize the number of transfers required.
DS3131 Figure 2-1. Block Diagram RECEIVE DIRECTION INTERNAL CONTROL BUS BERT (SECT. 6) JTRST JTDI JTMS JTCLK JTDO PCI BLOCK (SECT. 10) PCLK PRST PAD[31:0] PCBE[3:0] PPAR PFRAME PIRDY PTRDY PSTOP PIDSEL PDEVSEL PREQ PGNT PPERR PSERR PXAS PXDS PXBLAST DS3131 JTAG TEST ACCESS LOCAL BUS BLOCK (SECT. 11) RC39 RD39 TC39 TD39 DMA BLOCK (SECT. 9) RC2 RD2 TC2 TD2 FIFO BLOCK (SECT. 8) RC1 RD1 TC1 TD1 LAYER 1 BLOCK (SECT. 6) RC0 RD0 TC0 TD0 40-BIT SYNCHRONOUS HDLC CONTROLLERS (SECT.
DS3131 Figure 2-2.
DS3131 Restrictions In creating the overall system architecture, the user must balance the port, throughput, and HDLC channel restrictions of the DS3131. Table 2-A lists all of the upper-bound maximum restrictions. Table 2-A. Restrictions ITEM Port Throughput HDLC RESTRICTION Maximum of 40 physical ports Maximum data rate of 52Mbps Maximum receive: 132Mbps (Refer to Application Note 358: DS3134 PCI Bus Utilization.
DS3131 Table 2-B.
DS3131 3. SIGNAL DESCRIPTION 3.1 Overview/Signal List This section describes the input and output signals on the DS3131. Signal names follow a convention that is shown in the Signal Naming Convention table below. Table 3-A lists all of the signals, their signal type, description, and pin location. Signal Naming Convention FIRST LETTER R T L J P SIGNAL CATEGORY SECTION Receive Serial Port Transmit Serial Port Local Bus JTAG Test Port PCI Bus 3.2 3.2 3.3 3.4 3.
DS3131 PIN NAME TYPE T18 T20 P17 R20 P19 N18 N20 M18 M20 L18 K20 K18 J19 H20 H18 G19 G18 E20 F18 D20 D19 E17 C19 C18 A20 W9, U14, C10 V17 U16 Y18 W17 V16 Y17 W16 V15 W15 V14 Y15 W14 Y14 V13 W13 Y13 V9 U9 Y8 W8 V8 Y7 W7 V7 U7 V6 TD3 TD4 TD5 TD6 TD7 TD8 TD9 TD10 TD11 TD12 TD13 TD14 TD15 TD16 TD17 TD18 TD19 TD20 TD21 TD22 TD23 TD24 TD25 TD26 TD27 N.C.
DS3131 PIN NAME TYPE Y5 W5 V5 Y4 Y3 U5 Y16 V12 Y9 W6 Y2 Y11 W10 W4 Y6 W18 V10 W12 V11 V4 W3 Y12 W11 Y10 V18 Y20 W19 Y1 V3 V2 T4 U2 U1 R3 T1 P3 P2 N3 N1 M2 L3 L1 K3 J1 J3 H1 H3 G2 F1 G4 E1 E3 PAD26 PAD27 PAD28 PAD29 PAD30 PAD31 PCBE0 PCBE1 PCBE2 PCBE3 PCLK PDEVSEL PFRAME PGNT PIDSEL PINT PIRDY PPAR PPERR PREQ PRST PSERR PSTOP PTRDY PXAS PXBLAST PXDS RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RC8 RC9 RC10 RC11 RC12 RC13 RC14 RC15 RC16 RC17 RC18 RC19 RC20 RC21 RC22 RC23 RC24 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I
DS3131 PIN NAME TYPE C1 D3 C2 W2 W1 U3 V1 T3 T2 P4 R2 R1 P1 N2 M3 M1 L2 K1 K2 J2 J4 H2 G1 G3 F2 F3 E2 D1 E4 D2 B1 A19 D16 B18 B17 C17 C8 A7 B7 A6 C7 B6 A5 D7 C6 B5 A4 C5 B4 A3 D5 C4 RC25 RC26 RC27 RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RD8 RD9 RD10 RD11 RD12 RD13 RD14 RD15 RD16 RD17 RD18 RD19 RD20 RD21 RD22 RD23 RD24 RD25 RD26 RD27 JTMS JTDO JTCLK JTRST JTDI LA0–RD37 LA1–RC37 LA2–RD36 LA3–RC36 LA4–RD35 LA5–RC35 LA6–RD34 LA7–RC34 LA8–RD33 LA9–RC33 LA10–RD32 LA11–RC32 LA12–RD31 LA13–RC31 LA14–RD30 LA15–RC30 I I
DS3131 PIN NAME TYPE FUNCTION B3 B2 A2 C3 A18 A17 C16 B16 A16 C15 D14 B15 A15 C14 B14 A14 C13 B13 A13 D12 C9 B11 B10 LA16–RD29 LA17–RC29 LA18–RD28 LA19–RC28 LD0–TC28 LD1–TD28 LD2–TC29 LD3–TD29 LD4–TC30 LD5–TD30 LD6–TC31 LD7–TD31 LD8–TC32 LD9–TD32 LD10–TC33 LD11–TD33 LD12–TC34 LD13–TD34 LD14–TC35 LD15–TD35 LMS–RD39 LBHE–TD37 LHOLD–TD39 I/O–I I/O–I I/O–I I/O–I I/O–I I/O–O I/O–I I/O–O I/O–I I/O–O I/O–I I/O–O I/O–I I/O–O I/O–I I/O–O I/O–I I/O–O I/O–I I/O–O I–I O–O O–O A9 LWR–RC39 I/O–I C12 LIM–TC36
DS3131 Figure 3-1.
DS3131 3.2 Serial Port Interface Signal Description Signal Name: RC0 to RC39 Signal Description: Receive Serial Clock Signal Type: Input Data can be clocked into the device either on rising edges (normal clock mode) or falling edges (inverted clock mode) of RC. This is programmable on a per port basis. RC can operate at speeds from DC to 52MHz. Clock gapping is acceptable. If not used, this signal should be wired low.
DS3131 Signal Name: LBPXS Signal Description: Local Bus or Port Extension Select Signal Type: Input (with internal 10kΩ pullup) This signal must be left open-circuited (or connected high) to activate and enable the local bus. When this signal is connected low, the local bus is disabled and its signals are redefined to support 12 bit-synchronous HDLC controllers on ports 28 to 39 (Table 3-A).
DS3131 Signal Name: LRD (LDS LDS) LDS Signal Description: Local Bus Read Enable (Local Bus Data Strobe) Signal Type: Input/Output (three-state capable) In the PCI bridge mode (LMS = 0), this active-low output signal is asserted on the rising edge of LCLK. In Intel mode (LIM = 0), it is asserted when data is to be read from the local bus. In Motorola mode (LIM = 1), the rising edge is used to write data into the slave device.
DS3131 Signal Name: LBHE Signal Description: Local Bus Byte-High Enable (PCI Bridge Mode Only) Signal Type: Output (three-state capable) This active-low output signal is asserted when all 16 bits of the data bus (LD[15:0]) are active. It remains high if only the lower 8 bits (LD[7:0)] are active.
DS3131 3.5 PCI Bus Signal Description Signal Name: PCLK Signal Description: PCI and System Clock Signal Type: Input (Schmitt triggered) This clock input provides timing for the PCI bus and the device’s internal logic. A 33MHz clock with a nominal 50% duty cycle should be applied here. Signal Name: PRST Signal Description: PCI Reset Signal Type: Input This active-low input is used to force an asynchronous reset to both the PCI bus and the device’s internal logic.
DS3131 updated on the rising edge of PCLK. When the device is a target, this signal is an input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, PFRAME is three-stated. Signal Name: PIRDY Signal Description: PCI Initiator Ready Signal Type: Input/Output (three-state capable) The initiator creates this active-low signal to signal the target that it is ready to send/accept or to continue sending/accepting data.
DS3131 Signal Name: PREQ Signal Description: PCI Bus Request Signal Type: Output (three-state capable) The initiator asserts this active-low signal to request that the PCI bus arbiter allow it access to the bus. PREQ is updated on the rising edge of PCLK. Signal Name: PGNT Signal Description: PCI Bus Grant Signal Type: Input The PCI bus arbiter asserts this active-low signal to indicate to the PCI requesting agent that access to the PCI bus has been granted.
DS3131 Signal Name: PXBLAST Signal Description: PCI Extension Burst Last Signal Type: Output This active-low signal is asserted on the same clock edge as PFRAME is deasserted and is deasserted on the same clock edge as PIRDY is deasserted. This signal is only asserted when the device is an initiator. This signal is an output and is updated on the rising edge of PCLK. 3.
DS3131 4. MEMORY MAP 4.1 Introduction All addresses within the memory map are on dword boundaries, even though all internal device configuration registers are only one word (16 bits) wide. The memory map consumes an address range of 4kb (12 bits). When the PCI bus is the host (i.e.
DS3131 4.
DS3131 4.
DS3131 4.
DS3131 4.
DS3131 4.7 BERT Registers (5xx) OFFSET/ ADDRESS 0500 0504 0508 050C 0510 0514 0518 051C NAME BERTC0 BERTC1 BERTRP0 BERTRP1 BERTBC0 BERTBC1 BERTEC0 BERTEC1 REGISTER BERT Control 0 BERT Control 1 BERT Repetitive Pattern Set 0 (lower word) BERT Repetitive Pattern Set 1 (upper word) BERT Bit Counter 0 (lower word) BERT Bit Counter 1 (upper word) BERT Error Counter 0 (lower word) BERT Error Counter 1 (upper word) SECTION 6.4 6.4 6.4 6.4 6.4 6.4 6.4 6.4 4.
DS3131 4.
DS3131 4.11 PCI Configuration Registers for Function 0 (PIDSEL/Axx) OFFSET/ ADDRESS 0x000/0A00 0x004/0A04 0x008/0A08 0x00C/0A0C 0x010/0A10 0x03C/0A3C NAME PVID0 PCMD0 PRCC0 PLTH0 PDCM PINTL0 REGISTER PCI Vendor ID/Device ID 0 PCI Command Status 0 PCI Revision ID/Class Code 0 PCI Cache Line Size/Latency Timer/Header Type 0 PCI Device Configuration Memory Base Address PCI Interrupt Line and Pin /Min Grant/Max Latency 0 SECTION 10.2 10.2 10.2 10.2 10.2 10.2 4.
DS3131 5. GENERAL DEVICE CONFIGURATION AND STATUS/INTERRUPT 5.1 Master Reset and ID Register Description The master reset and ID (MRID) register can be used to globally reset the device. When the RST bit is set to 1, all of the internal registers (except the PCI configuration registers) are placed into their default state, which is 0000h. The host must set the RST bit back to 0 before the device can be programmed for normal operation.
DS3131 5.2 Master Configuration Register Description The master configuration (MC) register is used by the host to enable the receive and transmit DMAs as well as to control their PCI bus bursting attributes and select which port the BERT is dedicated to.
DS3131 Bit 6/PCI Bus Orientation (PBO). This bit selects whether HDLC packet data on the PCI bus operates in either Little Endian or Big Endian format. Little Endian byte ordering places the least significant byte at the lowest address while Big Endian places the least significant byte at the highest address. This bit setting only affects HDLC data on the PCI bus.
DS3131 5.3 Status and Interrupt 5.3.1 General Description of Operation There are two status registers in the device, status master (SM) and status for DMA (SDMA). Both registers report events in real-time as they occur by setting a bit within the register to 1. Each bit has the ability to generate an interrupt at the PCI bus through the PINTA output signal pin and if the local bus is in the configuration mode, then an interrupt also be created at the LINT output signal pin.
DS3131 Figure 5-1.
DS3131 5.3.2 Status and Interrupt Register Description Register Name: Register Description: Register Address: SM Status Master Register 0020h Bit # Name Default 7 reserved 0 6 reserved 0 5 reserved 0 4 PPERR 0 3 PSERR 0 2 SBERT 0 1 reserved 0 0 reserved 0 Bit # Name Default 15 LBINT 0 14 LBE 0 13 reserved 0 12 reserved 0 11 reserved 0 10 reserved 0 9 reserved 0 8 reserved 0 Note: Bits that are underlined are read-only; all other bits are read-write.
DS3131 Register Name: Register Description: Register Address: ISM Interrupt Mask Register for SM 0024h Bit # Name Default 7 reserved 0 6 reserved 0 5 reserved 0 4 PPERR 0 3 PSERR 0 2 SBERT 0 1 reserved 0 0 reserved 0 Bit # Name Default 15 LBINT 0 14 LBE 0 13 reserved 0 12 reserved 0 11 reserved 0 10 reserved 0 9 reserved 0 8 reserved 0 Note: Bits that are underlined are read-only; all other bits are read-write.
DS3131 Bit 3/Status Bit for Receive HDLC Abort Detected (RABRT). This status bit is set to 1 if any of the receive HDLC channels detects an abort. The RABRT bit is cleared when read and is not set again until another abort has been detected. If enabled through the RABRT bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode.
DS3131 for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode. Bit 11/Status Bit for Receive DMA Done-Queue Write Error (RDQWE). This status bit is set to 1 each time the receive DMA tries to write to the done queue and it is full. The RDQWE bit is cleared when read and is not set again until another write to the done queue detects that it is full.
DS3131 Register Name: Register Description: Register Address: ISDMA Interrupt Mask Register for SDMA 002Ch Bit # Name Default 7 RLBRE 0 6 RLBR 0 5 ROVFL 0 4 RLENC 0 3 RABRT 0 2 RCRCE 0 1 reserved 0 0 reserved 0 Bit # Name Default 15 TDQWE 0 14 TDQW 0 13 TPQR 0 12 TUDFL 0 11 RDQWE 0 10 RDQW 0 9 RSBRE 0 8 RSBR 0 Note: Bits that are underlined are read-only; all other bits are read-write.
DS3131 Bit 13/Status Bit for Transmit DMA Pending-Queue Read (TPQR) 0 = interrupt masked 1 = interrupt unmasked Bit 14/Status Bit for Transmit DMA Done-Queue Write (TDQW) 0 = interrupt masked 1 = interrupt unmasked Bit 15/Status Bit for Transmit DMA Done-Queue Write Error (TDQWE) 0 = interrupt masked 1 = interrupt unmasked 5.
DS3131 6. LAYER 1 6.1 General Description Each port on the DS3131 contains a dedicated bit-synchronous HDLC controller for that port. The Layer 1 block diagram in Figure 6-1 provides a block level description of the Layer 1 circuitry on each port. Depending on the configuration, the DS3131 can have either 28 or 40 bit-synchronous HDLC interfaces (Table 6-B). Figure 2-2 details the configurations shown in Table 6-B. Each of the 40 ports can be independently configured into a different mode.
DS3131 Figure 6-1.
DS3131 6.2 Port Register Descriptions Receive Side Control Bits (one each for all 40 ports) Register Name: Register Description: Register Address: RP[n]CR, where n = 0 to 39 for each port Receive Port [n] Control Register See the Register Map in Section 4.
DS3131 Transmit Side Control Bits (one each for all 40 ports) Register Name: Register Description: Register Address: TP[n]CR, where n = 0 to 39 for each port Transmit Port [n] Control Register See the Register Map in Section 4.
DS3131 6.3 BERT The BERT block is capable of generating and detecting the following patterns: The pseudorandom patterns 2E7, 2E11, 2E15, and QRSS A repetitive pattern from 1 to 32 bits in length Alternating (16-bit) words which flip every 1 to 256 words The BERT receiver has a 32-bit bit counter and a 24-bit error counter. It can generate interrupts upon detecting a bit error, a change in synchronization, or if an overflow occurs in the bit and error counters.
DS3131 6.4 BERT Register Description Figure 6-3.
DS3131 Register Name: Register Description: Register Address: BERTC0 BERT Control Register 0 0500h Bit # Name Default 7 reserved 0 6 TINV 0 5 RINV 0 4 PS2 0 3 PS1 0 2 PS0 0 1 LC 0 0 RESYNC 0 Bit # Name Default 15 IESYNC 0 14 IEBED 0 13 IEOF 0 12 reserved 0 11 RPL3 0 10 RPL2 0 9 RPL1 0 8 RPL0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/Force Resynchronization (RESYNC).
DS3131 Repetitive Pattern Length Map Length 17 Bits 21 Bits 25 Bits 29 Bits Code 0000 0100 1000 1100 Length 18 Bits 22 Bits 26 Bits 30 Bits Code 0001 0101 1001 1101 Length 19 Bits 23 Bits 27 Bits 31 Bits Code 0010 0110 1010 1101 Length 20 Bits 24 Bits 28 Bits 32 Bits Code 0011 0111 1011 1111 Bit 13/Interrupt Enable for Counter Overflow (IEOF). Allows the receive BERT to cause an interrupt if either the bit counter or the error counter overflows.
DS3131 Register Name: Register Description: Register Address: BERTC1 BERT Control Register 1 0504h Bit # Name Default 7 EIB2 6 EIB1 5 EIB0 4 SBE 3 reserved 2 reserved 1 reserved 0 TC 0 0 0 0 0 0 0 0 Bit # Name Default 15 14 13 10 9 8 0 0 0 0 0 0 12 11 Alternating Word Count 0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/Transmit Pattern Load (TC).
DS3131 Register Name: Register Description: Register Address: BERTBRP0 BERT Repetitive Pattern Set 0 0508h Register Name: Register Description: Register Address: BERTBRP1 BERT Repetitive Pattern Set 1 050Ch BERTRP0: BERT Repetitive Pattern Set 0 (lower word) Bit # 7 6 5 4 3 2 Name BERT Repetitive Pattern Set (lower byte) Default 0 0 0 0 0 0 Bit # Name Default 1 0 0 0 10 9 8 0 0 0 18 17 16 0 0 0 29 28 27 26 Bert Repetitive Pattern Set (upper byte) 0 0 0 0 25 24 0 0 15 14 13 0 0
DS3131 Register Name: Register Description: Register Address: BERTBC0 BERT 32-Bit Bit Counter (lower word) 0510h Register Name: Register Description: Register Address: BERTBC1 BERT 32-Bit Bit Counter (upper word) 0514h BERTBC0: BERT Bit Counter 0 (lower word) Bit # 7 6 5 4 3 2 Name BERT 32-Bit Bit Counter (lower byte) Default 0 0 0 0 0 0 Bit # Name Default 15 14 13 0 0 0 12 11 BERT 32-Bit Bit Counter 0 0 1 0 0 0 10 9 8 0 0 0 18 17 16 BERTBC1: BERT Bit Counter 0 (upper word) Bit # N
DS3131 Bit 1/BERT Error Counter Overflow (BECO). A latched bit that is set when the 24-bit BERT error counter (BEC) overflows. Cleared when read and is not set again until another overflow occurs. Bit 2/BERT Bit Counter Overflow (BBCO). A latched bit that is set when the 32-bit BERT bit counter (BBC) overflows. Cleared when read and is not set again until another overflow occurs. Bit 3/Bit Error Detected (BED). A latched bit that is set when a bit error is detected.
DS3131 7. HDLC 7.1 General Description Each port on the DS3131 has a dedicated bit-synchronous HDLC controller that can operate up to 52Mbps. See Figure 2-2 and Figure 6-1. HDLC channel numbers are assigned as shown below in Table 7-A. Table 7-A. HDLC Channel Assignment PORT NUMBER 0 1 2 3 4 ... 37 38 39 HDLC CHANNEL NUMBER 1 2 3 4 5 ... 38 39 40 7.2 HDLC Operation The HDLC controllers can handle all normal real-time tasks required.
DS3131 Table 7-B.
DS3131 Table 7-D. Transmit Bit-Synchronous HDLC Functions Zero Stuffing Interfill Selection Flag Generation CRC Generation Invert Data Bit Flip Transparent Mode Invert FCS Only used between opening and closing flags. Is disabled in between a closing flag and an opening flag and for sending aborts and/or interfill data. Disabled if the channel is set to the transparent mode. Can be either 7Eh or FFh. A programmable number of flags (1 to 16) can be set between packets.
DS3131 Bit 1/Receive Maximum Octet Length-Detection Enable (ROLD). When this bit is set low, the HDLC controller does not check to see if the octet length of the received packets exceeds the count loaded into the receive HDLC packet length (RHPL) register. When this bit is set high, the HDLC controller checks to see if the octet length of the received packets exceeds the count loaded into the RHPL register.
DS3131 Register Name: Register Description: Register Address: RHPL Receive HDLC Maximum Packet Length 03A0h Bit # Name Default 7 RHPL7 0 6 RHPL6 0 5 RHPL5 0 4 RHPL4 0 3 RHPL3 0 2 RHPL2 0 1 RHPL1 0 0 RHPL0 0 Bit # Name Default 15 RHPL15 0 14 RHPL14 0 13 RHPL13 0 12 RHPL12 0 11 RHPL11 0 10 RHPL10 0 9 RHPL9 0 8 RHPL8 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 15/Receive Bit-Synchronous HDLC Maximum Packet Length (RHPL0 to RHPL15).
DS3131 Bit 4/Transmit Invert Data Enable (TID). When this bit is set low, the outgoing HDLC packets are not inverted after being generated. When this bit is set high, the HDLC controller inverts all the data (flags, information fields, and FCS) after the packet has been generated. 0 = do not invert data 1 = invert all data (including flags and FCS) Bit 5/Transmit Bit Flip (TBF).
DS3131 8. FIFO 8.1 General Description and Example The BoSS contains one 8kB FIFO for the receive path and another 8kB FIFO for the transmit path. Both of these FIFOs are organized into blocks. Since a block is defined as 4 dwords (16 Bytes), each FIFO is made up of 512 blocks. Figure 8-1 shows an FIFO example. The FIFO contains a state machine that is constantly polling the 40 ports to determine if any data is ready for transfer to/from the FIFO from/to the HDLC engines.
DS3131 block pointer. The block pointer RAM tells the device how to link the eight blocks together to form a circular chain. The host must set the watermarks for the receive and transmit paths. The receive path has a high watermark and the transmit path has a low watermark. Figure 8-1.
DS3131 8.1.1 Receive High Watermark The high watermark tells the device how many blocks should be written into the receive FIFO by the HDLC controllers before the DMA begins sending the data to the PCI bus, or rather, how full the FIFO should get before it should be emptied by the DMA. When the DMA begins reading the data from the FIFO, it reads all available data and tries to completely empty the FIFO even if one or more EOFs (end of frames) are detected.
DS3131 8.2 FIFO Register Description Register Name: Register Description: Register Address: RFSBPIS Receive FIFO Starting Block Pointer Indirect Select 0900h Bit # Name Default 7 reserved 0 6 reserved 0 5 HCID5 0 4 HCID4 0 3 HCID3 0 2 HCID2 0 1 HCID1 0 0 HCID0 0 Bit # Name Default 15 IAB 0 14 IARW 0 13 reserved 0 12 reserved 0 11 reserved 0 10 reserved 0 9 reserved 0 8 reserved 0 Note: Bits that are underlined are read-only; all other bits are read-write.
DS3131 Register Name: Register Description: Register Address: RFBPIS Receive FIFO Block Pointer Indirect Select 0910h Bit # Name Default 7 BLKID7 0 6 BLKID6 0 5 BLKID5 0 4 BLKID4 0 3 BLKID3 0 2 BLKID2 0 1 BLKID1 0 0 BLKID0 0 Bit # Name Default 15 IAB 0 14 IARW 0 13 reserved 0 12 reserved 0 11 reserved 0 10 reserved 0 9 reserved 0 8 BLKID8 0 Note: Bits that are underlined are read-only; all other bits are read-write.
DS3131 Register Name: Register Description: Register Address: RFHWMIS Receive FIFO High-Watermark Indirect Select 0920h Bit # Name Default 7 reserved 0 6 reserved 0 5 HCID5 0 4 HCID4 0 3 HCID3 0 2 HCID2 0 1 HCID1 0 0 HCID0 0 Bit # Name Default 15 IAB 14 IARW 0 13 reserved 0 12 reserved 0 11 reserved 0 10 reserved 0 9 reserved 0 8 reserved 0 Note: Bits that are underlined are read-only; all other bits are read-write.
DS3131 Register Name: Register Description: Register Address: TFSBPIS Transmit FIFO Starting Block Pointer Indirect Select 0980h Bit # Name Default 7 reserved 0 6 reserved 0 5 HCID5 0 4 HCID4 0 3 HCID3 0 2 HCID2 0 1 HCID1 0 0 HCID0 0 Bit # Name Default 15 IAB 0 14 IARW 0 13 reserved 0 12 reserved 0 11 reserved 0 10 reserved 0 9 reserved 0 8 reserved 0 Note: Bits that are underlined are read-only; all other bits are read-write.
DS3131 Register Name: Register Description: Register Address: TFBPIS Transmit FIFO Block Pointer Indirect Select 0990h Bit # Name Default 7 BLKID7 0 6 BLKID6 0 5 BLKID5 0 4 BLKID4 0 3 BLKID3 0 2 BLKID2 0 1 BLKID1 0 0 BLKID0 0 Bit # Name Default 15 IAB 0 14 IARW 0 13 reserved 0 12 reserved 0 11 reserved 0 10 reserved 0 9 reserved 0 8 BLKID8 0 Note: Bits that are underlined are read-only; all other bits are read-write.
DS3131 Register Name: Register Description: Register Address: TFLWMIS Transmit FIFO Low-Watermark Indirect Select 09A0h Bit # Name Default 7 reserved 0 6 reserved 0 5 HCID5 0 4 HCID4 0 3 HCID3 0 2 HCID2 0 1 HCID1 0 0 HCID0 0 Bit # Name Default 15 IAB 0 14 IARW 0 13 reserved 0 12 reserved 0 11 reserved 0 10 reserved 0 9 reserved 0 8 reserved 0 Note: Bits that are underlined are read-only, all other bits are read-write.
DS3131 9. DMA 9.1 Introduction The DMA block (Figure 2-1) handles the transfer of packet data from the FIFO block to the PCI block and vice versa. Throughout this section, the terms host and descriptor are used. Host is defined as the CPU or intelligent controller that sits on the PCI bus and instructs the device how to handle the incoming and outgoing packet data.
DS3131 Table 9-A.
DS3131 9.2 Receive Side 9.2.1 Overview The receive DMA uses a scatter-gather technique to write packet data into main memory. The host keeps track of and decides where the DMA should place the incoming packet data. There are a set of descriptors that get handed back and forth between the DMA and the host. Through these descriptors the host can inform the DMA where to place the packet data and the DMA can tell the host when the data is ready to be processed.
DS3131 On an HDLC channel basis in the receive DMA configuration RAM, the host instructs the DMA how to use the large and small buffers for the incoming packet data on that particular HDLC channel. The host has three options: (1) only use large buffers, (2) only use small buffers, or (3) first fill a small buffer, then if the incoming packet requires more buffer space, use one or more large buffers for the remainder of the packet.
DS3131 Host Actions The host typically handles the receive DMA as follows: 1) The host is always trying to make free data buffer space available and therefore tries to fill the freequeue descriptor. 2) The host either polls, or is interrupted, when some incoming packet data is ready for processing. 3) The host then reads the done-queue descriptor circular queue to find out which channel has data available, what the status is, and where the receive packet descriptor is located.
DS3131 Figure 9-2.
DS3131 9.2.2 Packet Descriptors A contiguous section up to 65,536 quad dwords that make up the receive packet descriptors resides in main memory. The receive packet descriptors are aligned on a quad dword basis and can be placed anywhere in the 32-bit address space through the receive descriptor base address (Table 9-C). A data buffer is associated with each descriptor. The data buffer can be up to 8191 Bytes long and must be a contiguous section of main memory.
DS3131 Figure 9-4. Receive Packet Descriptors dword 0 Data Buffer Address (32) dword 1 BUFS (3) dword 2 Byte Count (13) Next Descriptor Pointer (16) Timestamp (24) 00b HDLC CH#(6) dword 3 unused (32) Note: The organization of the receive descriptor is not affected by the enabling of Big Endian. dword 0; Bits 0 to 31/Data Buffer Address. Direct 32-bit starting address of the data buffer that is associated with this receives descriptor. dword 1; Bits 0 to 15/Next Descriptor Pointer.
DS3131 9.2.3 Free Queue The host writes the 32-bit addresses of the available (free) data buffers and their associated packet descriptors to the receive free queue. The descriptor space is indicated through a 16-bit pointer, which the DMA uses along with the receive packet descriptor base address to find the exact 32-bit address of the associated receive packet descriptor. Figure 9-5.
DS3131 Empty Case The receive free queue is considered empty when the read and write pointers are identical. Receive Free-Queue Empty State read pointer > empty descriptor empty descriptor empty descriptor empty descriptor empty descriptor empty descriptor empty descriptor < write pointer Full Case The receive free queue is considered full when the read pointer is ahead of the write pointer by one descriptor. Therefore, one descriptor must always remain empty.
DS3131 Figure 9-6.
DS3131 Status/Interrupts On each read of the free queue by the DMA, the DMA sets either the status bit for receive DMA large buffer read (RLBR) or the status bit for receive DMA small buffer read (RSBR) in the status register for DMA (SDMA). The DMA also checks the receive free-queue large-buffer host write pointer and the receive free-queue small-buffer host write pointer to ensure that an underflow does not occur.
DS3131 Register Name: Register Description: Register Address: RDMAQ Receive DMA Queues Control 0780h Bit # Name Default 7 reserved 0 6 reserved 0 5 RDQF 0 4 RDQFE 0 3 RFQSF 0 2 RFQLF 0 1 reserved 0 0 RFQFE 0 Bit # Name Default 15 reserved 0 14 reserved 0 13 reserved 0 12 reserved 0 11 reserved 0 10 RDQT2 0 9 RDQT1 0 8 RDQT0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/Receive Free-Queue FIFO Enable (RFQFE).
DS3131 9.2.4 Done Queue The DMA writes to the receive done queue when it has filled a free data buffer with packet data and has loaded the associated packet descriptor with all the necessary information. The descriptor location is indicated through a 16-bit pointer that the host uses with the receive descriptor base address to find the exact 32-bit address of the associated receive descriptor. Figure 9-7.
DS3131 The host reads from the receive done queue to find which data buffers and their associated descriptors are ready for processing. The receive done queue is circular. A set of internal addresses within the device that are accessed by the host and the DMA keep track of the queue’s addresses. On initialization, the host configures all of the registers, as shown in Table 9-F. After initialization, the DMA only writes to (changes) the write pointer and the host only writes to the read pointer.
DS3131 Figure 9-8.
DS3131 Buffer Write Threshold Setting In the DMA configuration RAM (Section 9.2.5), there is a host-controlled field called “threshold” (bits RDT0 to RDT2) that informs the DMA when it should write to the done queue. The host has the option to have the DMA place information in the done queue after a programmable number (from 1 to 7) data buffers have been filled or wait until the completed packet data has been written.
DS3131 Register Name: Register Description: Register Address: RDQFFT Receive Done-Queue FIFO Flush Timer 0744h Bit # Name Default 7 TC7 0 6 TC6 0 5 TC5 0 4 TC4 0 3 TC3 0 2 TC2 0 1 TC1 0 0 TC0 0 Bit # Name Default 15 TC15 0 14 TC14 0 13 TC13 0 12 TC12 0 11 TC11 0 10 TC10 0 9 TC9 0 8 TC8 0 Note: Bits that are underlined are read-only, all other bits are read-write. Bits 0 to 15/Receive Done-Queue FIFO Flush Timer Control Bits (TC0 to TC15).
DS3131 Bit 5/Receive Done-Queue FIFO Flush (RDQF). When this bit is set to 1, the internal done-queue FIFO is flushed by sending all data into the done queue. This bit must be set to 0 for proper operation. 0 = FIFO in normal operation 1 = FIFO is flushed Bits 8 to 10/Receive Done-Queue Status-Bit Threshold Setting (RDQT0 to RDQT2). These bits determine when the DMA sets the receive DMA done-queue write (RDQW) status bit in the status register for DMA (SDMA) register.
DS3131 9.2.5 DMA Configuration RAM There is a set of 120 dwords (3 dwords per channel times 40 channels) on-board the device that the host uses to configure the DMA. It uses the DMA to store values locally when it is processing a packet. Most of the fields within the DMA configuration RAM are for DMA use and the host never writes to these fields. The host is only allowed to write (configure) to the lower word of dword 2 for each HDLC channel.
DS3131 - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 0; Bits 0 to 31/Current Data Buffer Address. The current 32-bit address of the data buffer that is being used. This address is used by the DMA to keep track of where data should be written to as it comes in from the receive FIFO. - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 1; Bits 0 to 15/Current Descriptor Pointer.
DS3131 - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 2; Bits 10 to 14/DMA Reserved. Could be any value when read. Should be set to 0 when written to by the host. - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 2; Bit 15/First Buffer Fill (FBF). This bit is set to 1 by the receive DMA when it is in the process of filling the first buffer of a packet. The DMA uses this bit to determine when to switch to large buffers when the buffer size-select field is set to 10.
DS3131 Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal receive DMA configuration RAM, this bit should be written to 1 by the host. This causes the device to begin obtaining the data from the channel location indicated by the HCID bits. During the read access, the IAB bit is set to 1. Once the data is ready to be read from the RDMAC register, the IAB bit is set to 0.
DS3131 9.3 Transmit Side 9.3.1 Overview The transmit DMA uses a scatter-gather technique to read packet data from main memory. The host keeps track of and decides from where (and when) the DMA should grab the outgoing packet data. A set of descriptors that get handed back and forth between the host and the DMA tells the DMA where to obtain the packet data, and the DMA can tell the host when the data has been transmitted.
DS3131 Host Linking of Packets (Packet Chaining) The host also has the option to link multiple packets together in a chain. Through the chain valid (CV) bit in the packet descriptor, the host can inform the transmit DMA that the next descriptor pointer field contains the descriptor of another HDLC packet that is ready for transmission. The transmit DMA ignores the CV bit until it sees EOF = 1, which indicates the end of a packet.
DS3131 Figure 9-10. Transmit DMA Operation EOF = 1 Data Buffer Address EOF CV # Bytes Next Desc. Ptr. unused CH #5 unused PV Next Pend. Desc. Done-Queue Descriptors (circular queue) 00h Status CH#5 Free Desc. Ptr. 04h Status CH#1 Free Desc. Ptr. 08h Status CH# Free Desc. Ptr. 0Ch Status CH# Free Desc. Ptr. 10h Status CH# Free Desc. Ptr. 14h Status CH# Free Desc. Ptr. EOF = 0 Data Buffer Address EOF CV # Bytes Next Desc. Ptr. unused CH #1 unused PV Next Pend. Desc.
DS3131 Figure 9-11.
DS3131 Figure 9-12.
DS3131 Figure 9-13.
DS3131 DMA Updates to the Done Queue The host has two options for when the transmit DMA should write descriptors that have completed transmission to the done queue. On a channel-by-channel basis, through the done-queue select (DQS) bit in the transmit DMA configuration RAM, the host can condition the DMA to: 1) Write to the done queue only when the complete HDLC packet has been transmitted (DQS = 0). 2) Write to the done queue when each data buffer has been transmitted (DQS = 1).
DS3131 descriptor pointer and PV fields in the packet descriptor to 0 to ready them for transmission). The second option allows the software a cleaner error-recovery technique. See Figure 9-14 for more details. Figure 9-14.
DS3131 9.3.2 Packet Descriptors A contiguous section of up to 65,536 quad dwords that make up the transmit packet descriptors resides in main memory. The transmit packet descriptors are aligned on a quad-dword basis and can be placed anywhere in the 32-bit address space through the transmit descriptor base address (Table 9-I). A data buffer is associated with each descriptor. The data buffer can be up to 8191 Bytes long and must be a contiguous section of main memory.
DS3131 Figure 9-16. Transmit Packet Descriptors dword 0 Data Buffer Address (32) dword 1 EOF dword 2 CV unused Byte Count (13) unused (26) Next Descriptor Pointer (16) HDLC CH# (6) dword 3 unused (15) PV Next Pending Descriptor Pointer (16) Note 1: The organization of the transmit descriptor is not affected by the enabling of Big Endian.
DS3131 9.3.3 Pending Queue The host writes to the transmit pending queue the location of the readied descriptor, channel number, and control information. The descriptor space is indicated through a 16-bit pointer, which the DMA uses with the transmit packet-descriptor base address to find the exact 32-bit address of the associated transmit packet descriptor. Figure 9-17.
DS3131 The transmit DMA reads from the transmit pending-queue descriptor circular queue which data buffers and their associated descriptors are ready for transmission. A set of internal addresses within the device that are accessed by both the host and the DMA keep track of the circular queue addresses in the transmit pending queue. On initialization, the host configures all of the registers shown in Table 9-J.
DS3131 Figure 9-18.
DS3131 Register Name: Register Description: Register Address: TDMAQ Transmit DMA Queues Control 0880h Bit # Name Default 7 reserved 0 6 reserved 0 5 reserved 0 4 reserved 0 3 TDQF 0 2 TDQFE 0 1 TPQF 0 0 TPQFE 0 Bit # Name Default 15 reserved 0 14 reserved 0 13 reserved 0 12 reserved 0 11 reserved 0 10 TDQT2 0 9 TDQT1 0 8 TDQT0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/Transmit Pending-Queue FIFO Enable (TPQFE).
DS3131 9.3.4 Done Queue The DMA writes to the transmit done queue when it has finished either transmitting a complete packet chain or a complete data buffer. This option is selected by the host when it configures the DQS field in the transmit DMA configuration RAM (Section 9.3.5). The descriptor location is indicated in the done queue through a 16-bit pointer that the host uses along with the transmit descriptor base address to find the exact 32-bit address of the associated transmit descriptor.
DS3131 The host reads from the transmit done queue to find which data buffers and their associated descriptors have completed transmission. The transmit done queue is circular queue. A set of internal addresses within the device that are accessed by both the host and the DMA keep track of the circular queue addresses in the transmit done queue. On initialization, the host configures all of the registers, as shown in Table 9-K.
DS3131 Figure 9-20.
DS3131 Done-Queue FIFO Flush Timer To ensure the done-queue FIFO gets flushed to the done queue on a regular basis, the transmit donequeue FIFO flush timer (TDQFFT) is used by the DMA to determine the maximum wait time in between writes. The TDQFFT is a 16-bit programmable counter that is decremented every PCLK divided by 256. It is only monitored by the DMA when the transmit done-queue FIFO is enabled (TDQFE = 1). For a 33MHz PCLK, the timer is decremented every 7.76µs.
DS3131 Register Name: Register Description: Register Address: TDMAQ Transmit DMA Queues Control 0880h Bit # Name Default 7 reserved 0 6 reserved 0 5 reserved 0 4 reserved 0 3 TDQF 0 2 TDQFE 0 1 TPQF 0 0 TPQFE 0 Bit # Name Default 15 reserved 0 14 reserved 0 13 reserved 0 12 reserved 0 11 reserved 0 10 TDQT2 0 9 TDQT1 0 8 TDQT0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/Transmit Pending-Queue FIFO Enable (TPQFE). See Section 9.3.3 for details.
DS3131 9.3.5 DMA Configuration RAM The device contains an on-board set of 240 dwords (6 dwords per channel times 40 channels) that are used by the host to configure the DMA and used by the DMA to store values locally when it is processing a packet. Most of the fields within the DMA configuration RAM are for DMA use and the host never writes to these fields. The host is only allowed to write (configure) to the lower word of dword 1 for each HDLC channel.
DS3131 - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 0; Bits 0 to 31/Current Data Buffer Address. This is the current 32-bit address of the data buffer that is being used. This address is used by the DMA to keep track of where data should be read from as it is passed to the transmit FIFO. - HOST MUST CONFIGURE dword 1; Bit 0/Channel Enable (CHEN). This bit is controlled by both the host and the transmit DMA to enable and disable a HDLC channel.
DS3131 - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 1; Bits 20 to 21/Priority State (PRIST). This field is used by the transmit DMA to keep track of queued priority descriptors as they arrive from the pending queue, and for the DMA to know when it should create a horizontal linked list of transmit priority descriptors and where it can find the next valid priority descriptor. This field handles priority packets and the PENDST field handles standard packets.
DS3131 - FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD dword 5; Bits 16 to 31/Next Priority Pending Descriptor Pointer. This 16-bit value is the offset from the transmit descriptor base address of the first transmit priority packet descriptor for the packet priority that is queued up next for transmission.
DS3131 Register Name: Register Description: Register Address: TDMAC Transmit DMA Configuration 0874h Bit # Name Default 7 D7 0 6 D6 0 5 D5 0 4 D4 0 3 D3 0 2 D2 0 1 D1 0 0 D0 0 Bit # Name Default 15 D15 0 14 D14 0 13 D13 0 12 D12 0 11 D11 0 10 D10 0 9 D9 0 8 D8 0 Note: Bits that are underlined are read-only, all other bits are read-write. Bits 0 to 15/Transmit DMA Configuration RAM Data (D0 to D15). Data that is written to or read from the transmit DMA configuration RAM.
DS3131 10. PCI BUS 10.1 General Description of Operation The PCI block interfaces the DMA block to an external high-speed bus. The PCI block complies with Revision 2.1 (June 1, 1995) of the PCI Local Bus Specification. HDLC packet data always passes to and from the BoSS through the PCI bus. The user has the option to configure and monitor the internal device registers either through the PCI bus (local bus bridge mode) or through the local bus (local bus configuration mode).
DS3131 10.1.1 PCI Read Cycle A read cycle on the PCI bus is shown in Figure 10-2. During clock cycle #1, the initiator asserts the PFRAME signal and drives the address onto the PAD signal lines and the bus command (which would be a read) onto the PCBE signal lines. The target reads the address and bus command and, if the address matches its own, it then asserts the PDEVSEL signal and begins the bus transaction.
DS3131 10.1.2 PCI Write Cycle A write cycle on the PCI bus is shown in Figure 10-3. During clock cycle #1, the initiator asserts the PFRAME signal and drives the address onto the PAD signal lines and the bus command (which would be a write) onto the PCBE signal lines. The target reads the address and bus command and, if the address matches its own, it then asserts the PDEVSEL signal and begins the bus transaction.
DS3131 10.1.3 PCI Bus Arbitration The PCI bus can be arbitrated as shown in Figure 10-4. The initiator requests bus access by asserting PREQ. A central arbiter grants the access some time later by asserting PGNT. Once the bus has been granted, the initiator waits until both PIRDY and PFRAME are deasserted (i.e., an idle cycle) before acquiring the bus and beginning the transaction.
DS3131 10.1.5 PCI Target Retry Targets can terminate the requested bus transaction before any data is transferred because the target is busy and temporarily unable to process the transaction. Such a termination is called a target retry and no data is transferred. A target retry is signaled to the initiator by the assertion of PSTOP and not asserting PTRDY on the initial data phase (Figure 10-6). When BoSS is a target, it only issues a target retry when the host is accessing the local bus.
DS3131 10.1.7 PCI Target Abort Targets can also abort the current transaction, which means they do not wish for the initiator to attempt the request again. No data is transferred in a target abort scenario. A target abort is signaled to the initiator by the simultaneous assertion of PSTOP and deassertion of PDEVSEL (Figure 10-8). When BoSS is a target, it only issues a target abort when the host is accessing the local bus.
DS3131 10.1.8 PCI Fast Back-to-Back Fast back-to-back transactions are two consecutive bus transactions without the usually required idle cycle (PFRAME and PIRDY deasserted) between them. This can only occur when there is a guarantee that there is not any contention on the signal lines. The PCI specification allows two types of fast backto-back transactions—those that access the same agent (Type 1) and those that do not (Type 2).
DS3131 10.2 PCI Configuration Register Description PVID0 PCI Vendor ID/Device ID Register 0 0x000h Register Name: Register Description: Register Address: LSB Vendor ID (Read Only/Set to EAh) Vendor ID (Read Only/Set to 13h) Device ID (Read Only/Set to 31h) MSB Device ID (Read Only/Set to 31h) Bits 0 to 15/Vendor ID. These read-only bits identify Dallas Semiconductor as the device’s manufacturer. The vendor ID was assigned by the PCI Special Interest Group and is fixed at 13EAh. Bits 16 to 31/Device ID.
DS3131 10.2.1 Command Bits (PCMD0) Bit 0/I/O Space Control (IOC). This read-only bit is forced to 0 by the device to indicate that it does not respond to I/O space accesses. Bit 1/Memory Space Control (MSC). This read/write bit controls whether or not the device responds to accesses by the PCI bus to the memory space, which are the internal device configuration registers. When this bit is set to 0, the device ignores accesses attempted to the internal configuration registers.
DS3131 10.2.2 Status Bits (PCMD0) The upper words in the PCMD0 register are the status portion, which report events as they occur. As previously mentioned, reads of the status portion occur normally but writes are unique in that bits can only be reset (i.e., forced to 0). This occurs when 1 is written to a bit position. Writes with a 0 to a bit position have no affect. This allows individual bits to be reset. Bits 16 to 20/Reserved. These read-only bits are forced to 0 by the device.
DS3131 Register Name: Register Description: Register Address: PRCC0 PCI Revision ID/Class Code Register 0 0x008h LSB Revision ID (Read Only/Set to 00h) Class Code (Read Only/Set to 00h) Class Code (Read Only/Set to 80h) MSB Class Code (Read Only/Set to 02h) Bits 0 to 7/Revision ID. These read-only bits identify the specific device revision, which is selected by Dallas Semiconductor. Bits 8 to 15/Class Code Interface.
DS3131 Register Name: Register Description: Register Address: PDCM PCI Device Configuration Memory Base Address Register 0x010h Base Address (Read Only/Set to 0h) TYPE1 PF Base Address TYPE0 LSB MSI Base Address (Read Only/Set to 0h) Base Address MSB Base Address Note: Read-only bits in the PDCM register are underlined; all other bits are read-write. Bit 0/Memory Space Indicator (MSI).
DS3131 Register Name: Register Description: Register Address: PVID1 PCI Vendor ID/Device ID Register 1 0x100h LSB Vendor ID (Read Only/Set to EAh) Vendor ID (Read Only/Set to 13h) Device ID (Read Only/Set to 31h) MSB Device ID (Read Only/Set to 31h) Bits 0 to 15/Vendor ID. These read-only bits identify Dallas Semiconductor as the manufacturer of the device. The vendor ID was assigned by the PCI Special Interest Group and is fixed at 13EAh. Bits 16 to 31/Device ID.
DS3131 10.2.3 Command Bits (PCMD1) Bit 0/I/O Space Control (IOC). This read-only bit is forced to 0 by the device to indicate that it does not respond to I/O space accesses. Bit 1/Memory Space Control (MSC). This read/write bit controls whether or not the device responds to accesses by the PCI bus to the memory space, which is the local bus. When this bit is set to 0, the device ignores accesses attempted to the local bus. When set to 1, the device allows accesses to the local bus.
DS3131 10.2.4 Status Bits (PCMD1) The upper words in the PCMD1 register are the status portion, which report events as they occur. As mentioned earlier, reads of the status portion occur normally, but writes are unique in that bits can only be reset (i.e., forced to 0). This occurs when 1 is written to a bit position. Writes with a 0 to a bit position have no affect. This allows individual bits to be reset. Bits 16 to 20/Reserved. These read-only bits are forced to 0 by the device.
DS3131 Register Name: Register Description: Register Address: PRCC1 PCI Revision ID/Class Code Register 1 0x108h LSB Revision ID (Read Only/Set to 00h) Class Code (Read Only/Set to 00h) Class Code (Read Only/Set to 80h) MSB Class Code (Read Only/Set to 06h) Bits 0 to 7/Revision ID. These read-only bits identify the specific device revision, selected by Dallas Semiconductor. Bits 8 to 15/Class Code Interface. These read-only bits identify the subclass interface value for the device and are fixed at 00h.
DS3131 Register Name: Register Description: Register Address: PLBM PCI Local Bus Memory Base Address Register 0x110h LSB Base Address (Read Only/Set to 0h) PF TYPE1 Base Address TYPE0 MSI Base Address (Read Only/Set to 0h) Base Address MSB Base Address Note: Read-only bits in the PLBM register are underlined; all other bits are read-write. Bit 0/Memory Space Indicator (MSI). This read-only bit is forced to 0 to indicate that the local bus is mapped to memory space. Bits 1 and 2/Type 0 and Type 1.
DS3131 11. LOCAL BUS 11.1 General Description The DS3131’s local bus can be either enabled or disabled. When it is disabled, the device uses the local bus signals to connect to bit-synchronous HDLC controllers on ports 28 to 39 (HDLC channels 29 to 40). The local bus is enabled and disabled through a hardware control signal called LBPXS. The local bus is enabled when LBPXS is left open-circuited (or connected high). It is disabled when LBPXS is connected low.
DS3131 Figure 11-1. Bridge Mode xDSL Transceiver DS3131 BOSS PCI / Custom Bus XDSL Transceiver Host Processor and Main Memory xDSL Transceiver xDSL Transceiver blb_cfga Local Bus Figure 11-2. Bridge Mode with Arbitration Enabled xDSL Transceiver PCI / Custom Bus DS3131 BOSS xDSL Transceiver xDSL Transceiver 1 2 xDSL Transceiver 3 1. Request Bus Access 2. Bus Access Granted 3.
DS3131 Figure 11-3.
DS3131 11.1.1 PCI Bridge Mode In the PCI bridge mode, data from the PCI bus can be transferred to the local bus. The local bus acts as a “master” and creates all the necessary signals to control the bus. The user must configure the local bus bridge mode control register (LBBMC), which is described in Section 11.2. With 20 address lines, the local bus can address 1MB address space.
DS3131 If the local bus is used as 16-bit bus, then the LBW control bit must be set to 0. In 16-bit accesses, the host can either perform a 16-bit access or an 8-bit access by asserting the appropriate PCBE signals (see Table 11-C). For 16-bit access, the host enables the combination of either PCBE0/PCBE1 or PCBE2/PCBE3 and the local bus block maps the word from/to the PCI bus to/from the LD[15:0] signals. For 8-bit access in the 16-bit bus mode, the host must assert just one of the PCBE0 to PCBE3 signals.
DS3131 Bridge Mode Interrupt In the PCI bridge mode, the local bus can detect an external interrupt through the LINT signal. If the local bus detects that the LINTA signal has been asserted, it then sets the LBINT status bit in the status master (SM) register. Setting this status bit can cause a hardware interrupt to occur at the PCI bus through the PINTA signal. This interrupt can be masked through the ISM register. See Section 5 for more details. 11.1.
DS3131 Figure 11-4.
DS3131 11.2 Local Bus Bridge Mode Control Register Description Register Name: Register Description: Register Address: LBBMC Local Bus Bridge Mode Control 0040h Note: This register can only be accessed through the PCI bus and therefore only in the PCI bridge mode. In configuration mode, this register cannot be accessed. It is set to all zeros upon a hardware reset issued through the PRST pin.
DS3131 Bit 6/Local Bus Width (LBW) 0 = 16 bits 1 = 8 bits Bits 8 to 11/Local Bus Arbitration Timer Setting (LAT0 to LAT3). These four bits determine the total time the local bus seizes the bus when it has been granted in the arbitration mode (LARBE = 1). This period is measured from LHLDA (LBG) being detected to LBGACK inactive.
DS3131 11.3 Examples of Bus Timing for Local Bus PCI Bridge Mode Operation Figure 11-5. 8-Bit Read Cycle Intel Mode (LIM = 0) Arbitration Enabled (LARBE = 1) Bus Transaction Time = 4 LCLK (LRDY = 0100) An attempted access by the host causes the local bus to request the bus. If bus access has not been granted (LBGACK deasserted), the timing shown at the top of the page applies, with LHOLD being asserted. Once LHLDA is detected, the local bus grabs the bus for 32 to 1,048,576 clocks and then releases it.
DS3131 Figure 11-6. 16-Bit Write Cycle Intel Mode (LIM = 0) Arbitration Enabled (LARBE = 1) Bus Transaction Time = 4 LCLK (LRDY = 0100) An attempted access by the host causes the local bus to request the bus. If bus access has not been granted (LBGACK deasserted), the timing shown at the top of the page applies, with LHOLD being asserted. Once LHLDA is detected, the local bus grabs the bus for 32 to 1,048,576 clocks and then releases it.
DS3131 Figure 11-7. 8-Bit Read Cycle Intel Mode (LIM = 0) Arbitration Disabled (LARBE = 0) Bus Transaction Time = Timed from LRDY (LRDY = 0000) LCLK LA[19:0] 1 2 3 4 5 6 7 8 9 Address Valid LD[7:0] LD[15:8] LBHE LWR LRD LRDY Note: The LRDY signal must be detected by the 9th LCLK or the bus access attempted by the host is unsuccessful and the LBE status bit is set.
DS3131 Figure 11-8. 16-Bit Write (Only Upper 8 Bits Active) Cycle Intel Mode (LIM = 0) Arbitration Disabled (LARBE = 0) Bus Transaction Time = Timed from LRDY (LRDY = 0000) LCLK LA[19:0] 1 2 3 4 5 6 7 8 9 10 Address Valid LD[7:0] LD[15:8] Data Valid LBHE LRD LWR LRDY Note: The LRDY signal must be detected by the 9th LCLK or the bus access attempted by the host is unsuccessful and the LBE status bit is set.
DS3131 Figure 11-9. 8-Bit Read Cycle Motorola Mode (LIM = 1) Arbitration Enabled (LARBE = 1) Bus Transaction Time = 6 LCLK (LRDY = 0110) An attempted access by the host causes the local bus to request the bus. If bus access has not been granted (LBGACK deasserted), the timing shown at the top of the page applies, with LBR being asserted. Once LBG is detected, the local bus grabs the bus for 32 to 1,048,576 clocks and then releases it.
DS3131 Figure 11-10. 8-Bit Write Cycle Motorola Mode (LIM = 1) Arbitration Enabled (LARBE = 1) Bus Transaction Time = 6 LCLK (LRDY = 0110) An attempted access by the host causes the local bus to request the bus. If bus access has not been granted (LBGACK deasserted), the timing shown at the top of the page applies, with LBR being asserted. Once LBG is detected, the local bus grabs the bus for 32 to 1,048,576 clocks and then releases it.
DS3131 Figure 11-11. 16-Bit Read Cycle Motorola Mode (LIM = 1) Arbitration Disabled (LARBE = 0) Bus Transaction Time = Timed from LRDY (LRDY = 0000) LCLK LA[19:0] 1 2 3 4 5 6 7 8 9 10 Address Valid LD[7:0] LD[15:8] LBHE LR/W LDS LRDY Note: The LRDY signal must be detected by the 9th LCLK or the bus access attempted by the host is unsuccessful and the LBE status bit is set.
DS3131 Figure 11-12. 8-Bit Write Cycle Motorola Mode (LIM = 1) Arbitration Disabled (LARBE = 0) Bus Transaction Time = Timed from LRDY (LRDY = 0000) LCLK LA[19:0] LD[7:0] 1 2 3 4 5 6 7 8 9 10 Address Valid Data Valid Three-State LD[15:8] LBHE LR/W LDS LRDY Note: The LRDY signal must be detected by the 9th LCLK or the bus access attempted by the host is unsuccessful and the LBE status bit is set.
DS3131 12. JTAG 12.1 JTAG Description The DS3131 supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. Figure 12-1 is a block diagram. The DS3131 contains the following items, which meet the requirements set by the IEEE 1149.
DS3131 12.2 TAP Controller State Machine Description This section details the operation of the TAP controller state machine. See Figure 12-2 for details about each of the states described below. The TAP controller is a finite state machine, which responds to the logic level at JTMS on the rising edge of JTCLK. Figure 12-2.
DS3131 Test-Logic-Reset. The TAP controller is in the Test-Logic-Reset state upon DS3131 power-up. The instruction register contains the IDCODE instruction. All system logic on the DS3131 operates normally. Run-Test-Idle. Run-Test-Idle is used between scan operations or during specific tests. The instruction and test registers remain idle. Select-DR-Scan. All test registers retain their previous state.
DS3131 Shift-IR. In this state, the shift register in the instruction register is connected between JTDI and JTDO and shifts data one stage for every rising edge of JTCLK toward the serial output. The parallel registers as well as all test registers remain at their previous states. A rising edge on JTCLK with JTMS high moves the controller to the Exit1-IR state.
DS3131 12.3 Instruction Register and Instructions The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS low shifts data one stage toward the serial output at JTDO.
DS3131 12.4 Test Registers IEEE 1149.1 requires a minimum of two test registers, the bypass register and the boundary scan register. An optional identification register has been included in the DS3131 design that is used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller. Bypass Register This is a single 1-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ instructions that provides a short path between JTDI and JTDO.
DS3131 13. AC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Voltage on Any Lead with Respect to VSS (except VDD) Supply Voltage (VDD) with Respect to VSS Operating Temperature/Ambient Temperature Under Bias Junction Temperature Under Bias Storage Temperature Range Soldering Temperature Range ESD Tolerance (Note 1) -0.3V to 5.5V -0.3V to 3.63V 0°C to +70°C ≤125°C -55°C to +125°C See IPC/JEDEC J-STD-020A Class 2 (2000V→4000V HBM: 1.
DS3131 AC CHARACTERISTICS: LAYER 1 PORTS (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.
DS3131 AC CHARACTERISTICS: LOCAL BUS IN BRIDGE MODE (LMS = 0) (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.
DS3131 AC CHARACTERISTICS: LOCAL BUS IN CONFIGURATION MODE (LMS = 1) (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.
DS3131 Figure 13-3.
DS3131 Figure 13-4.
DS3131 AC CHARACTERISTICS: PCI BUS INTERFACE (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.
DS3131 AC CHARACTERISTICS: JTAG TEST PORT INTERFACE (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.) PARAMETER JTCLK Clock Period JTCLK Clock Low Time JTCLK Clock High Time JTMS/JTDI Setup Time to the Rising Edge of JTCLK JTMS/JTDI Hold Time from the Rising Edge of JTCLK Delay Time from the Falling Edge of JTCLK to Data Valid on JTDO SYMBOL t1 t2 t3 CONDITIONS MIN 1000 400 400 TYP MAX UNITS ns ns ns t4 50 ns t5 50 ns t6 2 Figure 13-6.
DS3131 14. MECHANICAL DIMENSIONS 14.
DS3131 15. APPLICATIONS This section describes some possible applications for the DS3131. There are many potential configurations but only a few are shown. Users are encouraged to contact the factory for support of their particular application. Email telecom.support@dalsemi.com or visit our website at www.maxim-ic.com/telecom for more information. 15.1 T1/E1 and T3/E3 Applications Figure 15-1 shows an application where 28 T1 lines are being terminated into the DS3131.
DS3131 Figure 15-2 shows an application where up to 40 T1 or E1 ports are interfaced to a single DS3131. In this application, the quad T1 and E1 transceivers (DS21Q352/DS21Q552/DS21Q354/DS21Q554) perform the line interface function and frames to the T1 or E1 line. The local bus (if enabled) can be used to configure and monitor the T1/E1 transceivers. Figure 15-2.
DS3131 Figure 15-3 shows an application where three T3 or E3 framers are interfaced to a single DS3131. The DS3131 is used to terminate both the payload of the T3 or E3 link as well as the overhead channels (like the C bits in a T3 application). The local bus (if enabled) can be used to configure and monitor the T3/E3 framers. Figure 15-3. Unchannelized T3 or E3 Application Payload Overhead (i.e.
DS3131 15.2 DSL and Cable Modem Applications Figure 15-4 shows an application where multiple xDSL or cable modems are interfaced to a single DS3131. Such an application would exist in a DSLAM. The DS3131 is used to terminate both the payload of the xDSL/cable modem link as well as the overhead channels (like the links used for signaling and provisioning).
DS3131 15.3 ONET/SDH Applications Figure 15-5 shows an application where the overhead links on multiple SONET or SDH lines are being terminated into a single DS3131. The local bus (if enabled) can be used to configure and monitor the SONET/SDH interfaces. Figure 15-5.
