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Maxim/Dallas Semiconductor Confidential

Note: This Product Preview contains preliminary information and is subject to change without notice.

PRELIMINAR

PRODUCT BRIEF

Some revisions of this device may incorporate deviations from published specifications known as errata.

Multiple revisions of any device may be simultaneously available through various sales channels. For

information about device errata, visit: http://dbserv.maxim-ic.com/errata.cfm

Rev 1.6 1 of 12 022604

PRODUCT PREVIEW

DS3161,2,3,4 Multi-Port ATM/Packet PHYs For DS3/E3

FEATURES

• Universal PHYs map ATM cells and/or

HDLC packets into DS3 or E3 data streams

• Single, dual, triple and quad-port devices

• UTOPIA 2 or 3 or POS-PHY 2 or 3 interface

with 8, 16, or 32 bit bus width up to 66 MHz

• Ports independently configurable for cell or

packet traffic in POS-PHY bus modes

• Direct, PLCP and clear-channel cell mapping

• Direct and clear-channel packet mapping

• On-chip DS3 (M23 or C-bit) and E3 (G.751

or G.832) framers

• Ports independently configurable for DS3, E3

or arbitrary framing protocol up to 52 Mbps

• Programmable (externally controlled or

internally hardware based engine) subrate

DS3/E3 circuitry

• DS3/E3/PLCP alarm generation and detection

• Built-in HDLC controllers with 256 byte

FIFOs for DS3 PMDL, G.751 Sn bit or G.832

NR/GC bytes

• On-chip BERTs for PRBS and repetitive

pattern generation, detection and analysis

• Full featured DS3/E3/PLCP alarms

• Large performance-monitoring counters for

accumulation intervals up to 1 second

• Flexible overhead insertion/extraction ports

for DS3, E3 and PLCP framers

• Loopbacks include line, diagnostic, framer

payload and system interface

• Ports can be disabled to reduce power

• Integrates clock rate adapter to generate the

required 44.736 MHz for DS3, 34.368 MHz

for E3, and/or 52 MHz for arbitrary framing

protocol up to 52 Mbps

• 8/16-bit generic microprocessor interface

• 3.3V supply with 5V tolerant I/O

• Small high-density Thermally Enhanced (TE)

Chip Scale BGA packaging

• IEEE 1149.1 JTAG test port

www.maxim-ic.com/telecom

Summary of content (12 pages)

PAGE 1
Maxim/Dallas Semiconductor Confidential PRODUCT BRIEF PRELIMINARY PRODUCT PREVIEW DS3161,2,3,4 Multi-Port ATM/Packet PHYs For DS3/E3 FEATURES • • • • • • • • • • • • • • • • • Universal PHYs map ATM cells and/or HDLC packets into DS3 or E3 data streams Single, dual, triple and quad-port devices UTOPIA 2 or 3 or POS-PHY 2 or 3 interface with 8, 16, or 32 bit bus width up to 66 MHz Ports independently configurable for cell or packet traffic in POS-PHY bus modes Direct, PLCP and clear-channel cell mapping
PAGE 2
Maxim/Dallas Semiconductor Confidential PRODUCT PREVIEW DS3161,2,3,4 Multi-Port ATM/Packet PHYs For DS3/E3 FUNCTIONAL DIAGRAM ORDERING INFORMATION Line Interface Serial Clock/Data Ports[1:n] DS3/E3 Overhead Ports[1:n] PLCP Overhead Ports[1:n] DS316x to LIUs or SONET/SDH mapper System Interface UTOPIA or POS-PHY bus to ATM or Link layer Framer Interface Ports[1:n] Microprocessor Interface Commercial Temperature Range (0°C to 70°C) DS3161 Single 400-lead TE-CSBGA DS3162 Dual 400-lead TE-CSBGA DS316
PAGE 3
Maxim/Dallas Semiconductor Confidential Product Preview: DS3161,2,3,4 DESCRIPTION The DS316x Multi-port PHYs map ATM cells and/or packets into as many as four DS3/E3 data streams. Dedicated cell processor and packet processor blocks prepare outgoing cells or packets for transmission and check incoming cells or packets upon arrival. Built-in DS3/E3 framers transmit and receive cell/packet data in properly formatted M23 DS3, C-bit DS3, G.751 E3 or G.832 E3 data streams.
PAGE 4
Maxim/Dallas Semiconductor Confidential Product Preview: DS3161,2,3,4 Figure 2–1 Four-Port Unchannelized ATM over T3/E3 Card Typical ATM Line Card x DS3/E3 Line DS315x #1 DS3154 4- Chan DS3/E DS3/E3 LIU Utopia POSPHY DS316x #1 DS3164 4- Chan DS3/E DS3/E3 ATM PH PHY 2/3 AT ATM Switch Card Utopia POS PHY 2/3 (S/W+ Igr/Egr Mgt) OC--12 n AT ATM SAR DS318 x DS3/E3 Line DS315x #3 DS3154 4- Chan DS3/E DS3/E3 LIU DS316x #3 DS3164 4- Chan DS3/E DS3/E3 ATM PH PHY X = 1, 2, 3, 4 Typical ATM Line Card
PAGE 5
Maxim/Dallas Semiconductor Confidential Product Preview: DS3161,2,3,4 3 FEATURE DETAILS 3.1 Global Features • • • • • • • • • • • • System interface configurable for UTOPIA 2 / UTOPIA 3 for ATM cell traffic or POS-PHY 2 / POSPHY 3 for HDLC or mixed packet/cell traffic Supports the following transmission protocols: • Direct-mapped ATM over DS3 or subrate DS3 • PLCP-mapped ATM over DS3 • Direct-mapped ATM over G.751 E3 or subrate G.751 E3 • PLCP-mapped ATM over G.751 E3 • Direct-mapped ATM over G.
PAGE 6
Maxim/Dallas Semiconductor Confidential • • Product Preview: DS3161,2,3,4 Framer pass-through mode for clear channel applications and externally defined frame formats Built-in support for subrate DS3/E3 3.
PAGE 7
Maxim/Dallas Semiconductor Confidential • • Product Preview: DS3161,2,3,4 Programmable fill level thresholds Underflow and overflow status indications 3.
PAGE 8
Maxim/Dallas Semiconductor Confidential • Product Preview: DS3161,2,3,4 Counters for number of packets and bytes read from the transmit FIFO 3.
PAGE 9
Maxim/Dallas Semiconductor Confidential • • Product Preview: DS3161,2,3,4 Insertion of the outgoing trail access point identifier from a 16-byte transmit register Receive trace identifier unstable status indication 3.
PAGE 10
Maxim/Dallas Semiconductor Confidential Specification T1.404-1994 T1.646-1995 ATM Forum af-phy-0034.000 af-phy-0039.000 af-phy-0043.000 af-phy-0054.000 af-phy-0136.000 af-phy-0143.000 af-bici-0013.003 ETSI ETS 300 337 ETS 300 689 IEEE IEEE Std 11491990 IETF RFC 1661 RFC 1662 RFC 2496 ISO ISO 3309:1993 ITU-T G.703 G.704 G.751 G.775 G.804 G.832 I.432 Rev 1.
PAGE 11
Maxim/Dallas Semiconductor Confidential Specification O.151 Q.921 OIF OIF-SPI3-01.
PAGE 12
Maxim/Dallas Semiconductor Confidential Product Preview: DS3161,2,3,4 5 PACKAGE MECHANICAL DIMENSIONS The target package is a 27x27 mm 400-lead TE1-CSBGA with ball pitch of 1.27mm for all port density configuration. 6 POWER ESTIMATE Current typical power estimate is 2 Watts at 3.3V (pending mode of operation). 1 TE-CSBGA = Thermally Enhanced Chip Scale Ball Grid Array 12 of 12 Rev 1.