Instruction Manual

Maxim/Dallas Semiconductor Confidential Product Preview: DS3161,2,3,4
Rev 1.6 9 of 12 022604
• Insertion of the outgoing trail access point identifier from a 16-byte transmit register
• Receive trace identifier unstable status indication
3.17 Bit Error Rate Tester (BERT) Features
• Generates and detects pseudo-random patterns and repetitive patterns from 1 to 32 bits in length
• Supports pattern insertion/extraction in PLCP payload, DS3/E3 payload, or entire data stream
• Large 24-bit error counter allows testing to proceed for long periods without host intervention
• Errors can be inserted in the generated BERT patterns for diagnostic purposes (single bit errors or
specific bit-error rates)
3.18 Loopback Features
• Line facility loopback (receive to transmit) with optionally transmitting unframed all-one payload
toward system/trunk interface
• Framer diagnostic loopback (transmit to receive) with optionally transmitting unframed all-one signal
toward line/tributary interface
• Simultaneous line facility loopback and framer diagnostic loopback
• Framer payload loopback (receive to transmit) with optionally transmitting unframed all-one payload
toward system/trunk interface
• System interface loopback (transmit to receive)
3.19 Microprocessor Interface Features
• Multiplexed or non-multiplexed 8 or 16-bit control port
• Intel and Motorola bus compatible
• Global reset input pin
• Global interrupt output pin
• Two programmable I/O pins per port
3.20 Subrate Features
• Independent per port built-in support for subrate DS3 or E3
• Independent subrate operation for both Rx and Tx data paths
• Subrate operation for each channel is totally independent from the other channels’ operation, i.e. all
subrate functions within the device are mutually exclusive
• Three distinct subrate algorithms:
• (FFRAC) Externally controlled with DS3 or E3 payload manipulating capability
• (XFRAC) Externally controlled with simple DS3 or E3 data rate reduction capability
• (IFRAC) Internally controlled with flexible DS3 or E3 data rate reduction capability
• Subrate algorithm selection is on per port basis
• Internal subrate mechanism allows down to bit-level granularity of the DS3 or E3 payload
4 STANDARDS COMPLIANCE
Specification Specification Title
ANSI
T1.107-1995
Digital Hierarchy – Formats Specifications
T1.231-1997
Digital Hierarchy – Layer 1 In-Service Digital Transmission Performance
Monitoring