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PRODUCT BRIEF

Maxim/Dallas Semiconductor Confidential

Note: This Product Preview contains preliminary information and is subject to change without notice.

Some revisions of this device may incorporate deviations from published specifications known as errata.

Multiple revisions of any device may be simultaneously available through various sales channels. For

information about device errata, visit: http://dbserv.maxim-ic.com/errata.cfm

PRELIMINAR

PRODUCT BRIEF

PRODUCT PREVIEW

DS3181,2,3,4 Multi-Port ATM/Packet PHYs

For DS3/E3 with Built-In LIUs

FEATURES

• Quad (DS3184), triple (DS3183), dual

(DS3182) or single (DS3181) with integrated

LIU ATM / Packet PHYs for DS3 and E3

• Each port independently configurable

• Performs receive clock/data recovery and

transmit wave shaping

• Jitter attenuators can be placed either in the

receive or transmit paths

• Interfaces to 75Ω coaxial cable at lengths up

to 380 meters or 1246 feet (DS3) or 440

meters or 1443 feet (E3)

• Uses 1:2 transformers on both Tx and Rx

• Requires minimal external components

• Universal PHYs map ATM cells and/or

HDLC packets into DS3 or E3 data streams

• UTOPIA 2 or 3 or POS-PHY 2 or 3 interface

with 8, 16, or 32 bit bus width up to 66 MHz

• Ports independently configurable for cell or

packet traffic in POS-PHY bus modes

• Direct, PLCP and clear-channel cell mapping

• Direct and clear-channel packet mapping

• On-chip DS3 (M23 or C-bit) and E3 (G.751

or G.832) framers

• Ports independently configurable for DS3, E3

or arbitrary framing protocol up to 52 Mbps

• Programmable (externally controlled or

internally hardware based engine) subrate

DS3/E3 circuitry

• Full featured DS3/E3/PLCP alarms

• Built-in HDLC controllers with 256 byte

FIFOs for DS3 PMDL, G.751 Sn bit or G.832

NR/GC bytes

• On-chip BERTs for PRBS and repetitive

pattern generation, detection and analysis

• Large performance-monitoring counters for

accumulation intervals up to 1 second

• Flexible overhead insertion/extraction ports

for DS3, E3 and PLCP framers

• Loopback include line, diagnostic, framer

payload and system interface

• Ports can be disabled to reduce power

• Integrates clock rate adapter to generate the

required 44.736 MHz for DS3, 34.368 MHz

for E3, and/or 52 MHz for arbitrary framing

protocol up to 52 Mbps

• 8/16-bit generic microprocessor interface

• Low power 3.3V operation (5V tolerant I/O)

• Small high-density Thermally Enhanced (TE)

Chip Scale BGA packaging

• Industrial temperature range: -40 to +85°C

• IEEE 1149.1 JTAG test port

www.maxim-ic.com/telecom

Rev 1.5 1 of 13 022304

Summary of content (13 pages)

PAGE 1
PRODUCT BRIEF Maxim/Dallas Semiconductor Confidential PRODUCT BRIEF PRELIMINARY PRODUCT PREVIEW DS3181,2,3,4 Multi-Port ATM/Packet PHYs For DS3/E3 with Built-In LIUs FEATURES • • • • • • • • • • • • • • • • • Quad (DS3184), triple (DS3183), dual (DS3182) or single (DS3181) with integrated LIU ATM / Packet PHYs for DS3 and E3 Each port independently configurable Performs receive clock/data recovery and transmit wave shaping Jitter attenuators can be placed either in the receive or transmit paths Interfa
PAGE 2
Maxim/Dallas Semiconductor Confidential PRODUCT PREVIEW DS3181,2,3,4 Multi-Port ATM/Packet PHYs For DS3/E3 with Built-In LIUs FUNCTIONAL DIAGRAM ORDERING INFORMATION Line Interface TXPn/TXNn RXPn/RXNn Ports[1:n] DS3/E3 Overhead Ports[1:n] PLCP Overhead Ports[1:n] DS318x To T3/E3 Transformers System Interface UTOPIA or POS-PHY bus to ATM or Link layer Framer Interface Ports[1:n] Microprocessor Interface Commercial Temperature Range (0°C to 70°C) DS3181 Single 400-lead TE-CSBGA DS3182 Dual 400-lead
PAGE 3
Maxim/Dallas Semiconductor Confidential Product Preview: DS3181,2,3,4 DESCRIPTION The DS3184 (quad), DS3183 (triple), DS3182 (dual), and DS3181 (single) PHYs perform all of the functions necessary for mapping/demapping ATM cells and/or packets into as many as four DS3/E3 data streams on T3 or E3 physical copper lines. Each line interface unit (LIU) has independent receive and transmit paths.
PAGE 4
Maxim/Dallas Semiconductor Confidential Product Preview: DS3181,2,3,4 B3ZS/ HDB3 Decoder TDATn TDENn / TGCLKn TSOFn / TIOHMn TLCLKn TPOHn TPOHGCLK TPOHSOFn 8KREFI Tx Cell Processor TSCLK TADR[4:0] TDATA[31:0] TPRTY* TEN* TPXA TDXA[4:1] TSOX TSPA TEOP TSX TMOD[1:0] TERR Tx FIFO BERT System Interface Loopback Tx Packet Processor Rx Packet Processor Rx PLCP/FRAC Framer IEEE P1149.
PAGE 5
Maxim/Dallas Semiconductor Confidential Product Preview: DS3181,2,3,4 Figure 2-1 Four-Port Unchannelized ATM over T3/E3 Line Card Typical ATM Line Card x DS3/E3 Line DS315x #1 DS3154 4- Chan DS3/E DS3/E3 LIU Utopia POSPHY DS316x #1 DS3164 4- Chan DS3/E DS3/E3 ATM PH PHY 2/3 AT ATM Switch Card Utopia POS PHY 2/3 (S/W+ Igr/Egr Mgt) OC--12 n AT ATM SAR DS318 x DS3/E3 Line DS315x #3 DS3154 4- Chan DS3/E DS3/E3 LIU DS316x #3 DS3164 4- Chan DS3/E DS3/E3 ATM PH PHY X = 1, 2, 3, 4 Typical ATM Line
PAGE 6
Maxim/Dallas Semiconductor Confidential Product Preview: DS3181,2,3,4 3.1 Global Features • • • • • • • • • • System interface configurable for UTOPIA 2 / UTOPIA 3 for ATM cell traffic or POS-PHY 2 / POSPHY 3 for HDLC or mixed packet/cell traffic Supports the following transmission protocols: • Direct-mapped ATM over DS3 or subrate DS3 • PLCP-mapped ATM over DS3 • Direct-mapped ATM over G.751 E3 or subrate G.751 E3 • PLCP-mapped ATM over G.751 E3 • Direct-mapped ATM over G.832 E3 or subrate G.
PAGE 7
Maxim/Dallas Semiconductor Confidential • • • • Product Preview: DS3181,2,3,4 C bits configurable as payload or overhead Most framing overhead fields presented on the receive overhead port Framer pass-through mode for clear channel applications and externally defined frame formats Built-in support for subrate DS3/E3 3.
PAGE 8
Maxim/Dallas Semiconductor Confidential Product Preview: DS3181,2,3,4 3.7 Receive FIFO Features • • • • Storage capacity for four cells or 256 bytes of packet data Programmable port address Programmable fill level thresholds Underflow and overflow status indications 3.
PAGE 9
Maxim/Dallas Semiconductor Confidential • • • • Product Preview: DS3181,2,3,4 Automatic packet abort insertion Packet scrambling using the self-synchronizing scrambler (x43+1) Controls include enables/disables/settings for: packet processing, FCS insertion or overwrite, 16/32bit FCS, inter-frame fill type/length, scrambling, FCS error insertion type/rate/count Counters for number of packets and bytes read from the transmit FIFO 3.
PAGE 10
Maxim/Dallas Semiconductor Confidential • Product Preview: DS3181,2,3,4 Terminates the Path Maintenance Data Link in DS3 C-bit Parity mode or the G.751 Sn bit or the G.832 NR or GC channels 3.
PAGE 11
Maxim/Dallas Semiconductor Confidential Product Preview: DS3181,2,3,4 3.23 Subrate Features • • • • • • Independent per port built-in support for subrate DS3 or E3 Independent subrate operation for both Rx and Tx data paths Subrate operation for each channel is totally independent from the other channels’ operation, i.e.
PAGE 12
Maxim/Dallas Semiconductor Confidential Specification IEEE IEEE Std 11491990 IETF RFC 1661 RFC 1662 RFC 2496 ISO ISO 3309:1993 ITU-T G.703 G.704 G.751 G.775 G.804 G.823 G.832 I.432 O.151 Q.921 OIF OIF-SPI3-01.0 Saturn Group POS-PHY 2 POS-PHY 3 Telcordia GR-253-CORE GR-499-CORE GR-820-CORE Product Preview: DS3181,2,3,4 Specification Title D34S), Terminal equipment interface, V 1.2.
PAGE 13
Maxim/Dallas Semiconductor Confidential Product Preview: DS3181,2,3,4 5 PACKAGE MECHANICAL DIMENSIONS The target package is a 27x27 mm 400-lead TE1-CSBGA with ball pitch of 1.27mm for all port density configuration. 6 POWER ESTIMATE Current typical power estimate is 2.7 Watts at 3.3V (pending mode of operation). 1 TE-CSBGA: Thermally Enhanced Chip Scale Ball Grid Array 13 of 13 Rev 1.