Instruction Manual

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General Description

The DS8102 is a stand-alone, dual-channel, delta-

sigma modulator that converts measurements from two

differential analog input pairs into a Manchester-encod-

ed output bit stream that can be processed by a com-

panion microcontroller such as the MAXQ3108. One

channel operates at a fixed 1x gain, while the other

operates at a pin-selectable gain of 1x, 4x, 16x, or 32x.

The DS8102 includes an internal power-supply monitor,

on-board voltage reference, and low-power oscillator to

reduce the number of external components required for

data acquisition.

The Manchester-encoded output from the DS8102

combines pulse-density-modulated measurement val-

ues from both differential input channels with a syn-

chronization bit stream and is transmitted over a single

pin. This transmission scheme is ideal for split voltage

domain applications where the DS8102 and other “hot”-

side components must be electrically isolated from

“cold” low-voltage components such as a companion

microcontroller. In this type of application, the DS8102

can be capacitively coupled to a companion microcon-

troller with only two connection points required

(MNOUT and DGND).

The MAXQ3108 dual-core microcontroller, which

includes specialized Manchester bit-stream decoding

inputs and sinc3 filters, is specifically designed to act

as a companion microcontroller for up to three DS8102

devices. This configuration, which supports up to six

differential analog input channels, is well suited for

three-phase electricity-metering applications.

Applications

Single-Phase Electricity Metering

Three-Phase Electricity Metering

Power-Line Conditioning

Electrochemical and Optical Sensors

Industrial Control

Data-Acquisition Systems and Data Loggers

Features

♦ Dual Delta-Sigma 2nd-Order Modulators

Channel 0: Pin-Selectable Gain of 1x, 4x, 16x,

or 32x

Channel 1: Fixed Gain of 1x

♦ Selectable Internal or External Voltage Reference

♦ Manchester-Encoded Bit Stream Output

Includes Synchronization Bits to Allow Clock

Recovery

Single-Pin Transmission Scheme Simplifies

Electrical Isolation Using Capacitive Coupling

♦ Selectable Internal or External Clock Source

♦ Integrated Low-Power 8MHz Oscillator

♦ Operating Mode

Active Mode (8MHz, V

= 3.6V): 3.5mA

DS8102

Dual Delta-Sigma Modulator and Encoder

________________________________________________________________

Maxim Integrated Products

TOP VIEW

TSSOP

134 MNOUTAN1-

143 RSTV

REF

152

APDREF

AGND

161V

DGND

107

AN0+

116

G1AN0-

CLKSELV

125

CLKIO

AN1+

DS8102

Pin Configuration

Ordering Information

Rev 1; 2/09

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

Denotes a lead(Pb)-free/RoHS-compliant package.

PART TEMP RANGE PIN-PACKAGE

DS8102+ -40°C to +85°C 16 TSSOP

Typical Operating Circuit appears at end of data sheet.

MAXQ is a trademark of Maxim Integrated Products, Inc.

Summary of content (9 pages)

PAGE 1
Rev 1; 2/09 Dual Delta-Sigma Modulator and Encoder Features The DS8102 is a stand-alone, dual-channel, deltasigma modulator that converts measurements from two differential analog input pairs into a Manchester-encoded output bit stream that can be processed by a companion microcontroller such as the MAXQ3108. One channel operates at a fixed 1x gain, while the other operates at a pin-selectable gain of 1x, 4x, 16x, or 32x.
PAGE 2
DS8102 Dual Delta-Sigma Modulator and Encoder ABSOLUTE MAXIMUM RATINGS Voltage Range on AN0+, AN0-, AN1+, and AN1Relative to AGND ...............................................-4.0V to +4.0V Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Soldering Temperature...........................Refer to the IPC/JEDEC J-STD-020 Specification. Voltage Range on VDD Relative to DGND.............-0.3V to +4.
PAGE 3
Dual Delta-Sigma Modulator and Encoder (VDD = 2.7V to 3.6V, TA = -40°C to +85°C, fCLK = 8MHz, VREF = internal, OSR = 128, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP (Note 2) MAX UNITS ANALOG-TO-DIGITAL CONVERTER DYNAMIC SPECIFICATIONS DC Power-Supply Rejection Ratio Signal-to-Noise Ratio PSRR SINAD Total Harmonic Distortion THD (to 21st Harmonic) ANALOG-TO-DIGITAL CONVERTER INPUTS Input Voltage Range VDD = 3.0V to 3.
PAGE 4
Dual Delta-Sigma Modulator and Encoder DS8102 Pin Description PIN NAME 1 DGND Digital Ground 2 AGND Analog Ground 3 VREF Reference Voltage Input/Output. When APDREF = 0, the buffered internal voltage reference is driven on this pin as an output and can be used by other devices. When APDREF = 1, an external voltage reference must be provided on this pin.
PAGE 5
Dual Delta-Sigma Modulator and Encoder RST APDREF INTERNAL REFERENCE 8MHz OSCILLATOR REFERENCE BUFFER CLKIO VREF AN1+ 1x AN1- DS8102 INTEGRATORS/ COMPARATOR DELTA-SIGMA MODULATOR AN0+ AN0- CLKSEL 1x, 4x, 16x, 32x MANCHESTER ENCODER MNOUT INTEGRATORS/ COMPARATOR POWER MONITOR DELTA-SIGMA MODULATOR G1 G0 AGND Detailed Description Operating Modes DGND VDD 1) Drive the RST line on the DS8102 low to force the DS8102 into shutdown mode.
PAGE 6
DS8102 Dual Delta-Sigma Modulator and Encoder Once the power supply is at an acceptable level (V DD > V RST ) and the RST line is driven high, the DS8102 exits shutdown mode. However, a warmup sequence must then be completed before analog-todigital conversion and Manchester encoding begins. The length of this sequence depends on the internal/external voltage reference mode (controlled by the APDREF pin).
PAGE 7
Dual Delta-Sigma Modulator and Encoder The configuration pin APDREF selects whether the DS8102 uses its internal voltage reference or an external voltage reference provided at VREF when performing conversions. If the internal voltage reference is selected, the internal reference is buffered and driven out at VREF, and can be used by external devices if desired. Table 2 summarizes the modes of operation for the DS8102 based on the APDREF input.
PAGE 8
DS8102 Dual Delta-Sigma Modulator and Encoder 1 2 3 4 5 6 7 9 10 11 12 1 8 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 SYNC CHAN0 CHAN1 SYNC CHAN0 CHAN1 SYNC CHAN0 CHAN1 SYNC CHAN0 CHAN1 1 CLKIO 0 1 0 0 0 0 1 1 1 0 0 1 1 MNOUT Figure 1.
PAGE 9
Dual Delta-Sigma Modulator and Encoder REVISION NUMBER REVISION DATE 0 1/09 1 2/09 DESCRIPTION PAGES CHANGED Initial release. — Changed the part number in the Ordering Information table. 1 In the Electrical Characteristics table, changed fXCLK(MAX) from 12MHz to 8MHz; changed tXCLK-CLCL(MIN) from 83ns to 125ns; changed the Offset Error parameter from 1.4mV (min) to 1.4mV (max); added new conditions and note and changed 1.33MHz (typ) to 0.667MHz (typ) for the Input Sampling Rate parameter.