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DS92LV090A

9 Channel Bus LVDS Transceiver

General Description

The DS92LV090A is one in a series of Bus LVDS transceiv-

ers designed specifically for the high speed, low power

proprietary backplane or cable interfaces. The device oper-

ates from a single 3.3V power supply and includes nine

differential line drivers and nine receivers. To minimize bus

loading, the driver outputs and receiver inputs are internally

connected. The separate I/O of the logic side allows for loop

back support. The device also features a flow through pin out

which allows easy PCB routing for short stubs between its

pins and the connector.

The driver translates 3V TTL levels (single-ended) to differ-

ential Bus LVDS (BLVDS) output levels. This allows for high

speed operation, while consuming minimal power with re-

duced EMI. In addition, the differential signaling provides

common mode noise rejection of

1V.

The receiver threshold is less than

100 mV over a

common mode range and translates the differential Bus

LVDS to standard (TTL/CMOS) levels. (See Applications

Information Section for more details.)

Features

n Bus LVDS Signaling

n 3.2 nanosecond propagation delay max

n Chip to Chip skew

800ps

n Low power CMOS design

n High Signaling Rate Capability (above 100 Mbps)

n 0.1V to 2.3V Common Mode Range for V

= 200mV

100 mV Receiver Sensitivity

n Supports open and terminated failsafe on port pins

n 3.3V operation

n Glitch free power up/down (Driver & Receiver disabled)

n Light Bus Loading (5 pF typical) per Bus LVDS load

n Designed for Double Termination Applications

n Balanced Output Impedance

n Product offered in 64 pin TQFP package

n High impedance Bus pins on power off (V

= 0V)

n Driver Channel to Channel skew (same device) 230ps

typical

n Receiver Channel to Channel skew (same device)

370ps typical

Simplified Functional Diagram

TRI-STATE

is a registered trademark of National Semiconductor Corporation.

DS100111-1

February 2001

DS92LV090A 9 Channel Bus LVDS Transceiver

Summary of content (9 pages)

PAGE 1
DS92LV090A 9 Channel Bus LVDS Transceiver General Description Features The DS92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading, the driver outputs and receiver inputs are internally connected. The separate I/O of the logic side allows for loop back support.
PAGE 2
DS92LV090A Connection Diagram DS100111-2 Top View Order Number DS92LV090ATVEH See NS Package Number VEH064DB Pinout Description Pin Name Pin # Input/Output Descriptions DO+/RI+ 27, 31, 35, 37, 41, 45, 47, 51, 55 I/O True Bus LVDS Driver Outputs and Receiver Inputs. DO−/RI− 26, 30, 34, 36, 40, 44, 46, 50, 54 I/O Complimentary Bus LVDS Driver Outputs and Receiver Inputs. DIN 2, 6, 12, 18, 20, 22, 58, 60, 62 I TTL Driver Input. RO 3, 7, 13, 19, 21, 23, 59, 61, 63 O TTL Receiver Output.
PAGE 3
θja θjc Storage Temperature Range Lead Temperature (Soldering, 4 sec.) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) 4.0V Enable Input Voltage −0.3V to (VCC +0.3V) (DE, RE) −0.3V to (VCC +0.3V) Driver Input Voltage (DIN) Receiver Output Voltage −0.3V to (VCC +0.3V) (ROUT) −0.3V to +3.9V Bus Pin Voltage (DO/RI ± ) > 4.5 kV ESD (HBM 1.
PAGE 4
DS92LV090A DC Electrical Characteristics (Continued) Over recommended operating supply voltage and temperature ranges unless otherwise specified (Notes 2, 3) Symbol Parameter VIH Minimum Input High Voltage VIL Maximum Input Low Voltage IIH Input High Current IIL VCL ICCD ICCR ICCZ ICC IOFF Conditions Min Typ 2.0 VCC V GND 0.8 V +20 µA +20 µA VIN = VCC or 2.4V −20 Input Low Current VIN = GND or 0.4V −20 ± 10 ± 10 Input Diode Clamp Voltage ICLAMP = −18 mA −1.5 −0.
PAGE 5
(Continued) Over recommended operating supply voltage and temperature ranges unless otherwise specified (Note 6) Symbol Parameter Conditions Min Typ Max Units 4.5 10 ns 3.5 8 ns 3.5 8 ns 3.
PAGE 6
DS92LV090A Test Circuits and Timing Waveforms DS100111-3 FIGURE 1. Differential Driver DC Test Circuit DS100111-4 FIGURE 2. Differential Driver Propagation Delay and Transition Time Test Circuit DS100111-5 FIGURE 3. Differential Driver Propagation Delay and Transition Time Waveforms www.national.
PAGE 7
DS92LV090A Test Circuits and Timing Waveforms (Continued) DS100111-6 FIGURE 4. Driver TRI-STATE Delay Test Circuit DS100111-7 FIGURE 5. Driver TRI-STATE Delay Waveforms DS100111-8 FIGURE 6. Receiver Propagation Delay and Transition Time Test Circuit DS100111-9 FIGURE 7. Receiver Propagation Delay and Transition Time Waveforms 7 www.national.
PAGE 8
DS92LV090A Test Circuits and Timing Waveforms (Continued) DS100111-10 FIGURE 8. Receiver TRI-STATE Delay Test Circuit DS100111-11 FIGURE 9. Receiver TRI-STATE Delay Waveforms Typical Bus Application Configurations DS100111-12 Bi-Directional Half-Duplex Point-to-Point Applications DS100111-13 Multi-Point Bus Applications www.national.
PAGE 9
DS92LV090A 9 Channel Bus LVDS Transceiver Physical Dimensions All dimensions are in millimeters 64-Lead Molded TQFP Package Order Number DS92LV090ATVEH NS Package Number VEH064DB LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.