HD44780U (LCD-II) (Dot Matrix Liquid Crystal Display Controller/Driver) Description The HD44780U dot-matrix liquid crystal display controller and driver LSI displays alphanumerics, Japanese kana characters, and symbols. It can be configured to drive a dot-matrix liquid crystal display under the control of a 4- or 8-bit microprocessor.
HD44780U • 64 × 8-bit character generator RAM 8 character fonts (5 × 8 dot) 4 character fonts (5 × 10 dot) • 16-common × 40-segment liquid crystal display driver • Programmable duty cycles 1/8 for one line of 5 × 8 dots with cursor 1/11 for one line of 5 × 10 dots with cursor 1/16 for two lines of 5 × 8 dots with cursor • Wide range of instruction functions: Display clear, cursor home, display on/off, cursor on/off, display character blink, cursor shift, display shift • Pin function compatibilit
HD44780U HD44780U Block Diagram OSC1 OSC2 M Reset circuit ACL Timing generator CPG 8 RS R/W E Instruction register (IR) 7 Input/ output buffer 8 16-bit shift register Common signal driver 40-bit latch circuit Segment signal driver 7 40-bit shift register 8 7 DB4 to DB7 D Display data RAM (DDRAM) 80 × 8 bits Instruction decoder MPU interface Address counter DB0 to DB3 CL1 CL2 SEG1 to SEG40 7 Data register (DR) 8 40 8 8 LCD drive voltage selector Busy flag GND COM1 to COM16
HD44780U 65 66 67 68 69 70 71 72 73 74 75 76 77 78 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 FP-80B (Top view) 12 13 53 52 40 39 38 OSC2 V1 V2 V3 V4 V5 CL1 CL2 VCC M D RS R/W E DB0 DB1 37 41 36 42 24 35 43 23 34 44 22 33 45 21 32 46 20 31 47 19 30 48 18 29 49 17 28 50 16 27 51 15 26 14 25 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 GND OSC
HD44780U 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 1 60 2 59 3 58 4 57 5 56 6 55 7 54 8 53 9 52 TFP-80F (Top view) 10 11 51 50 40 39 38 37 36 35 34 33 32 31 30 41 29 42 20 28 43 19 27 44 18 26 45 17 25 46 16 24 47 15 23 48 14 22 49 13 21 12 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 DB7 DB6 DB5 DB4 GND OSC1 OSC2 V1 V2 V3 V4 V5 CL1 CL2 VCC M D RS R/W E DB0 DB1 DB2 DB3 SEG20
HD44780U HD44780U Pad Arrangement Chip size: 4.90 × 4.
HD44780U HCD44780U Pad Location Coordinates Pad No.
HD44780U Pin Functions Signal No. of Lines I/O Device Interfaced with RS 1 I MPU Selects registers. 0: Instruction register (for write) Busy flag: address counter (for read) 1: Data register (for write and read) R/W 1 I MPU Selects read or write. 0: Write 1: Read E 1 I MPU Starts data read/write. DB4 to DB7 4 I/O MPU Four high order bidirectional tristate data bus pins. Used for data transfer and receive between the MPU and the HD44780U. DB7 can be used as a busy flag.
HD44780U Function Description Registers The HD44780U has two 8-bit registers, an instruction register (IR) and a data register (DR). The IR stores instruction codes, such as display clear and cursor shift, and address information for display data RAM (DDRAM) and character generator RAM (CGRAM). The IR can only be written from the MPU. The DR temporarily stores data to be written into DDRAM or CGRAM and temporarily stores data to be read from DDRAM or CGRAM.
HD44780U Display Data RAM (DDRAM) Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its extended capacity is 80 × 8 bits, or 80 characters. The area in display data RAM (DDRAM) that is not used for display can be used as general data RAM. See Figure 1 for the relationships between DDRAM addresses and positions on the liquid crystal display. The DDRAM address (ADD ) is set in the address counter (AC) as hexadecimal.
HD44780U • 2-line display (N = 1) (Figure 4) Case 1: When the number of display characters is less than 40 × 2 lines, the two lines are displayed from the head. Note that the first line end address and the second line start address are not consecutive. For example, when just the HD44780 is used, 8 characters × 2 lines are displayed. See Figure 5. When display shift operation is performed, the DDRAM address shifts. See Figure 5.
HD44780U Case 2: For a 16-character × 2-line display, the HD44780 can be extended using one 40-output extension driver. See Figure 6. When display shift operation is performed, the DDRAM address shifts. See Figure 6.
HD44780U Character Generator ROM (CGROM) The character generator ROM generates 5 × 8 dot or 5 × 10 dot character patterns from 8-bit character codes (Table 4). It can generate 208 5 × 8 dot character patterns and 32 5 × 10 dot character patterns. Userdefined character patterns are also available by mask-programmed ROM. Character Generator RAM (CGRAM) In the character generator RAM, the user can rewrite character patterns by program.
HD44780U Hitachi User Start Computer processing Create character pattern listing 5 Evaluate character patterns No Determine character patterns 1 Create EPROM address data listing 2 Write EPROM 3 EPROM → Hitachi 4 OK? Yes Art work M/T Masking Trial Sample Sample evaluation OK? 6 No Yes Mass production Note: For a description of the numbers used in this figure, refer to the preceding page.
HD44780U • Programming character patterns This section explains the correspondence between addresses and data used to program character patterns in EPROM. The HD44780U character generator ROM can generate 208 5 × 8 dot character patterns and 32 5 × 10 dot character patterns for a total of 240 different character patterns. Character patterns EPROM address data and character pattern data correspond with each other to form a 5 × 8 or 5 × 10 dot character pattern (Tables 2 and 3).
HD44780U Handling unused character patterns 1. EPROM data outside the character pattern area: Always input 0s. 2. EPROM data in CGRAM area: Always input 0s. (Input 0s to EPROM addresses 00H to FFH.) 3. EPROM data used when the user does not use any HD44780U character pattern: According to the user application, handled in one of the two ways listed as follows. a. When unused character patterns are not programmed: If an unused character code is written into DDRAM, all its dots are lit.
HD44780U Table 4 Lower 4 Bits Upper 4 Bits Correspondence between Character Codes and Character Patterns (ROM Code: A00) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 xxxx0000 CG RAM (1) xxxx0001 (2) xxxx0010 (3) xxxx0011 (4) xxxx0100 (5) xxxx0101 (6) xxxx0110 (7) xxxx0111 (8) xxxx1000 (1) xxxx1001 (2) xxxx1010 (3) xxxx1011 (4) xxxx1100 (5) xxxx1101 (6) xxxx1110 (7) xxxx1111 (8) 1011 1100 1101 1110 1111 Note: The user can specify any pattern for character-generat
HD44780U Table 4 Lower 4 Bits Upper 4 Bits Correspondence between Character Codes and Character Patterns (ROM Code: A02) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 xxxx0000 CG RAM (1) xxxx0001 (2) xxxx0010 (3) xxxx0011 (4) xxxx0100 (5) xxxx0101 (6) xxxx0110 (7) xxxx0111 (8) xxxx1000 (1) xxxx1001 (2) xxxx1010 (3) xxxx1011 (4) xxxx1100 (5) xxxx1101 (6) xxxx1110 (7) xxxx1111 (8) 18
HD44780U Table 5 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character Patterns (CGRAM Data) For 5 × 8 dot character patterns Character Codes (DDRAM data) CGRAM Address Character Patterns (CGRAM data) 7 6 5 4 3 2 1 0 5 4 3 2 1 0 7 6 5 4 3 2 1 0 High High High Low 0 0 0 0 * 0 0 0 0 0 0 0 * 0 0 1 0 0 0 0 * 1 1 1 0 0 0 0 0 1 1 1 1 Low 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 0 0 1 1 0 1 0 1
HD44780U Table 5 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character Patterns (CGRAM Data) (cont) For 5 × 10 dot character patterns Character Codes (DDRAM data) CGRAM Address Character Patterns (CGRAM data) 7 6 5 4 3 2 1 0 5 4 3 2 1 0 7 6 5 4 3 2 1 0 High High High Low 0 0 0 0 * 0 0 * 0 0 0 0 * 1 1 * 0 0 1 1 Low 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1
HD44780U Timing Generation Circuit The timing generation circuit generates timing signals for the operation of internal circuits such as DDRAM, CGROM and CGRAM. RAM read timing for display and internal operation timing by MPU access are generated separately to avoid interfering with each other. Therefore, when writing data to DDRAM, for example, there will be no undesirable interferences, such as flickering, in areas other than the display area.
HD44780U Interfacing to the MPU The HD44780U can send data in either two 4-bit operations or one 8-bit operation, thus allowing interfacing with 4- or 8-bit MPUs. • For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. Bus lines DB0 to DB3 are disabled. The data transfer between the HD44780U and the MPU is completed after the 4-bit data has been transferred twice.
HD44780U Reset Function Initializing by Internal Reset Circuit An internal reset circuit automatically initializes the HD44780U when the power is turned on. The following instructions are executed during the initialization. The busy flag (BF) is kept in the busy state until the initialization ends (BF = 1). The busy state lasts for 10 ms after VCC rises to 4.5 V. 1. Display clear 2. Function set: DL = 1; 8-bit interface data N = 0; 1-line display F = 0; 5 × 8 dot character font 3.
HD44780U Normally, instructions that perform data transfer with internal RAM are used the most. However, autoincrementation by 1 (or auto-decrementation by 1) of internal HD44780U RAM addresses after each data write can lighten the program load of the MPU. Since the display shift instruction (Table 11) can perform concurrently with display data write, the user can minimize system development time with maximum programming efficiency.
HD44780U Table 6 Instructions (cont) Execution Time (max) (when f cp or f OSC is 270 kHz) Code Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description Write data to CG or DDRAM 1 0 Write data Writes data into DDRAM or CGRAM. 37 µs tADD = 4 µs* Read data 1 from CG or DDRAM 1 Read data Reads data from DDRAM or CGRAM.
HD44780U Instruction Description Clear Display Clear display writes space code 20H (character pattern for character code 20H must be a blank pattern) into all DDRAM addresses. It then sets DDRAM address 0 into the address counter, and returns the display to its original status if it was shifted. In other words, the display disappears and the cursor or blinking goes to the left edge of the display (in the first line if 2 lines are displayed). It also sets I/D to 1 (increment mode) in entry mode.
HD44780U Cursor or Display Shift Cursor or display shift shifts the cursor position or display to the right or left without writing or reading display data (Table 7). This function is used to correct or search the display. In a 2-line display, the cursor moves to the second line when it passes the 40th digit of the first line. Note that the first and second line displays will shift at the same time. When the displayed data is shifted repeatedly each line moves only horizontally.
HD44780U RS Clear display Code 0 RS Return home Code 0 RS Entry mode set Code 0 RS Display on/off control Code 0 RS Cursor or display shift Code 0 RS Function set Code 0 RS Set CGRAM address Code 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 * Note: * Don’t care.
HD44780U Set DDRAM Address Set DDRAM address sets the DDRAM address binary AAAAAAA into the address counter. Data is then written to or read from the MPU for DDRAM. However, when N is 0 (1-line display), AAAAAAA can be 00H to 4FH. When N is 1 (2-line display), AAAAAAA can be 00H to 27H for the first line, and 40H to 67H for the second line.
HD44780U Cursor 5 × 8 dot character font 5 × 10 dot character font Alternating display Cursor display example Blink display example Figure 12 Cursor and Blinking RS Set DDRAM address Code 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 A A A A Higher order bit RS Read busy flag and address Code 0 A A Lower order bit R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 BF A A A Higher order bit Figure 13 Instruction (2) 30 A A A A Lower order bit A
HD44780U Write Data to CG or DDRAM Write data to CG or DDRAM writes 8-bit binary data DDDDDDDD to CG or DDRAM. To write into CG or DDRAM is determined by the previous specification of the CGRAM or DDRAM address setting. After a write, the address is automatically incremented or decremented by 1 according to the entry mode. The entry mode also determines the display shift. Read Data from CG or DDRAM Read data from CG or DDRAM reads 8-bit binary data DDDDDDDD from CG or DDRAM.
HD44780U Interfacing the HD44780U Interface to MPUs + , & % 0)* # • Interfacing to an 8-bit MPU See Figure 16 for an example of using a I/O port (for a single-chip microcomputer) as an interface device. In this example, P30 to P37 are connected to the data bus DB0 to DB7, and P75 to P77 are connected to E, R/W, and RS, respectively.
HD44780U • Interfacing to a 4-bit MPU The HD44780U can be connected to the I/O port of a 4-bit MPU. If the I/O port has enough bits, 8-bit data can be transferred. Otherwise, one data transfer must be made in two operations for 4-bit data. In this case, the timing sequence becomes somewhat complex. (See Figure 17.) See Figure 18 for an interface example to the HMCS4019R. Note that two cycles are needed for the busy flag check as well as for the data transfer. The 4-bit operation is selected by the program.
HD44780U Interface to Liquid Crystal Display Character Font and Number of Lines: The HD44780U can perform two types of displays, 5 × 8 dot and 5 × 10 dot character fonts, each with a cursor. Up to two lines are displayed for 5 × 8 dots and one line for 5 × 10 dots. Therefore, a total of three types of common signals are available (Table 9). The number of lines and font types can be selected by the program. (See Table 6, Instructions.
HD44780U Since five segment signal lines can display one digit, one HD44780U can display up to 8 digits for a 1-line display and 16 digits for a 2-line display. The examples in Figure 19 have unused common signal pins, which always output non-selection waveforms. When the liquid crystal display panel has unused extra scanning lines, connect the extra scanning lines to these common signal pins to avoid any undesirable effects due to crosstalk during the floating state.
HD44780U Connection of Changed Matrix Layout: In the preceding examples, the number of lines correspond to the scanning lines. However, the following display examples (Figure 20) are made possible by altering the matrix layout of the liquid crystal display panel. In either case, the only change is the layout. The display characteristics and the number of liquid crystal display characters depend on the number of common signals or on duty factor.
HD44780U Power Supply for Liquid Crystal Display Drive Various voltage levels must be applied to pins V1 to V5 of the HD44780U to obtain the liquid crystal display drive waveforms. The voltages must be changed according to the duty factor (Table 10). VLCD is the peak value for the liquid crystal display drive waveforms, and resistance dividing provides voltages V1 to V5 (Figure 21).
HD44780U Relationship between Oscillation Frequency and Liquid Crystal Display Frame Frequency The liquid crystal display frame frequencies of Figure 22 apply only when the oscillation frequency is 270 kHz (one clock pulse of 3.7 µs). 1/8 duty cycle COM1 400 clocks 1 2 3 4 8 1 2 11 1 2 1 2 VCC V1 V2 (V3) V4 V5 1 frame 1 frame = 3.7 µs × 400 × 8 = 11850 µs = 11.9 ms 1 Frame frequency = = 84.3 Hz 11.9 ms 1/11 duty cycle COM1 400 clocks 1 2 3 4 VCC V1 V2 (V3) V4 V5 1 frame 1 frame = 3.
HD44780U Instruction and Display Correspondence • 8-bit operation, 8-digit × 1-line display with internal reset Refer to Table 11 for an example of an 8-digit × 1-line display in 8-bit operation. The HD44780U functions must be set by the function set instruction prior to the display. Since the display data RAM can store data for 80 characters, as explained before, the RAM can be used for displays such as for advertising when combined with the display shift operation.
HD44780U Table 11 Step No. RS 8-Bit Operation, 8-Digit × 1-Line Display Example with Internal Reset Instruction R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display Operation 1 Power supply on (the HD44780U is initialized by the internal reset circuit) Initialized. No display. 2 Function set 0 0 0 Sets to 8-bit operation and selects 1-line display and 5 × 8 dot character font. (Number of display lines and character fonts cannot be changed after step #2.
HD44780U Table 11 Step No.
HD44780U Table 12 Step No. RS 4-Bit Operation, 8-Digit × 1-Line Display Example with Internal Reset Instruction R/W DB7 DB6 DB5 DB4 Display Operation 1 Power supply on (the HD44780U is initialized by the internal reset circuit) Initialized. No display. 2 Function set 0 0 0 0 1 0 Sets to 4-bit operation. In this case, operation is handled as 8 bits by initialization, and only this instruction completes with one write.
HD44780U Table 13 Step No. RS 8-Bit Operation, 8-Digit × 2-Line Display Example with Internal Reset Instruction R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display Operation 1 Power supply on (the HD44780U is initialized by the internal reset circuit) Initialized. No display. 2 Function set 0 0 0 Sets to 8-bit operation and selects 2-line display and 5 × 8 dot character font.
HD44780U Table 13 Step No. RS 9 8-Bit Operation, 8-Digit × 2-Line Display Example with Internal Reset (cont) Instruction R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display Write data to CGRAM/DDRAM 1 0 0 1 0 0 10 11 12 13 44 1 0 1 · · · · · HITACHI M_ 1 1 1 1 HITACHI MICROCO_ Entry mode set 0 0 0 0 0 1 1 1 HITACHI MICROCO_ Write data to CGRAM/DDRAM 1 0 0 1 0 0 1 1 0 1 ITACHI ICROCOM_ 0 0 · · · · · Return home 0 0 0 0 0 Writes M.
HD44780U Initializing by Instruction If the power supply conditions for correctly operating the internal reset circuit are not met, initialization by instructions becomes necessary. Refer to Figures 23 and 24 for the procedures on 8-bit and 4-bit initializations, respectively. Power on Wait for more than 40 ms after VCC rises to 2.7 V Wait for more than 15 ms after VCC rises to 4.5 V RS R/WDB7 DB6 DB5 DB4 DB3DB2 DB1 DB0 0 0 0 0 1 1 * * * * BF cannot be checked before this instruction.
HD44780U Power on Wait for more than 15 ms after VCC rises to 4.5 V RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 1 Wait for more than 40 ms after VCC rises to 2.7 V BF cannot be checked before this instruction. Function set (Interface is 8 bits long.) Wait for more than 4.1 ms RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 1 BF cannot be checked before this instruction. Function set (Interface is 8 bits long.) Wait for more than 100 µs RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 1 BF cannot be checked before this instruction.
HD44780U Absolute Maximum Ratings* Item Symbol Value Unit Notes Power supply voltage (1) VCC–GND –0.3 to +7.0 V 1 Power supply voltage (2) VCC–V5 –0.3 to +13.0 V 1, 2 Input voltage Vt –0.3 to VCC +0.3 V 1 Operating temperature Topr –30 to +75 °C Storage temperature Tstg –55 to +125 °C Note: * 4 If the LSI is used above these absolute maximum ratings, it may become permanently damaged.
HD44780U DC Characteristics (VCC = 2.7 to 4.5 V, Ta = –30 to +75°C*3) Item Symbol Min Typ Max Unit Input high voltage (1) (except OSC1) VIH1 0.7V CC — VCC V 6 Input low voltage (1) (except OSC1) VIL1 –0.3 — 0.55 V 6 Input high voltage (2) (OSC1) VIH2 0.7V CC — VCC V 15 Input low voltage (2) (OSC1) VIL2 — — 0.2V CC V 15 Output high voltage (1) VOH1 (DB0–DB7) 0.75V CC — — V –I OH = 0.1 mA 7 Output low voltage (1) (DB0–DB7) — — 0.2V CC V I OL = 0.
HD44780U AC Characteristics (VCC = 2.7 to 4.5 V, Ta = –30 to +75°C*3) Clock Characteristics Item Symbol Min Typ Max Unit External External clock frequency clock External clock duty operation External clock rise time f cp 125 250 350 kHz Duty 45 50 55 % t rcp — — 0.2 µs t fcp — — 0.
HD44780U Interface Timing Characteristics with External Driver Item Symbol Min Typ Max Unit Test Condition High level t CWH 800 — — ns Figure 27 Low level t CWL 800 — — Clock set-up time t CSU 500 — — Data set-up time t SU 300 — — Data hold time t DH 300 — — M delay time t DM –1000 — 1000 Clock rise/fall time t ct — — 200 Clock pulse width Power Supply Conditions Using Internal Reset Circuit Item Symbol Min Typ Max Unit Test Condition Power supply rise tim
HD44780U DC Characteristics (VCC = 4.5 to 5.5 V, Ta = –30 to +75°C*3) Item Symbol Min Typ Max Unit Input high voltage (1) (except OSC1) VIH1 2.2 — VCC V 6 Input low voltage (1) (except OSC1) VIL1 –0.3 — 0.6 V 6 Input high voltage (2) (OSC1) VIH2 VCC–1.0 — VCC V 15 Input low voltage (2) (OSC1) VIL2 — — 1.0 V 15 Output high voltage (1) VOH1 (DB0–DB7) 2.4 — — V –I OH = 0.205 mA 7 Output low voltage (1) (DB0–DB7) — — 0.4 V I OL = 1.
HD44780U AC Characteristics (VCC = 4.5 to 5.5 V, Ta = –30 to +75°C*3) Clock Characteristics Item Symbol Min Typ Max Unit External External clock frequency clock External clock duty operation External clock rise time f cp 125 250 350 kHz 11 Duty 45 50 55 % 11 t rcp — — 0.2 µs 11 t fcp — — 0.2 µs 11 190 270 350 kHz External clock fall time Rf Clock oscillation frequency f OSC oscillation Note: * Test Condition Notes* Rf = 91 kΩ VCC = 5.
HD44780U Interface Timing Characteristics with External Driver Item Symbol Min Typ Max Unit Test Condition High level t CWH 800 — — ns Figure 27 Low level t CWL 800 — — Clock set-up time t CSU 500 — — Data set-up time t SU 300 — — Data hold time t DH 300 — — M delay time t DM –1000 — 1000 Clock rise/fall time t ct — — 100 Clock pulse width Power Supply Conditions Using Internal Reset Circuit Item Symbol Min Typ Max Unit Test Condition Power supply rise tim
HD44780U Electrical Characteristics Notes 1. All voltage values are referred to GND = 0 V. VCC B V1 A = VCC –V5 B = VCC –V1 A ≥ 1.5 V B ≤ 0.25 × A A V5 2. 3. 4. 5. The conditions of V1 and V5 voltages are for proper operation of the LSI and not for the LCD output level. The LCD drive voltage condition for the LCD output level is specified as LCD voltage VLCD. VCC ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 must be maintained. For die products, specified at 75°C.
HD44780U 6. Applies to input pins and I/O pins, excluding the OSC1 pin. 7. Applies to I/O pins. 8. Applies to output pins. 9. Current flowing through pull–up MOSs, excluding output drive MOSs. 10. Input/output current is excluded. When input is at an intermediate level with CMOS, the excessive current flows through the input circuit to the power supply. To avoid this from happening, the input level must be fixed high or low. 11. Applies only to external clock operation. Th Oscillator Open Tl OSC1 0.
HD44780U 13. RCOM is the resistance between the power supply pins (VCC, V1, V4, V5) and each common signal pin (COM1 to COM16). RSEG is the resistance between the power supply pins (VCC, V2, V3, V5) and each segment signal pin (SEG1 to SEG40). 14. The following graphs show the relationship between operation frequency and current consumption. VCC = 3 V 1.8 1.6 1.6 1.4 1.4 1.2 1.2 1.0 max. 0.8 typ. 0.6 ICC (mA) ICC (mA) VCC = 5 V 1.8 1.0 0.8 0.6 0.4 0.4 0.2 0.2 0.
HD44780U Load Circuits Data Bus DB0 to DB7 VCC = 5 V For VCC = 4.5 to 5.5 V For VCC = 2.7 to 4.5 V 3.
HD44780U Timing Characteristics VIH1 VIL1 RS VIH1 VIL1 tAS R/W tAH VIL1 VIL1 PWEH tAH tEf VIH1 VIL1 E VIH1 VIL1 tEr tH tDSW VIH1 VIL1 DB0 to DB7 VIL1 VIH1 VIL1 Valid data tcycE Figure 25 Write Operation VIH1 VIL1 RS VIH1 VIL1 tAS tAH VIH1 R/W VIH1 PWEH tAH tEf VIH1 VIL1 E VIH1 VIL1 VIL1 tEr tDHR tDDR DB0 to DB7 VOH1 VOL1 * Valid data tcycE Note: * VOL1 is assumed to be 0.8 V at 2 MHz operation.
HD44780U tct VOH2 CL1 VOH2 VOL2 tCWH tCSU CL2 tCWH VOH2 VOL2 tCWL tct tCSU VOH2 VOL2 D tDH tSU VOH2 M t DM Figure 27 Interface Timing with External Driver VCC 2.7 V/4.5 V*2 0.2 V 0.2 V 0.2 V tOFF*1 trcc 0.1 ms ≤ trcc ≤ 10 ms tOFF ≥ 1 ms Notes: 1. tOFF compensates for the power oscillation period caused by momentary power supply oscillations. 2. Specified at 4.5 V for 5-V operation, and at 2.7 V for 3-V operation. 3. For if 4.
