PRELIMINARY ISD5100 SERIES SINGLE-CHIP 1 TO 16 MINUTES DURATION VOICE RECORD/PLAYBACK DEVICES WITH DIGITAL STORAGE CAPABILITY -1- Publication Release Date: October, 2003 Revision 0.
ISD5100 – SERIES 1. GENERAL DESCRIPTION The ISD5100 ChipCorder Series provide high quality, fully integrated, single-chip Record/Playback solutions for 1- to 16-minute messaging applications that are ideal for use in cellular phones, automotive communications, GPS/navigation systems and other portable products.
ISD5100 – SERIES 2. FEATURES Fully-Integrated Solution • • • Single-chip voice record/playback solution Dual storage of digital and analog data Durations 8 to 16-minute (ISD5116) 4 to 8-minute (ISD5108) 2 to 4-minute (ISD5104) 1 to 2-minute (ISD5102) Low Power Consumption • • • • • +2.7 to +3.3V (VCC) Supply Voltage Supports 2.0V and 3.
ISD5100 – SERIES 3. BLOCK DIAGRAM ISD5100-Series Block Diagram FTHRU INP FILTO MICROPHONE 1 (AGPD) AGCCAP INP (S1M0 S1M1 ) FILTO ANA IN 1 (INS0) AUX IN AMP ARRAY 1 (AXPD) 2 SUM1 ARRAY 2 1 (FLS0) ( S1S0 S1S1 ) SUM2 (ANALOG) SUM2 ( S2M0 S2M1 ) 3 ( ) AOS0 AOS1 AOS2 Array I/OMux 64-bit/samp. SUM2 64-bit/samp. VOL ARRAY OUT (DIGITAL) ANA IN INP ANA IN 2 SUM2 2 Power Conditioning VCCA VSSA VSSA VSSD VSSD Volume Control Vol MUX 0.625/0.883/1.25/1.
ISD5100 – SERIES 4. TABLE OF CONTENTS 1. GENERAL DESCRIPTION...................................................................................................................2 2. FEATURES ..........................................................................................................................................3 3. BLOCK DIAGRAM................................................................................................................................4 4. TABLE OF CONTENTS ................
ISD5100 – SERIES 7.4.6. Ana Out Description ..............................................................................................................33 7.4.7. Analog Inputs ........................................................................................................................33 7.5. Digital Mode .................................................................................................................................36 7.5.1. Erasing Digital Data .................................
ISD5100 – SERIES 5.
ISD5100 – SERIES 6. PIN DESCRIPTION Pin Name SCL A1 SDA SOIC/PDIP 1 2 3 TSOP 8 9 10 A0 VSSD NC MIC+ VSSA MICANA OUT+ ANA OUTACAP 4 5,6 7,21,22 8 9,15,23 10 11 12 13 11 12,13 1,14,28 16 2,15,22 17 18 19 20 SP- 14 21 SP+ VCCA 16 17 23 24 ANA IN AUX IN AUX OUT 18 19 20 25 26 27 RAC 24 3 25 4 XCLK 26 5 VCCD 27,28 6,7 INT [1] Functionality I2C Serial Clock Line: to clock the data into and out of the I2C interface. Input pin that supplies the LSB +1 bit for the I2C Slave Address.
ISD5100 – SERIES 7. FUNCTIONAL DESCRIPTION 7.1. OVERVIEW 7.1.1 Speech/Voice Quality The ISD5100 ChipCorder Series can be configured via software to operate at 4.0, 5.3, 6.4 or 8.0 kHz sampling frequency to select appropriate voice quality. Increasing the duration decreases the sampling frequency and bandwidth, which affects audio quality. The table in the following section shows the relationship between sampling frequency, duration and filter pass band. 7.1.2.
ISD5100 – SERIES interface. These are the RAC timing pin and the INT pin for interrupts to the controller. Communications with all the internal registers of any operations are through the serial bus, as well as digital memory Read and Write operations. 7.1.5. Programming The ISD5100 Series are also ideal for playback-only applications, where single or multiple messages may be played back when desired. Playback is controlled through the I2C interface.
ISD5100 – SERIES operation, voice from Mic inputs are fed to AUX OUT and transmitted to the phone line, while message from other party is input from the AUX IN, then fed through to the speaker for listening. The ISD5100 device has the flexibility for other applications, because the audio paths can be configured differently, with each circuit block being powered-up or –down individually, according to the applications requirement. 7.2.1.
ISD5100 – SERIES Digital data is sent and received serially over the I2C interface. The data is serial-to-parallel converted and stored in one of two alternating (commutating) 64-bit shift registers. When an input register is full, it becomes the register that is parallel written into the array. The prior write register becomes the new serial input register. A mechanism is built-in to ensure there is always a register available for storing new data.
ISD5100 – SERIES Pinout Table A1 A0 Slave Address R/W Bit HEX Value 0 0 <100 0000> 0 80 0 1 <100 0001> 0 82 1 0 <100 0010> 0 84 1 1 <100 0011> 0 86 0 0 <100 0000> 1 81 0 1 <100 0001> 1 83 1 0 <100 0010> 1 85 1 1 <100 0011> 1 87 ISD5100 Series I2C Operation Definitions There are many control functions used to operate the ISD5100-Series. Among them are: 7.3.1.1.
ISD5100 – SERIES Note that the processor could have sent an I2C STOP after the Status Word data transfer and aborted the transfer of the Address bytes. Conventions used in I2C Data A graphical representation of this operation is found below. See the caption box above for more explanation.
ISD5100 – SERIES 7.3.1.2. Load Command Byte Register (Single Byte Load): A single byte may be written to the Command Byte Register in order to power up the device, start or stop Analog Record (if no address information is needed), or do a Message Cueing function. The Command Byte Register is loaded as follows: S SLAVE ADDRESS W A DATA A P 1. Host executes I2C START 2. Send Slave Address with R/W bit = “0” (Write) [80h] Command Byte 3. Slave responds back with an ACK. 4. Wait for SCL to go HIGH 5.
ISD5100 – SERIES 7.3.2. I2C Control Registers The ISD5100 Series are controlled by loading commands to, or, reading from, the internal command, configuration and address registers. The Command byte sent is used to start and stop recording, write or read digital data and perform other functions necessary for the operation of the device. Command Byte Control of the ISD5100 Series are implemented through an 8-bit command byte, sent after the 7-bit device address and the 1-bit Read/Write selection bit.
ISD5100 – SERIES Register Bits The register load may be used to modify a command sequence (such as load an address) or used with the null command sequence to load a configuration or test register. Not all registers are accessible to the user. [RG2 is always 0 as the four additional combinations are undefined.] RG2 RG1 RG0 C2 C1 C0 0 0 0 No action 0 0 1 Reserved 0 1 0 Load CFG0 0 1 1 Load CFG1 Function 7.3.3.
ISD5100 – SERIES OPCODE COMMAND BYTE TABLE Pwr Function Bits Register Bits OPCODE HEX PU DAB FN2 FN1 FN0 RG2 RG1 RG0 COMMAND BIT NUMBER CMD C7 C6 C5 C4 C3 C2 C1 C0 POWER UP 80 1 0 0 0 0 0 0 0 POWER DOWN 00 0 0 0 0 0 0 0 0 STOP (DO NOTHING) STAY ON 80 1 0 0 0 0 0 0 0 STOP (DO NOTHING) STAY OFF 00 0 0 0 0 0 0 0 0 LOAD CFG0 82 1 0 0 0 0 0 1 0 LOAD CFG1 83 1 0 0 0 0 0 1 1 RECORD ANALOG 90 1 0 0 1 0 0 0 0 RECORD ANALOG @
ISD5100 – SERIES 7.3.4. Data Bytes 2 In the I C write mode, the device can accept data sent after the command byte. If a register load option is selected, the next two bytes are loaded into the selected register. The format of the data is MSB first, the I2C standard. Thus to load DATA<15:0> into the device, DATA<15:8> is sent first, the byte is acknowledged, and DATA<7:0> is sent next. The address register consists of two bytes.
ISD5100 – SERIES 7.3.5. Configuration Resiter Bytes The configuration register bytes are defined, in detail, in the drawings of section 7.4 on page 29. The drawings display how each bit enables or disables a function of the audio paths in the ISD5100Series. The tables below give a general illustration of the bits. There are two configuration registers, CFG0 and CFG1, so there are four 8-bit bytes to be loaded during the set-up of the device.
ISD5100 – SERIES Configuration Register 1 (CFG1) D15 D14 D13 D12 D11 D10 D9 D8 D7 D 6 D5 D4 D3 D2 D1 D0 VLS1 VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLS0 FLD1 FLD0 FLPD AGPD AGC AMP Power Down Filter Power Down SAMPLE RATE (& Filter) Set up (2 bits) FILTER MUX Select SUM 2 SUMMING AMP Control (2 bits) SUM 1 SUMMING AMP Control (2 bits) SUM 1 MUX Select (2 bits) VOLUME CONTROL (3 bits) VOLUME CONT. MUX Select (2 bits) 7.3.6.
ISD5100 – SERIES Record Mode The command sequence for an Analog Record would be a four byte sequence consisting of the Slave Address (80h), the Command Byte (91h) for Record Analog @ Address, and the two address bytes. See “Load Command Byte Register (Address Load)” in section 7.3.2 on page 17. 7.3.7. Feed Through Mode The previous examples were dependent upon the device already being powered up and the various paths being set through the device for the desired operation.
ISD5100 – SERIES To select this mode, the following control bits must be configured in the ISD5100 Series configuration registers. To set up the transmit path: 1. Select the FTHRU path through the ANA OUT MUX—Bits AOS0, AOS1 and AOS2 control the state of the ANA OUT MUX. These are the D6, D7 and D8 bits respectively of Configuration Register 0 (CFG0) and they should all be ZERO to select the FTHRU path. 2. Power up the ANA OUT amplifier—Bit AOPD controls the power up state of ANA OUT.
ISD5100 – SERIES 6. Don’t Care bits—The following stages are not used in Feed Through Mode. Their bits may be set to either level. In this example, we will set all the following bits to a ZERO. (a). Bit INS0, bit D9 of CFG0 controls the Input Source Mux. (b). Bits AXG0 and AXG1 are bits D11 and D12 respectively in CFG0. They control the AUX IN amplifier gain setting. (c). Bits FLD0 and FLD1 are bits D2 and D3 respectively in CFG1. They control the sample rate and filter band pass setting. (d).
ISD5100 – SERIES 4. Power up the LOW PASS FILTER—Bit FLPD controls the power up state of the LOW PASS FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS FILTER STAGE. 5. Select the 6.4 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To enable the 6.4 kHz sample rate, D2 must be set to ONE and D3 set to ZERO. 6.
ISD5100 – SERIES 5. Power up the LOW PASS FILTER—Bit FLPD controls the power up state of the LOW PASS FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS FILTER STAGE. 6. Select the 5.3 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To enable the 5.3 kHz sample rate, D2 must be set to ZERO and D3 set to ONE. 7.
ISD5100 – SERIES 6. Power up the VOLUME CONTROL LEVEL—Bit VLPD controls the power-up state of the VOLUME CONTROL attenuator. This is Bit D0 of CFG0. This bit must be set to a ZERO to power-up the VOLUME CONTROL. 7. Select a VOLUME CONTROL LEVEL—Bits VOL0, VOL1, and VOL2 control the state of the VOLUME CONTROL LEVEL. These are bits D11, D12, and D13, respectively, of CFG1. A binary count of 000 through 111 controls the amount of attenuation through that state.
ISD5100 – SERIES 7.4. ANALOG MODE 7.4.1. Aux In and Ana In Description The AUX IN is an additional audio input to the ISD5100-Series, such as from the microphone circuit in a mobile phone “car kit.” This input has a nominal 694 mV p-p level at its minimum gain setting (0 dB). See the AUX IN Amplifier Gain Settings table on page 37. Additional gain is available in 3 dB steps (controlled by the I2C serial interface) up to 9 dB. Internal to the device Rb CCOUP=0.
ISD5100 – SERIES 7.4.2.
ISD5100 – SERIES 7.4.3. ISD5100 Series Aanalog Structure (right half) Description FILTER FILTER FILTO FILTO SUM2 SUMMING AMP MUX MUX SUM1 Σ LOW PASS FILTER ARRAY FLS0 SOURCE 0 SUM1 1 ARRAY FLPD SUM2 1 1 (FLS0) (FLPD) 2 (S2M1,S2M0) CONDITION 0 Power Up 1 Power Down ANA IN AMP XCLK FLD1 FLD0 0 0 8 KHz 3.6 KHz 0 1 6.4 KHz 2.9 KHz 1 0 5.3 KHz 2.4 KHz 1 1 4.0 KHz 1.
ISD5100 – SERIES 7.4.4.
ISD5100 – SERIES 7.4.5. Speaker and Aux Out Description Car Kit OUTPUT MUX AUX OUT (1 Vp-p Max) SP+ Sp eaker VOL ANA IN AMP FILTO SP– 2 ( OPA1, OPA0) SUM2 2 ( OPS1,OPS0) OPA1 15 14 AIG1 AIG0 AIP D 13 12 11 10 OPS1 OPS0 0 0 VOL 0 1 ANA IN 1 0 FILTO 1 1 SUM2 9 AXG1 AXG0 AXPD INS0 8 AOS2 SOURCE 7 6 AOS1 AOS0 5 4 AUX OUT 0 Power Down Power Down 0 1 3.6 VP-P @ 150 Ω Power Down 1 0 23.
ISD5100 – SERIES 7.4.6. Ana Out Description *FTHRU (1 Vp-p max. from AUX IN or ARRAY) (69 4 mV p-p max.
ISD5100 – SERIES * FTHRU 6 dB AGPD MIC+ AGCIN MIC AGC CONDITION 0 Power Up 1 Power Down MIC– 1 ( AGPD) To AutoMute ACAP (Pl ayback Only) * Di ffe re nti al Path 15 14 VLS1 VLS0 13 12 11 VOL2 VOL1 V OL0 10 S1S1 9 8 S1S0 S1M1 7 6 5 S1M0 S2M1 S2M0 4 3 2 1 0 FLS0 FLD1 FLD0 FLPD AGPD CFG1 ANA IN (Analog Input) The ANA IN pin is the analog input from the telephone chip set.
ISD5100 – SERIES 1. Gain from ANA IN to SP+/2. Gain from ANA IN to ARRAY IN 3. 0TLP Input is the reference Transmission Level Point that is used for testing. This level is typically 3 dB below clipping 4. Speaker Out gain set to 1.6 (High). (Differential) AUX IN (Auxiliary Input) The AUX IN is an additional audio input to the ISD5100-Series, such as from the microphone circuit in a mobile phone “car kit.” This input has a nominal 694 mV p-p level at its minimum gain setting (0 dB). See the following table.
ISD5100 – SERIES 7.5. DIGITAL MODE 7.5.1. Erasing Digital Data The Digital Erase command can only erase an entire page at a time. This means that the D1 command only needs to include the 11-bit page address; the 5-bit for block address are left at 00000. Once a page has been erased, each block may be written separately, 64 bits at a time. But, if a block has been previously written then the entire page of 2048 bits must be erased in order to re-write (or change) a block.
ISD5100 – SERIES 7.5.3. Reading Digital Data The Digital Read command utilizes the combined I2C command format. That is, a command is sent to the chip using the write data direction. Then the data direction is reversed by sending a repeated start condition, and the slave address with R/W set to 1. After this, the slave device (ISD5100Series) begins to send data to the master until the master generates a NACK. If the part encounters an overflow condition, the INT pin is pulled LOW.
ISD5100 – SERIES WaitACK WaitSCLHigh SendByte(row%256) - low address byte WaitACK WaitSCLHigh I2CStop repeat until the number of RAC pulses are one less than the number of rows to delete { wait RAC low WAIT RAC high } Note: If only one row is going to be erased, send the following STOP command immediately after ERASE command and skip the loop above I2CStart SendByte(0x80) - Write, Slave address zero WaitACK WaitSCLHigh SendByte(0xc0) - Stop digital erase WaitACK WaitSCLHigh I2CStop wait until erase of
ISD5100 – SERIES WaitSCLHigh SendByte(0x40) - Exit Digital Mode Command WaitACK WaitSCLHigh I2Cstop Notes 1. Erase operations must be addressed on a Row boundary. The 5 LSB bits of the Low Address Byte will be ignored. 2. I2C bus is released while erase proceeds. Other devices may use the bus until it is time to execute the STOP command that causes the end of the Erase operation. 3. Host processor must count RAC cycles to determine where the chip is in the erase process, one row per RAC cycle.
ISD5100 – SERIES S SLAVE ADDRESS W A CON A P Erase starts on falling edge of Slave acknowledge S SLAVE ADDRESS W A D1 Command Byte "N" RAC cycles Last erased row Note A DATA A DATA A High Addr. Byte P Note 2 Low Addr.
ISD5100 – SERIES SUGGESTED FLOW FOR DIGITAL ERASE IN ISD5100-Series 80,C0 ENTER DIGITAL MODE TO ERASE MULTIPLE (n) PAGES (ROWS) 80,D1,nn,nn SEND ERASE COMMAND COMMANDS NO 80 = PowerUp or Stop C0 = Enter Digital Mode D1 = Erase Digital Page@ 40 = Exit Digital Mode COUNT RAC FOR n-1 RAC\ ~ 250 uS YES 80,C0 SEND STOP COMMAND BEFORE NEXT RAC SEND STOP COMMAND BEFORE RAC NO WAIT FOR RAC NO RAC\ ~ 125 uS WAIT FOR RAC YES 80,40 80,C0 RAC\ ~ 125 uS YES EXIT DIGITAL MODE STOP COMMAND MUST BE F
ISD5100 – SERIES 7.5.4.2.
ISD5100 – SERIES I2CStart SendByte(0x80) - Write, Slave address zero WaitACK WaitSCLHigh SendByte(0x40) - Exit Digital Mode Command WaitACK WaitSCLHigh I2CStop S SLAVE ADDRESS W A W A C9h CON A Command Byte A DATA P A A Low Addr. Byte ~ ~ High Addr. Byte DATA DATA A DATA A DATA A P ~ ~ S SLAVE ADDRESS S SLAVE ADDRESS W A - 43 - 40h A P Publication Release Date: October, 2003 Revision 0.
ISD5100 – SERIES S U G G E S T E D F L O W F O R D IG IT A L W R IT E IN IS D 5 1 0 0 -S e rie s 8 0 ,C 0 8 0 ,C 9 ,n n ,n n E N T E R D IG IT A L MODE S E N D W R IT E COMMAND W / START ADDRESS C O M M AN D S 8 0 = P o w e rU p o r S to p C 0 = E n te r D ig ita l M o d e C 9 = W rite D ig ita l P a g e @ 4 0 = E x it D ig ita l M o d e SEND DATA BYTE (S E N D NE XT BYTE) W A IT fo r S C L H IG H NO BYTE COUNTER =256? YES 8 0 ,4 0 6 /2 4 /2 0 0 2 B O J R e vis io n N /C E X IT D IG IT A L MODE
ISD5100 – SERIES 7.5.4.3.
ISD5100 – SERIES } I2CStop() I2CStart SendByte(0x80) - Write, Slave address zero WaitACK WaitSCLHigh SendByte(0x40) - Exit Digital Mode WaitACK WaitSCLHigh I2CStop S S SLAVE ADDRESS SLAVE ADDRESS W A W E1h CON A A DATA P A High Addr. Byte DATA A Low Addr.
ISD5100 – SERIES S U G G E S T E D F L O W F O R D IG IT A L R E A D IN IS D 5 1 0 0 -S e rie s 8 0 ,C 0 8 0 ,E 1 ,n n ,n n E N T E R D IG IT A L MODE SEND READ COMMAND W / START ADDRESS C O M M AN D S 8 0 = P o w e rU p o r S to p C 0 = E n te r D ig ita l M o d e E 1 = R e a d D ig ita l P a g e @ 4 0 = E x it D ig ita l M o d e READ DATA BYTE (R E A D N E XT BYTE) W A IT fo r S C L H IG H NO BYTE COUNTER =256? YES 8 0 ,4 0 6 /2 4 /2 0 0 2 B O J R e vis io n N /C E X IT D IG IT A L MODE D E
ISD5100 – SERIES 7.6. PIN DETAILS 7.6.1. Digital I/O Pins SCL (Serial Clock Line) The Serial Clock Line is a bi-directional clock line. It is an open-drain line requiring a pull-up resistor to Vcc. It is driven by the "master" chips in a system and controls the timing of the data exchanged over the Serial Data Line. SDA (Serial Data Line) The Serial Data Line carries the data between devices on the I2C interface. Data must be valid on this line when the SCL is HIGH.
ISD5100 – SERIES RAC Waveform During Digital Erase @ 8kHz Operation 1.25 ms TRACE .25 ms TRACEL INT (Interrupt) INT is an open drain output pin. The ISD5100 Series interrupt pin goes LOW and stays LOW when an Overflow (OVF) or End of Message (EOM) marker is detected. Each operation that ends in an EOM or OVF generates an interrupt, including the message cueing cycles. The interrupt is cleared by a READ STATUS instruction that will give a status byte out the SDA line.
ISD5100 – SERIES A0, A1 (Address Pins) These two pins are normally strapped for the desired address that the ISD5100 Series will have on the I2C serial interface. If there are four of these devices on the bus, then each must be strapped differently in order to allow the Master device to address them individually. The possible addresses range from 80h to 87h, depending upon whether the device is being written to, or read from, by the host.
ISD5100 – SERIES ACAP (AGC Capacitor) This pin provides the capacitor connection for setting the parameters of the microphone AGC circuit. It should have a 4.7 µF capacitor connected to ground. It cannot be left floating. This is because the capacitor is also used in the playback mode for the AutoMute circuit. This circuit reduces the amount of noise present in the output during quiet pauses.
ISD5100 – SERIES ANA IN (Analog Input) The ANA IN pin is the analog input from the telephone chip set. It can be switched (by the I2C interface) to the speaker output, the array input or to various other paths. This pin is designed to accept a nominal 1.11 V p-p when at its minimum gain (6 dB) setting. There is additional gain available, if required, in 3 dB steps, up to 15 dB. The gain settings are controlled from the I2C interface. ANA IN Input Modes Internal to the device Rb CCOUP = 0.
ISD5100 – SERIES AUX IN (Auxiliary Input) The AUX IN is an additional audio input to the ISD5100-Series, such as from the microphone circuit in a mobile phone “car kit.” This input has a nominal 694 mV p-p level at its minimum gain setting (0 dB). See the AUX IN Amplifier Gain Settings table on page 56. Additional gain is available in 3 dB steps (controlled by the I2C interface) up to 9 dB. AUX IN Input Modes Internal to the device Rb CCOUP = 0.
ISD5100 – SERIES 7.6.3. Power and Ground Pins VCCA, VCCD (Voltage Inputs) To minimize noise, the analog and digital circuits in the ISD5100 Series devices use separate power busses. These +3 V busses lead to separate pins. Tie the VCCD pins together as close as possible and decouple both supplies as near to the package as possible. VSSA, VSSD (Ground Inputs) The ISD5100 Series utilizes separate analog and digital ground busses.
ISD5100 – SERIES 7.6.4. PCB Layout Examples For SOIC package : PC board traces and the three chip capacitors are on the bottom side of the board. 1 Note 3 Note V S S D (Digital G round) 1 Note 1: V SSD traces should be kept separated back to the V SS supply feed point.. Note 2: V CCD traces should be kept separate back to the V CC Supply feed point. Note 3: The Digital and Analog grounds tie together at the power supply.
ISD5100 – SERIES 8.TIMING DIAGRAMS 8.1.
ISD5100 – SERIES I2C INTERFACE TIMING STANDARD-MODE PARAMETER FAST-MODE UNIT SYMBOL MIN. MAX. MIN. MAX. fSCL 0 100 0 400 kHz tHD-STA 4.0 - 0.6 - µs LOW period of the SCL clock tLOW 4.7 - 1.3 - µs HIGH period of the SCL clock tHIGH 4.0 - 0.6 - µs Set-up time for a repeated START condition tSU-STA 4.7 - 0.6 - µs Data set-up time tSU-DAT 250 - 100(1) SCL clock frequency Hold time (repeated) START condition.
ISD5100 – SERIES 8.2.
ISD5100 – SERIES 8.3. EXAMPLE OF POWER UP COMMAND (FIRST 12 BITS) - 59 - Publication Release Date: October, 2003 Revision 0.
ISD5100 – SERIES 9. ABSOLUTE MAXIMUM RATINGS ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS)(1) Condition Value 0 Junction temperature 150 C Storage temperature range -650C to +1500C Voltage Applied to any pin (VSS - 0.3V) to (VCC + 0.3V) Voltage applied to any pin (Input current limited to +/-20 mA) (VSS – 1.0V) to (VCC + 1.0V) Lead temperature (soldering 3000C – 10 seconds) VCC - VSS 1. -0.3V to +5.5V Stresses above those listed may cause permanent damage to the device.
ISD5100 – SERIES OPERATING CONDITIONS (PACKAGED PARTS) Condition Commercial operating temperature range Value (1) 0 0 0 C to +70 C (1) -200C to +700C Industrial operating temperature(1) -400C to +850C Supply voltage (VCC)(2) +2.7V to +3.3V Extended operating temperature Ground voltage (VSS) 1 (3) 0V 2. . Case temperature VCC = VCCA = VCCD 3.
ISD5100 – SERIES 10. ELECTRICAL CHARACTERISTICS 10.1. GENERAL PARAMETERS Min(2) Symbol Parameters VIL Input Low Voltage VIH Input High Voltage VOL SCL, SDA Voltage VIL2V Input low interface VIH2V Input high voltage for 2V interface VOL1 RAC, INT Output Low Voltage VOH Output High Voltage ICC VCC Current (Operating) Max(2) Unit s VCC x 0.2 V VCC x 0.8 Output voltage Typ(1) for Conditions V Low 0.4 V IOL = 3 µA 2V 0.
ISD5100 – SERIES 10.2. TIMING PARAMETERS Symbol Parameters FS Sampling Frequency FCF TREC TPLAY Conditions 6.4 kHz (5) 5.3 kHz (5) 4.0 kHz (5) 8.0 kHz (sample rate) 3.4 kHz Knee Point 6.4 kHz (sample rate) 2.7 kHz Knee Point(3)(7) 5.3 kHz (sample rate) 2.3 kHz Knee Point 4.0 kHz (sample rate) 1.7 kHz Knee Point(3)(7) Filter Knee ISD5116 ISD5108 ISD5104 ISD5102 8.0 kHz (sample rate) 8.73 4.36 2.18 1.08 min (6) 6.4 kHz (sample rate) 2.72 1.
ISD5100 – SERIES 4.0 kHz (sample rate) TRACL TRACM TRACML 512 msec 8.0 kHz (sample rate) 8 msec 6.4 kHz (sample rate) 10 msec 5.3 kHz (sample rate) 12.1 msec 4.0 kHz (sample rate) 16 msec 8.0 kHz (sample rate) 500 µsec 6.4 kHz (sample rate) 625 µsec 5.3 kHz (sample rate) 750 µsec 4.0 kHz (sample rate) 1000 µsec 15.6 µsec 19.5 µsec 23.4 µsec 31.2 µsec 8.0 kHz (sample rate) 1.25 msec 6.4 kHz (sample rate) 1.56 msec 5.3 kHz (sample rate) 1.87 msec 4.
ISD5100 – SERIES 10.3. ANALOG PARAMETERS MICROPHONE INPUT(14) Min(2) Symbol Parameters VMIC+/- MIC +/- Input Voltage VMIC (0TLP) MIC +/- input reference transmission level point (0TLP) AMIC Gain from MIC +/- input to ANA OUT AMIC (GT) MIC +/- Gain Tracking RMIC Microphone input resistance AAGC Microphone AGC Amplifier Range Typ(1)(14) Max(2) Units 300 mV Peak-to-Peak(4)(8) mV Peak-to-Peak(4)(10) 208 5.5 6.0 6.5 dB Conditions 1 kHz (4) (0TLP) at VMIC +/-0.
ISD5100 – SERIES AUX IN(14) Min(2) Symbol Parameters VAUX IN AUX IN Input Voltage VAUX IN (0TLP) AUX IN Voltage Input AAUX IN (ANA OUT) Gain from AUX IN to ANA OUT AAUX IN (GA) AUX IN Gain Accuracy AAUX IN (GT) AUX IN Gain Tracking RAUX IN AUX IN Input Resistance (0TLP) Typ(1)(14) Max(2) Units 1.0 V Peak-to-Peak (0 dB gain setting) 694.2 mV Peak-to-Peak (0 dB gain setting) 0 to +9 dB 4 Steps of 3 dB dB (11) +/-0.
ISD5100 – SERIES VCC and VCC pins FR Frequency Response (3003400 Hz) dB +0.5 With 0TLP input to ANA IN, 6 dB setting (12) Guaranteed design by POUTLG Power Output (Low Gain Setting) 23.5 mW RMS Differential load at 8Ω SINAD SINAD ANA IN to SP+/- 62.5 dB 0TLP ANA In input minimum gain, 150Ω load (12)(13) ANA OUT (14) Min (2) Max (2) Symbol Parameters SINAD SINAD, MIC IN to ANA OUT 62.5 dB Load = 5kΩ(12)(13) SINAD SINAD, AUX IN to ANA OUT (0 to 9 dB) 62.
ISD5100 – SERIES CRTANA OUT/AUX OUT ANA OUT to AUX OUT Cross Talk -65 dB Max(2) Units 1.
ISD5100 – SERIES Conditions 1. Typical values: TA = 25°C and Vcc = 3.0V. 2. All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100 percent tested. 3. Low-frequency cut off depends upon the value of external capacitors (see Pin Descriptions). 4. Differential input mode. Nominal differential input is 208 mV p-p. (0TLP) 5. Sampling frequency can vary as much as –6/+4 percent over the industrial temperature and voltage ranges.
ISD5100 – SERIES SDA SCL data line stable; data valid changed of data allowed Bit transfer on the I2C-Bus Start and stop conditions Both data and clock lines remain HIGH when the interface bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P).
ISD5100 – SERIES LCD DRIVER MICROCONTROLLER STATIC RAM OR EEPROM SDA SCL GATE ARRAY ISD 5116 2 Example of an I C-bus configuration using two microcontrollers Acknowledge The number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit.
ISD5100 – SERIES 10.5. I2C PROTOCOL Since the I2C protocol allows multiple devices on the bus, each device must have an address. This address is known as a “Slave Address”. A Slave Address consists of 7 bits, followed by a single bit that indicates the direction of data flow. This single bit is 1 for a Write cycle, which indicates the data is being sent from the current bus master to the device being addressed.
ISD5100 – SERIES Master Reads from Slave immediately after first byte (Read Mode) acknowledgement from slave From Slave S SLAVE ADDRESS R A From Slave STATUS W ORD A From Slave High ADDR.
ISD5100 – SERIES 11. TYPICAL APPLICATION CIRCUIT Recording via Microphone 1 2 3 To µC I2C Interface & Address Setting 4 SCL SDA RAC A1 A0 INT VCC VCC 1.5KΩ 1.5KΩ 220 µF To µ C I/O for message management (optional) 24 25 Electret microphone 0.1µF 0.1µF 8 10 VCCD MIC+ 51XX MIC- VSSD VSSD VSSA 1.5KΩ 4.7µF 13 VCCD VCCA ACAP VSSA VSSA SP+ SP- 27 28 0.1µF 17 5 6 0.1µF 9 15 23 16 14 SOIC / PDIP Please see web site www.winbond-usa.com for updates.
ISD5100 – SERIES 12. PACKAGE SPECIFICATION 12.1. 28-LEAD 8X13.4MM PLASTIC THIN SMALL OUTLINE PACKAGE (TSOP) TYPE 1 A A B B G G 1 22 33 44 55 66 77 88 99 10 10 11 11 12 12 13 13 14 14 28 28 27 27 26 26 25 25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 17 16 16 15 15 F C E E D JJ H H I Plastic Thin Small Outline Package (TSOP) Type 1 Dimensions INCHES M ILLIM ETERS M in Nom M ax M in Nom M ax A 0.520 0.528 0.535 13.20 13.40 13.60 B 0.461 0.465 0.469 11.70 11.80 11.90 C 0.311 0.
ISD5100 – SERIES 12.2. 28-LEAD 300-MIL PLASTIC SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 2 3 4 5 1 6 7 8 9 10 11 12 13 14 A G C B D E H F Plastic Small Outline Integrated Circuit (SOIC) Dimensions INCHES MILLIMETERS Min Nom Max Min Nom Max A 0.701 0.706 0.711 17.81 17.93 18.06 B 0.097 0.101 0.104 2.46 2.56 2.64 C 0.292 0.296 0.299 7.42 7.52 7.59 D 0.005 0.009 0.0115 0.127 0.22 0.29 E 0.014 0.016 0.019 0.35 0.41 0.
ISD5100 – SERIES 12.3. 28-LEAD 600-MIL PLASTIC DUAL INLINE PACKAGE (PDIP) Plastic Dual Inline Package (PDIP) (P) Dimensions INCHES A B1 B2 C1 C2 D D1 E F G H J S 0 Min 1.445 0.065 0.600 0.530 0.015 0.125 0.015 0.055 0.008 0.070 0° Nom 1.450 0.150 0.070 0.540 0.018 0.060 0.100 0.010 0.075 MILLIMETERS Max 1.455 Min 36.70 0.075 0.625 0.550 0.19 1.65 15.24 13.46 0.135 0.022 0.065 0.38 3.18 0.38 1.40 0.012 0.080 15° 0.20 1.78 0° - 77 - Nom 36.83 3.81 1.78 13.72 0.46 1.52 2.54 0.25 1.91 Max 36.
ISD5100 – SERIES 12.4 ISD5116 DIE INFORMATION VSSD SDA VSSD A0 VCCD SCL INT VCCD XCLK A1 RAC VSSA ISD5116 Device Die Dimensions X: 4125 µm Y: 8030 µm Die Thickness [3] 292.1 µm ± 12.7 µm Pad Opening ≈ Single pad: 90 x 90 µm Double pad: 180 x 90 µm VSSA MIC + MIC - ANA OUT - ANA OUT + ≈ ISD5116 SP ACAP VSSA [2] VCCA [2] SP + ANA IN AUX OUT AUX IN Notes 1. The backside of die is internally connected to Vss. It MUST NOT be connected to any other potential or damage may occur. 2.
ISD5100 – SERIES ISD5116 Pad Coordinates (with respect to die center in µm) Pad Pad Name X Axis Y Axis VSSA Analog Ground 1879.45 3848.65 RAC Row Address Clock 1536.20 3848.65 Interrupt 787.40 3848.65 XCLK External Clock Input 475.60 3848.65 VCCD Digital Supply Voltage 288.60 3848.65 VCCD Digital Supply Voltage 73.20 3848.65 SCL Serial Clock Line -201.40 3848.65 Address 1 -560.90 3848.65 Serial Data Address -818.20 3848.65 Address 0 -1369.40 3848.
ISD5100 – SERIES 12.5 ISD5108 DIE INFORMATION VSSD VSSD SDA SCL VCCD INT A1 VCCD XCLK A0 RAC VSSA ISD5108 Device Die Dimensions (include scribe line) X: 4230 µm Y: 6090 µm Die Thickness [3] ≈ 292.1 µm ± 12.7 µm ISD5108 ≈ Pad Opening Single pad: 90 x 90 µm Double pad: 180 x 90 µm VSSA MIC + MIC ANA OUT SP ANA OUT + ACAP VSSA [2] VCCA [2] SP + ANA IN AUX OUT AUX IN Notes 1. The backside of die is internally connected to Vss.
ISD5100 – SERIES ISD5108 Pad Coordinates (with respect to die center in µm) Pad Pad Name X Axis Y Axis VSSA Analog Ground 1882.40 2820.65 RAC Row Address Clock 1539.15 2820.65 Interrupt 790.35 2820.65 XCLK External Clock Input 478.55 2820.65 VCCD Digital Supply Voltage 291.55 2820.65 VCCD Digital Supply Voltage 76.15 2820.65 SCL Serial Clock Line -198.45 2820.65 Address 1 -557.95 2820.65 Serial Data Address -815.25 2820.65 Address 0 -1366.45 2820.
ISD5100 – SERIES 12.6 ISD5104 DIE INFORMATION VSSD VSSD VCCD SDA SCL INT A1 VCCD XCLK A0 RAC VSSA ISD5104 Device Die Dimensions (include scribe line) X: 4230 µm Y: 5046 µm ≈ Die Thickness [3] ≈ ISD5104 292.1 µm ± 12.7 µm Pad Opening Single pad: 90 x 90 µm Double pad: 180 x 90 µm VSSA MIC + MIC ANA OUT SP ANA OUT + ACAP VSSA [2] VCCA [2] SP + ANA IN AUX OUT AUX IN Notes 1. The backside of die is internally connected to Vss.
ISD5100 – SERIES ISD5104 Pad Coordinates (with respect to die center in µm) Pad Pad Name X Axis Y Axis VSSA Analog Ground 1882.4 2306.65 RAC Row Address Clock 1539.15 2306.65 Interrupt 790.35 2306.65 XCLK External Clock Input 478.55 2306.65 VCCD Digital Supply Voltage 291.55 2306.65 VCCD Digital Supply Voltage 76.15 2306.65 SCL Serial Clock Line -198.45 2306.65 Address 1 -557.95 2306.65 Serial Data Address -815.25 2306.65 Address 0 -1366.45 2306.
ISD5100 – SERIES 12.7 ISD5102 DIE INFORMATION VSSD VSSD VCCD SDA SCL INT VCCD XCLK A1 A0 RAC VSSA ISD5102 Device Die Dimensions (include scribe line) X: 4230 µm Y: 5046 µm ≈ Die Thickness [3] ≈ ISD5102 292.1 µm ± 12.7 µm Pad Opening Single pad: 90 x 90 µm Double pad: 180 x 90 µm VSSA MIC + MIC ANA OUT SP ANA OUT + ACAP VSSA [2] VCCA [2] SP + ANA IN AUX OUT AUX IN Notes 1. The backside of die is internally connected to Vss.
ISD5100 – SERIES ISD5102 Pad Coordinates (with respect to die center in µm) Pad Pad Name X Axis Y Axis VSSA Analog Ground 1882.4 2306.65 RAC Row Address Clock 1539.15 2306.65 Interrupt 790.35 2306.65 XCLK External Clock Input 478.55 2306.65 VCCD Digital Supply Voltage 291.55 2306.65 VCCD Digital Supply Voltage 76.15 2306.65 SCL Serial Clock Line -198.45 2306.65 Address 1 -557.95 2306.65 Serial Data Address -815.25 2306.65 Address 0 -1366.45 2306.
ISD5100 – SERIES 13. ORDERING INFORMATION Winbond Part Number Description I51 - } } Product Family Special Temperature Field: ISD5100-Series Blank (1- to 16-minute durations) = Commercial Packaged (0°C to +70°C) or Commercial Die (0°C to +50°C) = Industrial (–40°C to +85°C) Duration: I 16 = ISD5116 (8 to 16 min) Package Type: 08 = ISD5108 (4 to 8 min) E = 28-Lead 8x13.
ISD5100 – SERIES 14. VERSION HISTORY VERSION DATE DESCRIPTION 0.1 Mar 2003 New data sheet for the ISD5100-Series 0.
ISD5100 – SERIES The contents of this document are provided only as a guide for the applications of Winbond products. Winbond makes no representation or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to discontinue or make changes to specifications and product descriptions at any time without notice. No license, whether express or implied, to any intellectual property or other right of Winbond or others is granted by this publication.
