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I5216 SERIES

Advanced Information

PRELIMINARY

8 TO 16 MINUTE VOICE RECORD/PLAYBACK SYSTEM WITH

INTEGRATED CODEC

Publication Release Date: November 30, 2001

-1 Revision A1

GENERAL DESCRIPTION

The ChipCorder I5216 is an 8 to 16 minute Voice and Data Record and Playback system with

integrated Voice band CODEC. The device works on a single 2.7V to 3.3V supply, and has fully

integrated system functions, including: AGC, microphone preamplifier, speaker driver, memory and

CODEC. The CODEC meets the PCM conformance specification of the G.714 recommendation. Its µ-

Law and A-law compander meets the specification of the ITU-T G.711 recommendation.

FEATURES

• Single Supply 2.7 to 3.3 Volt operation

• Voice and digital data record and playback system on a single chip

• Industry-leading sound quality

• Low voltage operation

• Message management

• Fully integrated system functions

• Flexible architecture

• Nonvolatile message storage

• Configurable ChipCorder sampling rates of 4 kHz, 5.3kHz, 6.4 kHz and 8kHz

• 8, 10, 12 and 16 minutes duration

• External or internal Voice recorder clock

• I

C serial interface (400kHz)

• Configurable analog paths

• 2.2V Microphone Bias Pin

• 100 year message retention (typical)

• 100K analog record cycles (typical)

• 10K digital record cycles (typical)

• Full-duplex (not in I

S mode) single channel speech CODEC with :

o External 13.824 MHz, 27.648 MHz, 20.48 MHz or 40.96 MHz master clock

o I

S and PCM digital audio interface ports

o Serial transfer data rate from 64 to 3072 Kbps

o Short and Long frame sync formats

o 2s complement and signed magnitude data format

o Complete µ-Law and A-Law companding

o Linear 14 bit ∆Σ PCM CODEC-filter for A/D and D/A converter

o 8 kHz or 44.1 kHz – 48 kHz digital audio sampling rate options

o Analog receive and transmit gain adjust

o Configurable setup through the I

C interface

Summary of content (83 pages)

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I5216 SERIES Advanced Information PRELIMINARY 8 TO 16 MINUTE VOICE RECORD/PLAYBACK SYSTEM WITH INTEGRATED CODEC GENERAL DESCRIPTION The ChipCorder I5216 is an 8 to 16 minute Voice and Data Record and Playback system with integrated Voice band CODEC. The device works on a single 2.7V to 3.3V supply, and has fully integrated system functions, including: AGC, microphone preamplifier, speaker driver, memory and CODEC. The CODEC meets the PCM conformance specification of the G.714 recommendation.
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I5216 SERIES Advanced Information PRELIMINARY TABLE OF CONTENTS GENERAL DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................................. 1 PIN LAYOUT & DESCRIPTIONS ............................................................................................ 4 I5216 BLOCK DIAGRAMS...........................................
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I5216 SERIES Advanced Information PRELIMINARY AUTO MUTE & AUTO GAIN FUNCTIONS ............................................................. ............ 37 VOLUME CONTROL DESCRIPTION ..................................................................... ............ 38 SPEAKER & AUX OUT DESCRIPTION .................................................................. ............ 39 MICROPHONE INPUTS .......................................................................................... ............
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I5216 SERIES Advanced Information PRELIMINARY ISD5216 Pin Layout VSSA SDI SDIO RAC INT MCLK VCCD VCCD SCL A1 SDA A0 VSSD VSSD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ISD5216 I5216 WS SCK NC AUX OUT AUX IN VCCA SP+ VSSA SPACAP MICBS MICMIC+ VSSA VCCD 1 28 VCCD SCL 2 27 MCLK A1 3 26 INT SDA 4 25 RAC A0 5 24 SDIO VSSD 6 23 SDI VSSD 7 22 VSSA VSSA 8 21 WS MIC+ 9 20 SCK MIC- ISD5216 I5216 10 19 NC MICBS 11 18 AUX OUT ACAP 12
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I5216 SERIES Advanced Information PRELIMINARY PIN DESCRIPTION Pin Name Pin No. Pin No. Pin No.
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I5216 SERIES Advanced Information PRELIMINARY BLOCK DIAGRAMS I5216 Block Diagram 2.2V Voltage reference MICBS 1 MICROPHONE (AGPD) MIC IN 1 (AGPD) AGCCAP 2 FILTO 1 ARRAY ( S1M0 S1M1 ) (INS0) AUX IN AMP 1 DAO (AXPD) ( AXG0 AXG1) MIC+ MIC- ARRAY 1 1 (FLS0) ( ) 2( FLD0 FLD1 ) (AMT0) SUM2 Program/Read Control (DIGITAL) VOL 2 x 64-bit reg.
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I5216 SERIES Advanced Information PRELIMINARY I5216 CODEC DIAGRAM µ/A-Law Expander or linear ( ) Digital Smoothing Interpolation Filter 14 bit Digital Σ∆ Demodulator ( MUTE ) ( Digital Anti-Aliasing Decimation Filter ( MUTE ) 1 1 (DAPD) Anti Aliasing Filter 1 CIG0 CIG1 CIG2 ) ( 1 (ADPD) HPF0 HSR0 ( COG0 COG1 COG2 ) 1 bit ) 2 ) µ/A-Law Compressor or linear SDIO SDI 8 bits or 16 bits Digital PLL WS (CKD2) 1 1 SCK (HSR0) 1 LAW0 LAW1 2 ( Sample frequency 14 bit PCM
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I5216 SERIES Advanced Information PRELIMINARY FUNCTIONAL DESCRIPTION O The I5216 ChipCorder Product provides high quality, fully integrated, single-chip Record/Playback solutions for 8- to 16-minute messaging applications that are ideal for use in PBX systems, cellular phones, automotive communications, GPS/navigation systems, and other portable products.
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I5216 SERIES Advanced Information PRELIMINARY FLASH STORAGE One of the benefits of Winbond’s ChipCorder technology is the use of on-chip nonvolatile memory, which provides zero-power message storage. A message is retained for up to 100 years (typically) without power. In addition, the device can be re-recorded over 10,000 times (typically) for digital messages and over 100,000 times (typically) for analog messages.
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I5216 SERIES Advanced Information PRELIMINARY INT SCL SDA Starting at the MICROPHONE inputs, the input signal at the MICROPHONE inputs can be routed in the following ways: • directly through the Voice band CODEC of the I5216 chip, then through the SDIO pin, to output the digital PCM signal. • through the AGC amplifier, before it is routed to the voice band CODEC.
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I5216 SERIES Advanced Information PRELIMINARY TRANSFORMER APPLICATION To Microcontroller I2C interface and Vcc Address setting .1µF .1µF 3 4 5 6 7 8 9 1.5kΩ .1µF Electret Microphone 10 11 12 13 14 WM-54B Panasonic .1µF 1.5kΩ 1 2 28 27 MCLK 26 VCCD VCCD SCL 4.7KΩ 4.7KΩ INT A1 25 SDA RAC A0 SDIO 24 23 VSSD ISD521 VSSA 22 VSSA WS 21 MIC+ SCK 20 MICNC 19 18 MICBS AUX OUT ACAP AUX IN 17 16 VCCA SP15 VSSD SDI SP+ VSSA 1µF 13.824 MHz Vcc Vcc PCM OUT PCM IN 8 KHz 2.
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I5216 SERIES Advanced Information PRELIMINARY HANDSET APPLICATION To Microcontroller I2C interface and Vcc Address setting .1µF .1µF 1.5kΩ .1µF 1 2 3 4 5 6 7 8 9 Electret Microphone 10 11 12 13 14 WM-54B Panasonic .1µF 1.5kΩ VCCD VCCD 26 RAC 25 SDIO 24 23 SDI A1 4.7KΩ 4.7KΩ INT SDA A0 VSSD VSSD 28 MCLK 27 SCL 13.824 MHz Vcc Vcc PCM OUT PCM IN 22 21 20 SCK 19 VSSA ISD521 VSSA 8 KHz WS MIC+ MIC- 2.
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I5216 SERIES Advanced Information PRELIMINARY CAR STEREO APPLICATION To Microcontroller I2C interface and Vcc Address setting .1µF .1µF 4 5 6 1.5kΩ 7 8 .1µF 9 10 11 12 13 14 Electret Microphone WM-54B Panasonic .1µF 1.5kΩ 1 2 3 VCCD 28 MCLK 27 VCCD SCL 26 RAC 25 24 SDIO 23 4.7KΩ 4.7KΩ INT A1 SDA A0 VSSD SDI VSSD VSSA ISD521 VSSA WS MIC+ SCK MIC- NC MICBS AUX OUT ACAP AUX IN SP- VCCA VSSA SP+ 22 21 20 19 18 17 16 15 20.48 MHz Vcc Vcc I2S SERIAL I/O 48 KHz 3.072 MHz .
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I5216 SERIES Advanced Information PRELIMINARY INTERNAL REGISTERS The following tables provide a general illustration of the bits. There are three configuration registers: CFG0, CFG1 and CFG2. Thus, there are six 8-bit bytes to be loaded during the set-up of the device. CFG0 Bit no. Signal Description D0 (LSB) VLPD Power down the Volume Control. D1 OPA0 Power down Speaker driver and/or Auxiliary output. D2 OPA1 Power down Speaker driver and/or Auxiliary output.
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I5216 SERIES Advanced Information PRELIMINARY CFG1 Bit no.
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I5216 SERIES Advanced Information PRELIMINARY CFG2 Bit no.
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I5216 SERIES Advanced Information PRELIMINARY MEMORY ORGANIZATION The I5216 memory array is arranged as 1888 rows (or pages) of 2048 bits, for a total memory of 3,866,624 bits. The primary addressing for the 2048 pages is handled by 11 bits of address data in the analog mode. At the 8 kHz sample rate, each page contains 256 milliseconds of audio. Thus, at 8 kHz there is actually room for 8 minutes and 3 seconds of audio.
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I5216 SERIES Advanced Information PRELIMINARY I2C SLAVE ADDRESS The I5216 has a 7 bit slave address of <100 00xy> where x and y are equal to the state, respectively, of the external address pins A1 and A0. Because all data bytes are required to be 8 bits, the LSB of the address byte is the Read/Write selection bit that tells the slave whether to transmit or receive data.
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I5216 SERIES Advanced Information PRELIMINARY I2C OPERATION DEFINTIONS There are many control functions used to operate the I5216. Among them are the following. 2 Conventions used in I C Data Transfer Diagrams READ STATUS COMMAND: The read status command is a read request from the Host processor to the I5216 without delivering a Command Byte. The Host supplies all of the clocks (SCL). In each case, the entity sending the data drives the data line (SDA).
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I5216 SERIES Advanced Information PRELIMINARY LOAD COMMAND BYTE REGISTER (Single Byte Load) A single byte may be written to the Command Byte Register in order to power up the device, start or stop Analog Record (if no address information is needed), or perform a Message Cueing function. The Command Byte Register is loaded as follows: S 2 SLAVE ADDRESS 1. Host executes I C START. 2. Send Slave Address with R/W bit = “0” (Write) [80h]. 3. Slave responds back with an ACK. 4. Wait for SCL to go HIGH.
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I5216 SERIES Advanced Information PRELIMINARY I2C CONTROL REGISTERS The I5216 is controlled by loading commands to, or reading commands from the internal command, configuration and address registers. The Command byte sent is used to start and stop recording, write or read digital data and perform other functions necessary for the operation of the device.
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I5216 SERIES Advanced Information PRELIMINARY REGISTER BITS The register load may be used to modify a command sequence (such as load an address) or used with the null command sequence to load a configuration or test register. Not all registers are accessible to the user. [The remaining three codes are No Ops.
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I5216 SERIES Advanced Information PRELIMINARY OPCODE COMMAND BYTE TABLE Pwr Function Bits Register Bits OPCODE HEX PU DAB FN2 FN1 FN0 RG2 RG1 RG0 COMMAND BIT NUMBER CMD C7 C6 C5 C4 C3 C2 C1 C0 POWER UP 80 1 0 0 0 0 0 0 0 POWER DOWN 00 0 0 0 0 0 0 0 0 STOP (DO NOTHING) STAY ON 80 1 0 0 0 0 0 0 0 STOP (DO NOTHING) STAY OFF 00 0 0 0 0 0 0 0 0 LOAD ADDRESS 81 1 0 0 0 0 0 0 1 LOAD CFG0 82 1 0 0 0 0 0 1 0 LOAD CFG1 83 1 0 0
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I5216 SERIES Advanced Information PRELIMINARY 1 See Playback and Stop Cycle on page 62 for details. DATABYTES 2 In the I C write mode, the device can accept data sent after the command byte. If a register load option is selected, the next two bytes are loaded into the selected register. The format of the data is MSB first, 2 as specified by the I C standard. Thus to load DATA<15:0> into the device, DATA<15:8> is sent first, the byte is acknowledged, and DATA<7:0> is sent next.
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I5216 SERIES Advanced Information PRELIMINARY POWER-UP SEQUENCE This sequence prepares the I5216 for an operation to follow, and waits for the Tpud time before sending the next command sequence. 2 1. Send I C Start. 2. Send one byte 10000000 {Slave Address, R/W = 0} 80h. 3. Slave ACK. 4. Wait for SCL High. 5. Send one byte 10000000 {Command Byte = Power Up} 80h. 6. Slave ACK. 7. Wait for SCL High. 2 8. Send I C Stop.
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I5216 SERIES Advanced Information PRELIMINARY PLAYBACK MODE The command sequence for an analog Playback operation can be handled several ways. One technique is to do a Load Address (81h), which requires sending a total of four bytes, followed by a Play Analog, which is a Command Byte (A8h) preceded by the Slave Address Byte. This is a total of six bytes plus the times for Start, ACK, and Stop.
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I5216 SERIES Advanced Information PRELIMINARY FEED THROUGH MODE The previous examples were dependent upon the device already being powered up and the various paths being set through the device for the desired operation. To set up the device for the various paths requires loading the three 16-bit Configuration Registers with the correct data. For example, in the Feed Through Mode, the device only needs to be powered up and a few paths selected.
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I5216 SERIES Advanced Information PRELIMINARY Table A Table B CIG2 CIG1 CIG0 GAIN 0 0 0 0.80 0 0 1 1.00 0 1 0 1.20 0 1 1 1.25 1 0 0 1.40 1 0 1 1.60 1 1 0 1.80 1 1 1 2.
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I5216 SERIES Advanced Information PRELIMINARY To set up the receive path: Set up the CODEC output gain amplifier for the correct gain—Bits COG0, COG1 and COG2 control the gain settings of this amplifier. These are bits D9, D10 and D11, respectively, of CFG2. The table below will help determine the setting COG2 COG1 COG0 GAIN (dB) 0 0 0 0 0 0 1 +2 0 1 0 +4 0 1 1 +6 1 0 0 -8 1 0 1 -6 1 1 0 -4 1 1 1 -2 1. Power up the DAC—Bit DAPD controls the power up state of the DAC.
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I5216 SERIES Advanced Information PRELIMINARY 3. Power down the AUX IN amplifier—Bit AXPD controls the power up state of the AUX IN input amplifier. This is bit D10 of CFG0 and it should be set to a ONE to power down this stage. 4. Power down the SUM1 and SUM2 Mixer amplifiers—Bits S1M0 and S1M1 control the SUM1 mixer and bits S2M0 and S2M1 control the SUM2 mixer. These are bits D7 and D8 in CFG1, and bits D5 and D6 in CFG1, respectively.
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I5216 SERIES Advanced Information PRELIMINARY 1. Select the CODEC path through the SUM1 MUX—Bits S1S0 and S1S1 control the state of the SUM1 MUX. These are bits D9 and D10, respectively, of CFG1 and they should be set to the state where both D9 and D10 are ZERO to select the CODEC path. 2. Select the SUM1 MUX input (only) to the S1 SUMMING amplifier—Bits S1M0 and S1M1 control the state of the SUM1 SUMMING amplifier.
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I5216 SERIES Advanced Information PRELIMINARY 3. Select the INPUT SOURCE MUX (only) to the S1 SUMMING amplifier—Bits S1M0 and S1M1 control the state of the SUM1 SUMMING amplifier. These are bits D7 and D8, respectively, of CFG1 and they should be set to the state where D7 is ZERO and D8 is ONE to select the INPUT SOURCE MUX (only) path. 4. Select the SUM1 SUMMING amplifier path through the FILTER MUX—Bit FLS0 controls the state of the FILTER MUX.
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I5216 SERIES Advanced Information PRELIMINARY 2. Power up the LOW PASS FILTER—Bit FLPD controls the power up state of the LOW PASS FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS FILTER STAGE. 3. Select the 8.0 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To enable the 8.0 kHz sample rate, D2 and D3 must be set to ZERO. 4.
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I5216 SERIES Advanced Information PRELIMINARY MESSAGE CUEING Message cueing allows the user to skip through messages, without having to know the actual physical location of each message. This operation is used during playback. In this mode, the messages are skipped 512 times faster than in normal playback mode. This operation will stop when an EOM marker is reached. Then, the internal address counter will be pointing to the next message.
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I5216 SERIES Advanced Information PRELIMINARY I5216 ANALOG STRUCTURE (Left Half) DESCRIPTION INP AUX IN Input Source MUX AGC AMP Σ SUM1 MUX ( S1M0 S1M1 ) SUM1 2 FILTO SUM1 MUX 1 (INS0) SUM1 Summing AMP INP ARRAY DAC OUT S1M1 S1M0 0 0 0 1 SUM1 MUX ONLY 1 0 INP Only 1 1 POWER DOWN S1S1 S1S0 SOURCE 0 0 AGC AMP 0 1 ARRAY AUX IN AMP 1 0 FILTO 1 1 N?C 2 ( S1S0 ) S1S1 INSO 0 1 SOURCE BOTH SOURCE DAC OUT (DAO) CIG2 CIG1 CIG0 AXG1 AXG0 AXPD INS0 OSPD AMT0
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I5216 SERIES Advanced Information PRELIMINARY I5216 ANALOG STRUCTURE (Right Half) DESCRIPTION FLPD CONDITION 0 Power Up 1 Power Down FLD1 FLD0 SAMPLE RATE 0 0 8 KHz 3.7 KHz FLS0 0 1 6.4 KHz 2.9 KHz 1 0 5.3 KHz 2.5 KHz 1 1 4.0 KHz 1.
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I5216 SERIES Advanced Information PRELIMINARY AUTO MUTE AND AUTO GAIN FUNCTIONS During playback, the signal passes through the Automatic Attenuator before it is filtered. The Automatic Attenuator will attenuate all signals at the noise level in order to reduce the noise during quiet pauses. During record, low level input signals are brought up by the Auto Gain function if the configuration bit D7 of CFG0 (AMT0) is set. This improves the signal to noise ratio of recorded low level input signals.
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I5216 SERIES Advanced Information PRELIMINARY VOLUME CONTROL DESCRIPTION VLPD VLS1 VLS0 SOURCE CONDITION 0 Power Up 1 Power Down VOL2 VOL1 VOL0 ATTENUATION 0 0 0 0 dB 0 0 1 4 dB 0 1 0 8 dB 0 0 DAC OUT 0 1 1 12 dB 0 1 SUM2 1 0 0 16 dB 1 0 SUM1 1 0 1 20 dB 1 1 INP 1 1 0 24 dB 1 1 1 28 dB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CIG2 CIG1 CIG0 AXG1 AXG0 AXPD INS0 OSPD AMT0 CDI1 CDI0 OPS1 OPS0 OPA1 OPA0 VLPD 15 14 13 12 1
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I5216 SERIES Advanced Information PRELIMINARY SPEAKER AND AUX OUT DESCRIPTION OPS1 OPS0 0 0 SOURCE OPA1 OPA0 SPKR DRIVE VOL 0 0 Power Down AUX OUT Power Down 0 1 DAC OUT 0 1 3.6 VP-P @ 150 Ω Power Down 1 0 FILTO 1 0 23.
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I5216 SERIES Advanced Information PRELIMINARY MICROPHONE INPUTs The microphone inputs transfer the voice signal to the on-chip AGC preamplifier, or directly to the CODEC INPUT MUX, depending on the selected path. The AGC circuit has a range of 45 dB in order to deliver a nominal 694 mV p-p into the storage array from a typical electret microphone output of 2 to 20 mV p-p. The input impedance is typically 10kΩ. The MICBS pin provides a 2.
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I5216 SERIES Advanced Information PRELIMINARY DIGITAL MODE In the Digital Mode, it is important to understand that each group of digital operations must be preceded by the Digital Mode command (0XC0) and followed by the Exit Digital Mode command (0X40). No delay is required after these commands. Note that after any of these operations is completed, the device is powered down.
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I5216 SERIES Advanced Information PRELIMINARY A sequence might look like: - read the entire page - store it in RAM - change the desired bit(s) - erase the page - write the new data from RAM to the entire page EXAMPLE COMMAND SEQUENCES Graphical representations of these operations follow each description.
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I5216 SERIES Advanced Information PRELIMINARY READ DIGITAL DATA: For a normal digital read, the Registers are loaded as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. S 2 Host executes I C START. Send Slave Address with R/W bit = “0” (Write). Slave responds back with an ACK. Wait for SCL HIGH. Send Digital Mode command – 0X80h, 0XC9h Slave responds with an ACK.
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I5216 SERIES Advanced Information PRELIMINARY ERASE DIGITAL DATA: To erase digital information the following is done: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 2 Host executes I C START. Send Slave Address with R/W bit = “0” (Write). Slave responds back with an ACK. Wait for SCL HIGH. Send Digital Mode command – 0X80h, 0XC0h Slave responds with an ACK. Wait for SCL HIGH. Send Slave Address command – 0X80h Slave responds with an ACK. Wait for SCL HIGH.
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I5216 SERIES Advanced Information PRELIMINARY Notes: 1. Erase operations must be addressed on a Row boundary. The 5 LSB bits of the Low Address Byte will be ignored. 2 2. I C bus is released while erase proceeds. Other devices may use the bus until it is time to execute the STOP command that causes the end of the Erase operation. 3. Host processor must count RAC cycles to determine where the chip is in the erase process, one row per RAC cycle. RAC pulses LOW for 0.
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I5216 SERIES Advanced Information PRELIMINARY The RAC pin remains HIGH for 500 µsec and stays LOW for 15.6 µsec under the Message Cueing mode. See the Timing Parameters table on page 55 for RAC timing information at other sample rates. When a record command is first initiated, the RAC pin remains HIGH for an extra TRACLO period in order to load sample and hold circuits internal to the device. The RAC pin can be used for message management techniques.
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I5216 SERIES Advanced Information PRELIMINARY Master Clock Input Table for ChipCorder Section FMCLK FLD1 FLD0 CKD2 CKDV Sample Rate Filter Knee 13.824 MHz 0 0 0 0 8.0 kHz 3.7 kHz 20.48 MHz 0 0 0 1 8.0 kHz 3.7 kHz 27.648 MHz 0 0 1 0 8.0 kHz 3.7 kHz 40.96 MHz 0 0 1 1 8.0 kHz 3.7 kHz 13.824 MHz 0 1 0 0 6.4 kHz 2.9 kHz 20.48 MHz 0 1 0 1 6.4 kHz 2.9 kHz 27.648 MHz 0 1 1 0 6.4 kHz 2.9 kHz 40.96 MHz 0 1 1 1 6.4 kHz 2.9 kHz 13.824 MHz 1 0 0 0 5.
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I5216 SERIES Advanced Information PRELIMINARY ANALOG I/O PINS MIC+, MIC- (Microphone Input +/-) The microphone input transfers the voice signal to the on-chip AGC preamplifier or directly to the CODEC A/D INPUT MUX, depending on the selected path. The AGC circuit has a range of 45 dB in order to deliver a nominal 694 mV p-p into the storage array from a typical electric microphone output of 2 to 20 mV p-p. The input impedance is typically 20 kΩ differential and 13.
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I5216 SERIES Advanced Information PRELIMINARY SP +, SP- (Speaker +/-) This is the speaker differential output circuit. It is designed to drive an 8Ω speaker connected across the speaker pins, up to a maximum of 23.5 mW RMS power. This stage has two selectable gains, 1.32 and 1.6, which can be chosen through the configuration registers. These pins are biased to approximately 1.2 VDC and, if used single-ended, must be capacitively coupled to their load. Do NOT ground the unused pin.
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I5216 SERIES Advanced Information PRELIMINARY AUX IN (Auxiliary Input) The AUX IN is an additional audio input to the Winbond I5216, such as from the microphone circuit in a mobile phone “car kit.” This input has a nominal 694 mV p-p level at its minimum gain setting (0 dB). (See Aux In Amplifier Gain Settings Table below). Additional gain is available in 3 dB steps (controlled 2 by the I C interface) up to 9 dB.
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I5216 SERIES Advanced Information PRELIMINARY POWER AND GROUND PINS VCCA, VCCD (Voltage Inputs) To minimize noise, the analog and digital circuits in the Winbond I5216 device use separate power busses. These +3 V busses lead to separate pins. Tie the VCCD pins together as close as possible, and decouple both supplies as near to the package as possible. VSSA, VSSD (Ground Inputs) The Winbond I5216 series utilizes separate analog and digital ground busses.
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I5216 SERIES Advanced Information PRELIMINARY SAMPLE PC LAYOUT FOR PDIP The PDIP package is illustrated from the top. PC board traces and the three chip capacitors are on the bottom side of the board. Note 2 1 C1 V C C D C2 MCLK V S S D Note 3 Note 1 VSSA (Digital Ground) C1=C2=C3=0.1 uF chip Capacitors Note 1: VSSD traces should be kept separated back to the VSS supply feed point. Note 2: VCCD traces should be kept separated back to the VCC supply feed point.
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I5216 SERIES Advanced Information PRELIMINARY ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (Packaged Parts) (1) Condition Value 0 Junction temperature 150 C Storage temperature range -65 C to +150 C Voltage Applied to any pin (VSS - 0.3V) to (VCC + 0.3V) Voltage applied to any pin (Input current limited to +/-20 mA) (VSS – 1.0V) to (VCC + 1.0V) Lead temperature (soldering 300 C 0 0 0 – 10 seconds) VCC - VSS -0.3V to +5.5V 1.
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I5216 SERIES Advanced Information PRELIMINARY OPERATING CONDITIONS (Die) Condition Value (1) 0 Die operating temperature range Supply voltage (VCC) Ground voltage (VSS) 1. 0 C to +50 C (2) +2.7V to +3.3V (3) Case temperature 0 0V 2. VCC = VCCA = VCCD 3. VSS = VSSA = VSSD General Parameters Min (2) Typ (1) Max (2) Symbol Parameters VIL Input Low Voltage VIH Input High Voltage VOL SCL, SDA, SDIO Output Low Voltage 0.4 V IOL = 3 mA VOL1 RAC, INT Output Low Voltage 0.
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I5216 SERIES Advanced Information PRELIMINARY TIMING PARAMETERS Symbol Parameters FS Sampling Frequency FCF TREC TPLAY TPUD TSTOP OR PAUSE Min (2) Typ (1) Max (2) Units Conditions 8.0 kHz (5) 6.4 kHz (5) 5.3 kHz (5) 4.0 kHz (5) 8.0 kHz (sample rate) 3.7 kHz Knee Point (3)(7) 6.4 kHz (sample rate) 2.9 kHz Knee Point (3)(7) 5.3 kHz (sample rate) 2.5 kHz Knee Point (3)(7) 4.0 kHz (sample rate) 1.8 kHz Knee Point (3)(7) 8.0 kHz (sample rate) 8.05 min (6) 6.
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I5216 SERIES Advanced Information PRELIMINARY TIMING PARAMETERS (CONT’D) Symbol Parameters TRAC RAC Clock Period TRACLO TRACM TRACML Min Typ (1) Max (2) Units Conditions 8.0 kHz (sample rate) 256 msec (9) 6.4 kHz (sample rate) 320 msec (9) 5.3 kHz (sample rate) 386 msec (9) 4.0 kHz (sample rate) 512 msec (9) 8.0 kHz (sample rate) 8 msec 6.4 kHz (sample rate) 10 msec 5.3 kHz (sample rate) 12.1 msec 4.0 kHz (sample rate) 16 msec 8.0 kHz (sample rate) 500 msec 6.
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I5216 SERIES Advanced Information PRELIMINARY ANALOG PARAMETERS MICROPHONE INPUT (14) Symbol Parameters VMIC+/- MIC +/- Input Voltage VMIC (0TLP) MIC +/- input reference transmission level point (0TLP) AMIC (GT) MIC +/- Gain Tracking RMIC Microphone input resistance AAGC Microphone AGC Amplifier Range VMICBS Microphone Bias Voltage RMICBS MICBS Output Resistance Min (2) Typ ( 1)(14) Max (2) Units Conditions mV Peak-to-Peak (4)(8) 208 mV Peak-to-Peak (4)(10) +/-0.
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I5216 SERIES Advanced Information PRELIMINARY SPEAKER OUTPUTS (14) (2) Symbol Parameters Min VSPHG SP+/- Output Voltage (High Gain Setting) RSPLG SP+/- Output Load Imp. (Low Gain) 8 RSPHG SP+/- Output Load Imp. (High Gain) 70 CSP SP+/- Output Load Cap. VSPAG SP+/- Output Bias Voltage (Analog Ground) VSPDCO Speaker Output DC Offset PSRR Power Supply Rejection Ratio FR Frequency Response (3003400 Hz) -0.25 POUTLG Power Output (Low Gain Setting) 23.5 Typ (1)(14) Max (2) 3.
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I5216 SERIES Advanced Information PRELIMINARY VOLUME CONTROL (14) Symbol Parameters AOUT Output Gain Absolute Gain 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. Min (2) Typ (1)(14) Max (2) -28 to 0 -0.5 +0.5 Units Conditions dB 8 steps of 4 dB, referenced to output dB AUX IN 1.0 kHz 0TLP, 6 dB gain setting measured differentially at SP+/- Typical values: TA = 25°C and Vcc = 3.0V. All min/max limits are guaranteed by Winbond via electrical testing or characterization.
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I5216 SERIES Advanced Information PRELIMINARY I2C INTERFACE TIMING STANDARD-MODE PARAMETER FAST-MODE SYMBOL MIN. MAX. MIN. MAX. UNIT fSCL 0 100 0 400 kHz tHD; STA 4.0 - 0.6 - ns LOW period of the SCL clock tLOW 4.7 - 1.3 - ns HIGH period of the SCL clock tHIGH 4.0 - 0.6 - ns tSU; STA 4.7 - 0.6 - ns tSU; DAT 250 - 100 SCL clock frequency Hold time (repeated) START condition.
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I5216 SERIES Advanced Information PRELIMINARY CODEC PARAMETERS The internal CODEC meets the specification of the ITU-T G.714 recommendation in 8 kHz sampling mode. This specification is verified, using the MIC+/- and SPEAKER+/- pins as analog input and output. The CODEC µ/A-Law Compander meets the specification of the ITU-T G.711 µ/A-Law companding recommendation Symbol Parameters LABS Absolute level TXMAX Max. Transmit level fch1 Min Units Conditions Vrms 0 dBm0 = -2.
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I5216 SERIES Advanced Information PRELIMINARY TIMING DIAGRAMS I2C TIMING DIAGRAM STOP START t t t f r SU;DAT SDA SCL t t f HIGH t t LOW SU;STO t SCLK PLAYBACK AND STOP CYCLE tSTOP tSTART SDA PLAY AT ADDR STOP SCL DATA CLOCK PULSES STOP AUX IN AUX OUT - 62 Publication Release Date: November 30, 2001 Revision A1
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I5216 SERIES Advanced Information PRELIMINARY EXAMPLE OF POWER UP COMMAND - 63 Publication Release Date: November 30, 2001 Revision A1
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I5216 SERIES Advanced Information PRELIMINARY I2S TIMING DIAGRAMS - 64 Publication Release Date: November 30, 2001 Revision A1
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I5216 SERIES Advanced Information PRELIMINARY I2S PARAMETERS (all values in nano seconds) Parameter Bit Clock period T Transmitter Receiver Lower Limit Upper Limit Lower Limit Upper Limit MIN MIN MIN MIN MAX MAX 325 MAX 114 114 Low time tLC 114 114 Rise time tRC MAX 325 High time tHC 49 Delay tdtr Hold time thtr NOTES 260 100 Set-up time tsr 65 Hold time thr 0 PCM TIMING DIAGRAMS - 65 Publication Release Date: November 30, 2001 Revision A1
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I5216 SERIES Advanced Information PRELIMINARY PCM TIMING DIAGRAMS (CONT’D) - 66 Publication Release Date: November 30, 2001 Revision A1
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I5216 SERIES Advanced Information PRELIMINARY PCM TIMING DIAGRAMS (CON’TD) - 67 Publication Release Date: November 30, 2001 Revision A1
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I5216 SERIES Advanced Information PRELIMINARY PCM PARAMETERS PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT Bit Clock Frequency 1/TSCK SCK 64 --- 3072 kHz Bit Clock Duty Cycle DC SCK --- 50 --- % Word Sync. Frequency 1/TWSl WS @ low rate --- 8000 --- Hertz Word Sync. Frequency 1/TWSh WS @ high rate 44.
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I5216 SERIES Advanced Information PRELIMINARY I2C SERIAL INTERFACE TECHNICAL INFORMATION CHARACTERISTICS OF THE I2C SERIAL INTERFACE 2 The I C interface is for bi-directional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the interface bus is not busy.
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I5216 SERIES Advanced Information PRELIMINARY SYSTEM CONFIGURATION A device generating a message is a ‘transmitter’; a device receiving a message is the ‘receiver’. The device that controls the message is the ‘master’ and the devices that are controlled by the master are the ‘slaves’. ACKNOWLEDGE The number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit.
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I5216 SERIES Advanced Information PRELIMINARY I2C PROTOCOL 2 Since the I C protocol allows multiple devices on the bus, each device must have an address. This address is known as a “Slave Address”. A Slave Address consists of 7 bits, followed by a single bit that indicates the direction of data flow. This single bit is 1 for a Write cycle, which indicates the data is being sent from the current bus master to the device being addressed.
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I5216 SERIES Advanced Information PRELIMINARY Another common operation in the ISD5216 is the reading of digital data from the chip’s memory array 2 at a specific address. This requires the I C interface Master to first send an address to the ISD5116 2 Slave device, and then receive data from the Slave in a single I C operation. To accomplish this, the data direction R/W bit must be changed in the middle of the command.
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I5216 SERIES Advanced Information PRELIMINARY I2S SERIAL INTERFACE TECHNICAL INFORMATION 2 THE I BUS As shown in the following figure, the bus has three lines: • continuous serial clock (SCK) • word select (WS) • serial data (SD)and the device generating SCK and WS is the master. Simple System Configurations and Basic Interface Timing SERIAL DATA Serial data is transmitted in two’s complement with the MSB first.
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I5216 SERIES Advanced Information PRELIMINARY Serial data sent by the transmitter may be synchronized with either the trailing (HIGH-to-LOW) or the leading (LOW-to-HIGH) edge of the clock signal. However, the serial data must be latched into the receiver on the leading edge of the serial clock signal, and so there are some restrictions when transmitting data that is synchronized with the leading edge (see figure below ). Note that the specifications are defined by the transmitter speed.
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I5216 SERIES Advanced Information PRELIMINARY WORD SELECT The word select line indicates the channel being transmitted: • WS = 0; channel 1 (left) • WS = 1; channel 2 (right) WS may change either on a trailing or leading edge of the serial clock, but it doesn’t need to be symmetrical. In the slave, this signal is latched on the leading edge of the clock signal. The WS line changes one clock period before the MSB is transmitted.
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I5216 SERIES Advanced Information PRELIMINARY S Parameters (all values in nanoseconds) Parameter Bit Clock period T Transmitter Receiver Lower Limit Upper Limit Lower Limit Upper Limit MIN MIN MIN MIN MAX MAX 325 MAX 114 114 Low time tLC 114 114 Rise time tRC MAX 325 High time tHC 49 Delay tdtr Hold time thtr NOTES 260 100 Set-up time tsr 65 Hold time thr 0 Voltage Level Specification Output Levels V L < 0.4V V H > 2.
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I5216 SERIES Advanced Information PRELIMINARY DEVICE PHYSICAL DIMENSIONS PLASTIC THIN SMALL OUTLINE PACKAGE (TSOP) TYPE E DIMENSIONS A B G 28 27 26 25 24 23 22 21 20 19 18 17 16 15 2 3 4 5 6 7 8 9 10 11 12 13 14 F C E D J H I PLASTIC THIN SMALL OUTLINE PACKAGE (TSOP) TYPE E DIMENSIONS INCHES M ILLIM ETERS M in Nom M ax M in Nom M ax A 0.520 0.528 0.535 13.20 13.40 13.60 B 0.461 0.465 0.469 11.70 11.80 11.90 C 0.311 0.315 0.319 7.90 8.00 8.10 D 0.002 0.006 0.05 E 0.
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I5216 SERIES Advanced Information PRELIMINARY PLASTIC SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) DIMENSIONS 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A G C B D F E H PLASTIC SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) DIMENSIONS INCHES MILLIMETERS Min Nom Max Min Nom Max A 0.701 0.706 0.711 17.81 17.93 18.06 B 0.097 0.101 0.104 2.46 2.56 2.64 C 0.292 0.296 0.299 7.42 7.52 7.59 D 0.005 0.009 0.0115 0.127 0.22 0.29 E 0.014 0.016 0.
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I5216 SERIES Advanced Information PRELIMINARY - 79 Publication Release Date: November 30, 2001 Revision A1
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I5216 SERIES Advanced Information PRELIMINARY DIE BONDING PHYSICAL LAYOUT I5216 DEVICE PIN/PAD LOCATIONS WITH RESPECT TO DIE CENTER IN MICRON (µM) PIN Pin Name X Axis Y Axis VSSD VSS Digital Ground -1880.70 4721.30 VSSD VSS Digital Ground -1709.10 4721.30 AD0 Address 0 -1407.20 4721.30 SDA Serial Data Address -1066.00 4721.30 AD1 Address 1 -743.70 4721.30 SCL Serial Clock Line -428.60 4721.30 VCCD VCC Digital Supply Voltage -156.50 4721.
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I5216 SERIES Advanced Information PRELIMINARY I5216 SERIES BONDING PHYSICAL LAYOUT VSSD VSSD A0 SDA A1 SCL V CCD V CCD (1) MCLK (UNPACKAGED DIE) INT RAC SDIO SDI VSSA I5216 Series Die Dimensions I5216 Series X: 4380 µm Die Dimensions X: µm 4380µm Y: 9880 Y: (3) 9880µm 988 I5216 (3) Die Thickness Die Thickness 292.1µm + 12.7µm 292.1 + 12.7 µm Pad µm Opening 90 x 90µm Pad Opening (min) 3.5 x 3.5 mils 90x 90 µm 3.5 x 3.
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I5216 SERIES Advanced Information PRELIMINARY ORDERING INFORMATION WINBOND PART NUMBER DESCRIPTION I5216-_ _ Product Family I5216 Product (8- to 16-minute durations) Special Temperature Field: Blank = Commercial Packaged (0°C to +70°C) or Commercial Die (0°C to +50°C) D = Extended (–20°C to +70°C) I = Industrial (–40°C to +85°C) Package Type: E = 28-Lead 8x13.4mm Plastic Thin Small Outline Package (TSOP) Type 1 S = 28-Lead 0.
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I5216 SERIES Advanced Information PRELIMINARY When ordering I5216 series devices, please refer to the following valid part numbers. Part Number I5216E I5216ED I5216EI I5216S I5216SD I5216SI I5216P I5216X Chip scale package is available upon customer’s request. For the latest product information, access Winbond’s worldwide website at http://www.winbondusa.com Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. No. 4, Creation Rd.