User Manual

I5216 SERIES
Advanced Information
PRELIMINARY
Publication Release Date: November 30, 2001
-6 Revision A1
BLOCK DIAGRAMS
5/22/01
I5216 Block Diagram
AUX IN
AMP
1.0 / 1.4 / 2.0 / 2.8
AGC
SUM1 MUX
Vol MUX
Filter
MUX
Low Pass
Filter
SUM1
DAO
VOL
SP+
SP-
SPEAKER
AUX OUT
MIC+
MIC -
AGCCAP
MICROPHONE
AUX IN
MCLK
V
SSA
V
CCA
V
SSA
V
SSD
V
SSD
V
CCD
V
CCD
2 x 64 S/H
Program/Read Control
Input Source MUX
Array I/O Mux
SUM1
INP
DAO
SUM2
FILTO
SUM2
SUM1
Summing
AMP
SUM2
Summing
AMP
Output MUX
Volume
Control
MIC IN
AUX IN
FILTO
SUM1
AUX IN
FILTO
SUM2
(ANALOG)
ARRAY
INP
SUM1 MUX
CTRL
(DIGITAL)
2 x 64-bit reg.
ARRAY OUT
(ANALOG)
ARRAY OUT
(DIGITAL)
ARRAY
Spkr.
AMP
AUX
OUT
AMP
Power Conditioning
RACINTSDA
SCL
A1A0
Device Control
Internal
Clock
Multilevel
Storage Array
Σ
ΣΣ
Σ
Σ
ΣΣ
Σ
2
( )
VLS0
VLS1
2
( )
AXG0
AXG1
2
( )
S1S0
S1S1
2
( )
S1M0
S1M1
2
( )
S2M0
S2M1
( )
OPA0
OPA1
2
( )
OPS0
OPS1
2
( )
FLD0
FLD1
2
(INS0)
1
1
(AXPD)
1
(AGPD)
1
(FLPD)
1
(FLS0)
3
( )
VOL0
VOL1
VOL2
PCM / I2S Interface
WS SCK SDIO SDI
µ
µµ
µ-Law / A-Law /
Linear 14 bit
CODEC
C
O
D
E
C
M
u
x
SUM2
INP
CDI0
( )
2.2V Voltage
reference
MICBS
DAO
A/D
2
Auto mute
Auto gain
1
(AMT0)
( )
2
ADPD
DAPD
CDI1
MIC+
MIC-
2
OSPD
CKDV
1
(AGPD)
÷2
1
(CKD2)
( )
1
(VLPD)