User Manual

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_______________General Description

The MAX1003 is a dual, 6-bit analog-to-digital converter

(ADC) that combines high-speed, low-power operation

with a user-selectable input range, an internal refer-

ence, and a clock oscillator. The dual parallel ADCs are

designed to convert in-phase (I) and quadrature (Q)

analog signals into two 6-bit, offset-binary-coded digital

outputs at sampling rates up to 90Msps. The ability to

directly interface with baseband I and Q signals makes

the MAX1003 ideal for use in direct-broadcast satellite,

VSAT, and QAM16 demodulation applications.

The MAX1003 input amplifiers feature true differential

inputs, a -0.5dB analog bandwidth of 55MHz, and user-

programmable input full-scale ranges of 125mVp-p,

250mVp-p, or 500mVp-p. With an AC-coupled input

signal, matching performance between input channels

is typically better than 0.1dB gain, 1/4LSB offset, and

0.5° phase. Dynamic performance is 5.85 effective

number of bits (ENOB) with a 20MHz analog input sig-

nal, or 5.7 ENOB with a 50MHz signal.

The MAX1003 operates with +5V analog and +3.3V digi-

tal supplies for easy interfacing to +3.3V-logic-compati-

ble digital signal processors and microprocessors. It

comes in a 36-pin SSOP package.

________________________Applications

Direct Broadcast Satellite (DBS) Receivers

VSAT Receivers

Wide Local Area Networks (WLANs)

Cable Television Set-Top Boxes

____________________________Features

♦ Two Matched 6-Bit ADCs

♦ High Sampling Rate: 90Msps per ADC

♦ Low Power Dissipation: 350mW

♦ Excellent Dynamic Performance:

5.85 ENOB with 20MHz Analog Input

5.7 ENOB with 50MHz Analog Input

♦ ±1/4LSB INL and DNL (typ)

♦ Internal Bandgap Voltage Reference

♦ Internal Oscillator with Overdrive Capability

♦ 55MHz (-0.5dB) Bandwidth Input Amplifiers with

True Differential Inputs

♦ User-Selectable Input Full-Scale Range

(125mVp-p, 250mVp-p, or 500mVp-p)

♦ 1/4LSB Channel-to-Channel Offset Matching (typ)

♦ 0.1dB Gain and 0.5° Phase Matching (typ)

♦ Single-Ended or Differential Input Drive

♦ Flexible, 3.3V, CMOS-Compatible Digital Outputs

MAX1003

Low-Power, 90Msps, Dual 6-Bit ADC

________________________________________________________________

Maxim Integrated Products

MAX1003

DATA

BUFFER

CLOCK

DRIVER

DI0–DI5

DCLK

TNK+

TNK-

DQ0–DQ5

INPUT

AMP

IIN+

IIN-

GAIN

QIN+

QIN-

CLOCK

OUT

DATA

BUFFER

ADC

VREF

BANDGAP

REFERENCE

OFFSET

CORREC-

TION Q

OFFSET

CORREC-

TION I

INPUT

AMP

QOCC+ QOCC-

IOCC+ IOCC-

_________________________________________________________Functional Diagram

19-1236; Rev 0; 6/97

PART

MAX1003CAX 0°C to +70°C

TEMP. RANGE PIN-PACKAGE

36 SSOP

EVALUATION KIT

AVAILABLE

______________Ordering Information

Pin Configuration appears at end of data sheet.

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800

Summary of content (12 pages)

PAGE 1
9-1236; Rev 0; 6/97 KIT ATION EVALU E L B AVAILA Low-Power, 90Msps, Dual 6-Bit ADC ____________________________Features ♦ Two Matched 6-Bit ADCs ♦ High Sampling Rate: 90Msps per ADC ♦ Low Power Dissipation: 350mW ♦ Excellent Dynamic Performance: 5.85 ENOB with 20MHz Analog Input 5.7 ENOB with 50MHz Analog Input ♦ ±1/4LSB INL and DNL (typ) ♦ Internal Bandgap Voltage Reference ♦ Internal Oscillator with Overdrive Capability ♦ 55MHz (-0.
PAGE 2
MAX1003 Low-Power, 90Msps, Dual 6-Bit ADC ABSOLUTE MAXIMUM RATINGS VCC to GND ............................................................-0.3V to 6.5V VCCO to OGND ........................................................-0.3V to 6.5V GND to OGND ........................................................-0.3V to 0.3V Digital and Clock Output Pins to OGND...-0.3V to VCCO (10sec) All Other Pins to GND...............................................-0.
PAGE 3
Low-Power, 90Msps, Dual 6-Bit ADC (VCC = +5V ±5%, VCCO = 3.3V ±300mV, TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC PERFORMANCE (Gain = open, external 90MHz clock (Figure 7), VINI = VINQ = 20MHz sine, amplitude -1dB below full scale, unless otherwise noted.) Maximum Sample Rate fMAX Analog Input -0.5dB Bandwidth BW 90 GAIN = GND, open, VCC GAIN = open (mid gain) 5.7 ENOBH ENOBL GAIN = VCC (high gain) GAIN = GND (low gain) 5.8 5.
PAGE 4
__________________________________________Typical Operating Characteristics (VCC = +5V ±5%, VCCO = 3.3V ±300mV, fCLK = 90Msps, GAIN = open (midgain) MAX1003 evaluation kit, TA = +25°C, unless otherwise noted.) EFFECTIVE NUMBER OF BITS vs. ANALOG INPUT FREQUENCY EFFECTIVE NUMBER OF BITS vs. SAMPLING/CLOCK FREQUENCY ANALOG INPUT BANDWIDTH EFFECTIVE NUMBER OF BITS MAGNITUDE (dB) -0.2 5.4 5.2 -0.4 -0.6 MAX1003-03 0 5.8 5.6 6.0 MAX1003-02 MAX1003-01 6.0 5.9 5.8 5.7 -0.8 5.6 -1.0 5.
PAGE 5
Low-Power, 90Msps, Dual 6-Bit ADC PIN NAME 1 GAIN FUNCTION 2 IOCC+ Positive I-Channel Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled inputs. Ground for DC-coupled inputs. 3 IOCC- Negative I-Channel Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled inputs. Ground for DC-coupled inputs. 4 IIN+ I-Channel Noninverting Analog Input 5 IIN- I-Channel Inverting Analog Input 6 VCC +5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 7).
PAGE 6
MAX1003 Low-Power, 90Msps, Dual 6-Bit ADC Single-ended and differential AC-coupled input circuits are shown in Figures 2 and 3. Each of the amplifier inputs is internally biased to a 2.35V reference through a 20kΩ resistor, eliminating external DC bias circuits. A series 0.1µF capacitor is required at each amplifier input for AC-coupled signals. When operating with AC-coupled inputs, the input amplifiers’ DC offset voltage is nulled to within ±1/2LSB by an on-chip offset-correction amplifier.
PAGE 7
Low-Power, 90Msps, Dual 6-Bit ADC _OCC+ _OCC+ _OCC- 0.1µF _IN+ INPUT AMP VSOURCE _IN+ INPUT AMP VSOURCE _IN- _IN- 0.1µF 0.1µF 20k MAX1003 20k 20k 2.35V INTERNAL REFERENCE Figure 3. Differential AC-Coupled Input Figure 2. Single-Ended AC-Coupled Input OFFSET CORRECTION DISABLED _OCC+ MAX1003 20k 2.35V INTERNAL REFERENCE OFFSET CORRECTION DISABLED _OCC- _OCC+ OFFSET CORRECTION _IN+ INPUT AMP VSOURCE INPUT AMP VSOURCE _IN- VREF 1.75V TO 2.
PAGE 8
MAX1003 Low-Power, 90Msps, Dual 6-Bit ADC The MAX1003 features a proprietary encoding scheme that ensures no more than 1LSB dynamic encoding error. Dynamic encoding errors resulting from metastable states may occur when the analog input voltage, at the time the sample is taken, falls close to the decision point for any one of the input comparators. The resulting output code for typical converters can be incorrect, including false full- or zero-scale outputs.
PAGE 9
Low-Power, 90Msps, Dual 6-Bit ADC MAX1003 N N+1 ANALOG INPUT N+2 tAD 50% TNK+ (INPUT CLOCK) tDCLK 1.4V tPD DCLK tSKEW DATA OUT DATA VALID N - 1 1.4V DATA VALID N Figure 8. MAX1003 Timing Diagram Output Data Format The conversion results are output on a dual, 6-bit-wide data bus. Data is latched into the ADC output latch following a pipeline delay of one clock cycle, as shown in Figure 8.
PAGE 10
MAX1003 Low-Power, 90Msps, Dual 6-Bit ADC __________Applications Information _____________Dynamic Performance The MAX1003 is designed with separate analog and digital power-supply and ground connections to isolate high-current digital noise spikes from the more sensitive analog circuitry. The high-current digital output ground (OGND) and analog ground (GND) should be at the same DC level, connected at only one location on the board. This will provide best noise immunity and improved conversion accuracy.
PAGE 11
Low-Power, 90Msps, Dual 6-Bit ADC MAX1003 __________________Pin Configuration TOP VIEW GAIN 1 36 VCC IOCC+ 2 35 DI5 IOCC- 3 34 DI4 IIN+ 4 33 DI3 IIN- 5 32 DI2 MAX1003 31 DI1 VCC 6 GND 7 30 DI0 VCC 8 29 DCLK TNK+ 9 28 VCCO TNK- 10 27 OGND GND 11 26 VCCO GND 12 25 DQ0 VCC 13 24 DQ1 QIN- 14 23 DQ2 QIN+ 15 22 DQ3 QOCC- 16 21 DQ4 QOCC+ 17 20 DQ5 GND 18 19 GND SSOP ___________________Chip Information TRANSISTOR COUNT: 6097 _____________________________________________
PAGE 12
________________________________________________________Package Information SSOP2.EPS MAX1003 Low-Power, 90Msps, Dual 6-Bit ADC Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.