9-4250; Rev 0; 8/08 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Ordering Information PART TEMP RANGE PIN-PACKAGE MAX11043ATL+ -40°C to +125°C 40 TQFN-EP* +Denotes a lead-free/RoHS-compliant package. *EP = Exposed pad. Applications DVDD SHDN DGND AGND AOUT AVDD REFDACL REFDACH TOP VIEW REFDAC Pin Configuration REFD The MAX11043 features 4 single-ended or differential channels of simultaneous-sampling ADCs with 16-bit resolution.
MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC ABSOLUTE MAXIMUM RATINGS AVDD to AGND ....................................................-0.3V to +4.0V DVDD to DGND .....................................................-0.3V to +4.0V DVREG to DGND...................................................-0.3V to +3.0V AGND to DGND.....................................................-0.3V to +0.
4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC ((VAVDD = +3.0V to +3.6V, VDVDD = +3.0V, CDVREG = 10µF, VAGND = VDGND = 0, common-mode input voltage = AVDD/2, VREFBP = VREFA = VREFB = VREFC = VREFD = +2.5V (external reference), VREFDAC = VREFDACH = +1.25V (external reference), VREFDACL = 0, CREFBP = CREFA = CREFB = CREFC = CREFD = CREFDAC = 1µF, fSCLK = 38.4MHz, fEXCLK = 38.
MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC ELECTRICAL CHARACTERISTICS (continued) ((VAVDD = +3.0V to +3.6V, VDVDD = +3.0V, CDVREG = 10µF, VAGND = VDGND = 0, common-mode input voltage = AVDD/2, VREFBP = VREFA = VREFB = VREFC = VREFD = +2.5V (external reference), VREFDAC = VREFDACH = +1.25V (external reference), VREFDACL = 0, CREFBP = CREFA = CREFB = CREFC = CREFD = CREFDAC = 1µF, fSCLK = 38.4MHz, fEXCLK = 38.
4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC ((VAVDD = +3.0V to +3.6V, VDVDD = +3.0V, CDVREG = 10µF, VAGND = VDGND = 0, common-mode input voltage = AVDD/2, VREFBP = VREFA = VREFB = VREFC = VREFD = +2.5V (external reference), VREFDAC = VREFDACH = +1.25V (external reference), VREFDACL = 0, CREFBP = CREFA = CREFB = CREFC = CREFD = CREFDAC = 1µF, fSCLK = 38.4MHz, fEXCLK = 38.
MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC ELECTRICAL CHARACTERISTICS (continued) ((VAVDD = +3.0V to +3.6V, VDVDD = +3.0V, CDVREG = 10µF, VAGND = VDGND = 0, common-mode input voltage = AVDD/2, VREFBP = VREFA = VREFB = VREFC = VREFD = +2.5V (external reference), VREFDAC = VREFDACH = +1.25V (external reference), VREFDACL = 0, CREFBP = CREFA = CREFB = CREFC = CREFD = CREFDAC = 1µF, fSCLK = 38.4MHz, fEXCLK = 38.
4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC ((VAVDD = +3.0V to +3.6V, VDVDD = +3.0V, CDVREG = 10µF, VAGND = VDGND = 0, common-mode input voltage = AVDD/2, VREFBP = VREFA = VREFB = VREFC = VREFD = +2.5V (external reference), VREFDAC = VREFDACH = +1.25V (external reference), VREFDACL = 0, CREFBP = CREFA = CREFB = CREFC = CREFD = CREFDAC = 1µF, fSCLK = 38.4MHz, fEXCLK = 38.
Typical Operating Characteristics (continued) (VAVDD = +3.3V, VDVDD = +3.0V, fSCLK = fEXCLK = 19.2MHz, VREFBP, VREF_ = +2.5V, common-mode input voltage = AVDD/2, TA = +25°C, unless otherwise noted.
4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC 1.0 0dBm MAX11043 toc14 MAX11043 toc13 MAX11043 toc12 CODES 3 TO 255 0.8 0.6 20mV/div DNL (LSB) 0.4 20dBm/div DACH 0.2 MAX11043 Typical Operating Characteristics (continued) (VAVDD = +3.3V, VDVDD = +3.0V, fSCLK = fEXCLK = 19.2MHz, VREFBP, VREF_ = +2.5V, common-mode input voltage = AVDD/2, TA = +25°C, unless otherwise noted.) COARSE DAC DNL FINE DAC SETTLING vs.
4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC MAX11043 Pin Description PIN NAME 1 AINBN Channel B Analog Negative Input 2 REFA Channel A Reference Bypass. Bypass REFA with a nominal 1µF capacitor to AGND. 3 AINAN Channel A Analog Negative Input 4 AINAP Channel A Analog Positive Input 5, 26 AVDD Analog Supply. Bypass each AVDD with a nominal 1µF capacitor to AGND. 6, 24, 33 AGND Analog Ground. Connect AGND inputs together.
4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC AVDD DVDD AINAP UP/DWN PGA EQ PROGRAMMABLE DIGITAL FILTER SIGMA-DELTA ADC AINAN DACSTEP CONVRUN EOC SERIAL INTERFACE SHDN REFA SCLK DOUT AINBP DIN PGA EQ PROGRAMMABLE DIGITAL FILTER SIGMA-DELTA ADC AINBN FLASH REFB MAX11043 AINCP PGA EQ PROGRAMMABLE DIGITAL FILTER SIGMA-DELTA ADC AINCN POR REFC DIGITAL SUPPLY AINDP INTERNAL REGULATOR +2.
MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Detailed Description The MAX11043 features 4 single-ended or differential channels of simultaneous-sampling ADCs with 16-bit resolution. The MAX11043 contains a versatile filter block and PGA per channel. The filter consists of seven cascaded 2nd-order filter sections for each channel allowing the construction of a 14th-order filter. The filter coefficients are user-programmable.
4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Equalizer (EQ) The EQ matches the frequency/gain characteristics of CW-chirp radar systems where the distance to the target is proportional to the measured frequency. Distant targets not only have a higher frequency, they have a weaker signal. Hence, higher frequencies need more amplification than lower frequencies.
Filter coefficients A1 and B1 are always 1. B3 is limited to -1, 0, and 1. Fine Gain A/B/C/D Registers at the input of each filter set. Fine gain adjustment has a resolution of 16 bits and a gain range of -4 to +4. Set the RECT bit to rectify the filter output. Figures 5–8 show the response to a step input of the default filters used for ADC trimming. Filter coefficients A2, A3, and B2 are stored as 16-bit two’s complement values in the range of -4 to +4.
4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC the step size. The UP/DWN input sets the direction of the step. Drive UP/DWN high to step up, drive low to step down. The coarse 8-bit, dual tap DAC generates the high and low reference values for the fine DAC. Obtain the coarse DAC reference from the main reference or by driving the REFDAC input externally. The main reference, REFBP, is divided by two before the coarse DAC.
MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Reference (REFBP) The MAX11043 features an internal 2.5V bandgap reference. Bypass REFBP with a 1µF capacitor or power down the buffer amplifier and drive REFBP with an external reference. In internal reference mode, REFBP provides the main reference voltage for the MAX11043. Refer to www.maxim-ic.com/references for a list of available precision references.
4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC tCSH tCH tDH CS MAX11043 tCP tDS tCSS tCL SCLK DIN START X ADR 4 ADR 3 ADR 2 ADR 1 ADR 0 R/W = 0 0 D7 D6 D5 D4 D3 D2 D1 D0 HIGH IMPEDANCE HIGH IMPEDANCE DOUT Figure 9.
MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Register Map Table 1.
4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC ADCA, ADCB, ADCC, and ADCD Result Registers (00h–03h) The ADC channel A, B, C, and D result registers provide the result data from the 4 ADC channels. EOC asserts low when new data is available. Initiate a data read prior to the next rising edge of EOC or the result is overwritten.
MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC SCHAN_<4:1>: Automatic ADC result output for each channel (A, B, C, and D). 1 = ADC channel data is output on DOUT each time a new result is valid in the sequence, A, B, C, and D. 0 = ADC data is not presented automatically for this channel (default).
4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC MAX11043 CONFIG_ Register (0Ch–0Fh) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 X X X BDAC3 BDAC2 BDAC1 BDAC0 DIFF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 EQ MODG1 MODG0 PDPGA FILT PGAG ENBIASP ENBIASN This register sets the gain of each ADC channel and selects one of the default filters or EQ function. EQ<7>: EQ function. 1 = analog EQ enabled.
MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Reference Register (10h) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 0 0 0 PURGE4 PURGE3 PURGE2 PURGE1 PURGE0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 EXTREF EXBUFA EXBUFB EXBUFC EXBUFD EXBUFDAC EXBUFDACH EXBUFDACL Reserved<15:13>: Reserved. Set to 0. PURGE4:PURGE0<12:8>: Filter purge interval. Straight binary.
4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC MAX11043 Fine Gain A/B/C/D Registers (11h–14h) Fine gain for each channel is a two’s complement binary value (8192 x desired gain). FINE GAIN REGISTER GAIN 7FFFh (4 – 1/8192) 4000h 2 2001h 8193/8192 2000h 1 (default) 1FFFh 8191/8192 1000h 0.5 0800h 0.
MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Flash Mode Register (18h) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FM2 (Flashmode2) FM1 (Flashmode1) FM0 (Flashmode0) 0 X X X Flash busy (read only) Write allowed only if flash busy bit is zero. FM2:FM0<7:5>: Flash operation (default 0). 000 = no operation. 110 = transfer data from flash to C-RAM. 111 = no operation. Reserved<4>: Reserved. Set to 0.
4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC This is a 16-bit register that contains the data for a flash write operation. Default = 0. Flash Data Out Register (1Bh) This is a read-only register. Data is valid only if flash busy is zero. This is a 16-bit register that contains the data for a flash read operation. Flash and C-RAM Register Map The flash memory consists of 2048 words by 16 bits.
MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Table 3.
4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC C-RAM ADDRESS 17h 18h 19h 1Ah 1Bh 1Ch FLASH ADDRESS MSB FOR C-RAM 2Eh — 2Fh 31h* — — — — — 3Bh* 3Dh* Not used — Not used — Not used — — LP filter gain for filter stage 1, gain = 1, 2, or 4 LP filter coefficient A2 for filter stage 1, gain = 1, 2, or 4 3Ch 1Eh — EQ gain trim for gain = 4 3Ah* 1Dh Not used EQ gain trim for gain = 2 38h 39h* — ADC gain trim for gain = 4 36h 37h* — Not used ADC g
MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Table 3.
4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC C-RAM ADDRESS 3Bh 3Ch FLASH ADDRESS MSB FOR C-RAM 76h — 77h* 78h 79h* 7Ah* 3Dh 7Bh* 7Ch 3Eh 7Dh* 7Eh* LSB FOR C-RAM Not used ADC gain trim for gain = 32 — — Not used ADC gain trim for gain = 64 — — LP filter gain for filter stage 1, gain = 8 LP filter coefficient A2 for filter stage 1, gain = 8 — — Not used LP filter coefficient A3 for filter stage 1, gain = 8 — MAX11043 Table 3.
MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Digital Filter Coefficients Table 4.
4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Example 1: N = 2.381 A2 = int (2.381 x 213) where N is the decimal coefficient value. The following are two examples of the transfer function equation: Example 2: N = -2.381 A2 = int (-2.381 x 213) A2 = int (-19505.
MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Typical Operating Circuit TO DIGITAL SUPPLY ECHO+ TO ANALOG SUPPLY AINAP DVDD *SEE NOTE AINAN ECHO- REFA AVDD RADAR FRONT END ECHO+ *SEE NOTE ECHO- AINBP AGND AINBN REFB ECHO+ *SEE NOTE AINCP AINCN ECHO- REFC ECHO+ *SEE NOTE MAX11043 CS UP/DWN DACSTEP CONVRUN EOC SHDN SCLK DOUT DIN OSCIN DSP AINDP AINDN ECHO- DGND REFD DVREG AOUT REFBP REFDAC REFDACH REFDACL EXT REF *NOTE: CONNE