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General Description

The MAX1121 is a monolithic 8-bit, 250Msps analog-to-

digital converter (ADC) optimized for outstanding

dynamic performance at high IF frequencies up to

500MHz. The product operates with conversion rates of

up to 250Msps while consuming only 477mW.

At 250Msps and an input frequency of 100MHz, the

MAX1121 achieves a spurious-free dynamic range

(SFDR) of 68dBc. Its excellent signal-to-noise ratio

(SNR) of 48.9dB at 10MHz remains flat (within 0.5dB)

for input tones up to 500MHz. This makes the MAX1121

ideal for wideband applications such as digital predis-

tortion in cellular base-station transceiver systems.

The MAX1121 requires a single 1.8V supply. The ana-

log input is designed for either differential or single-

ended operation and can be AC- or DC-coupled. The

ADC also features a selectable on-chip divide-by-2

clock circuit, which allows the user to apply clock fre-

quencies as high as 500MHz. This helps to reduce the

phase noise of the input clock source. A differential

LVDS sampling clock is recommended for best perfor-

mance. The converter’s digital outputs are LVDS com-

patible, and the data format can be selected to be

either two’s complement or offset binary.

The MAX1121 is available in a 68-pin QFN with

exposed paddle (EP) and is specified over the industri-

al (-40°C to +85°C) temperature range.

For pin-compatible, higher resolution versions of the

MAX1121, refer to the MAX1122 (170Msps), the

MAX1123 (210Msps), and the MAX1124 (250Msps)

data sheets.

Applications

Wireless and Wired Broadband Communication

Digital Oscilloscopes

Digital Predistortion Receivers

Communications Test Equipment

Radar and Satellite Subsystems Antenna Array

Processing

Instrumentation

Features

♦ 250Msps Conversion Rate

♦ SNR = 48.8dB/48.7dB at f

= 100MHz/500MHz

♦ SFDR = 68dBc/63.8dBc at f

= 100MHz/500MHz

♦ Single 1.8V Supply

♦ 477mW Power Dissipation at 250Msps

♦ On-Chip Track-and-Hold and Internal Reference

♦ On-Chip Selectable Divide-by-2 Clock Input

♦ LVDS Digital Outputs with Data Clock Output

♦ Evaluation Kit Available (Order MAX1124EVKIT)

MAX1121

1.8V, 8-Bit, 250Msps Analog-to-Digital Converter

with LVDS Outputs for Wideband Applications

________________________________________________________________ Maxim Integrated Products 1

5859606162 5455565763

AGND

TOP VIEW

OGND

ORP

ORN

D7P

D7N

D6P

D6N

5253

D5P

D5N

AGND

CLKN

CLKP

AGND

OGND

N.C.

D2P

D2N

OGND

DCLKP

DCLKN

D1P

D1N

D0P

D0N

N.C.

AGND

INN

INP

AGND

REFADJ

REFIO

AGND

48 D3N

AGND

656667

AGND

T/B

2322212019 2726252418 2928 323130

N.C.

3433

D4N

D3P

51 D4P

CLKDIV 17

MAX1121

Pin Configuration

Ordering Information

19-3077; Rev 1; 2/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART TEMP RANGE PIN-PACKAGE

MAX1121EGK -40°C to +85°C 68 QFN-EP*

*EP = Exposed paddle.

Summary of content (17 pages)

PAGE 1
9-3077; Rev 1; 2/04 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications Applications ♦ SNR = 48.8dB/48.7dB at fIN = 100MHz/500MHz ♦ SFDR = 68dBc/63.8dBc at fIN = 100MHz/500MHz ♦ Single 1.
PAGE 2
MAX1121 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications ABSOLUTE MAXIMUM RATINGS AVCC to AGND ......................................................-0.3V to +2.1V OVCC to OGND .....................................................-0.3V to +2.1V AVCC to OVCC .......................................................-0.3V to +2.1V AGND to OGND ....................................................-0.3V to +0.3V Analog Inputs to AGND ...........................-0.
PAGE 3
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications (AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins differential RL = 100Ω ±1%, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. ≥25°C guaranteed by production test, <25°C guaranteed by design and characterization. Typical values are at TA = +25°C.
PAGE 4
MAX1121 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications ELECTRICAL CHARACTERISTICS (continued) (AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins differential RL = 100Ω ±1%, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. ≥25°C guaranteed by production test, <25°C guaranteed by design and characterization. Typical values are at TA = +25°C.
PAGE 5
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications FFT PLOT (8192-POINT DATA RECORD, COHERENT SAMPLING) -40 -50 -60 HD2 HD3 -30 -40 -50 HD2 HD3 -60 -30 -40 -50 HD2 -70 -80 -80 -80 -90 -90 40 60 80 100 120 0 140 FFT PLOT (8192-POINT DATA RECORD, COHERENT SAMPLING) -40 HD3 -50 100 120 140 0 40 60 80 100 120 140 SFDR vs. ANALOG INPUT FREQUENCY (fSAMPLE = 250.0057MHz, AIN = -0.
PAGE 6
Typical Operating Characteristics (continued) (AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250.0057MHz, -0.5dBFS; see TOCs for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins differential RL = 100Ω, TA = +25°C.) SNR vs. fSAMPLE (fIN = 60.0294MHz, AIN = -0.5dBFS) 48.0 47.
PAGE 7
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications 49.5 70 480 470 460 48.0 47.5 65 PDISS (mW) 48.5 SFDR (dBc) 60 55 420 50 400 46.5 410 46.0 -40 -15 10 35 60 -40 35 60 85 60 20 100 140 180 220 260 SNR vs. SUPPLY VOLTAGE (fIN = 60.0294MHz, AIN = -0.5dBFS) INTERNAL REFERENCE vs. SUPPLY VOLTAGE (fSAMPLE = 250.0057MHz) 1.2350 MAX1121 toc23 MAX1121 toc22 50 AVCC = OVCC 49 MAX1121 toc24 FS VOLTAGE vs. FS ADJUST RESISTOR 1.
PAGE 8
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications MAX1121 Pin Description 8 PIN NAME 1, 6, 11–14, 20, 25, 62, 63, 65 FUNCTION AVCC Analog Supply Voltage. Bypass each pin with a 0.1µF capacitor for best decoupling results. 2, 5, 7, 10, 15, 16, 18, 19, 21, 24, 64, 66, 67, EP AGND Analog Converter Ground. Connect the converter’s exposed paddle (EP) to AGND. 3 REFIO Reference Input/Output.
PAGE 9
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications PIN NAME 50 D4N Complementary Output Bit 4 51 D4P True Output Bit 4 52 D5N Complementary Output Bit 5 53 D5P True Output Bit 5 54 D6N Complementary Output Bit 6 55 D6P True Output Bit 6 56 D7N Complementary Output Bit 7 57 D7P True Output Bit 7 58 ORN Complementary Output for Out-of-Range Control Bit.
PAGE 10
MAX1121 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications Detailed Description— Theory of Operation The MAX1121 uses a fully differential, pipelined architecture that allows for high-speed conversion, optimized accuracy and linearity, while minimizing power consumption and die size. Both positive (INP) and negative/complementary analog input terminals (INN) are centered around a commonmode voltage of 1.
PAGE 11
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter SAMPLING EVENT SAMPLING EVENT SAMPLING EVENT SAMPLING EVENT MAX1121 INN INP tCL tCH tAD CLKN N N+1 N+8 N+9 CLKP tCPDL tLATENCY DCLKP N-8 N-7 N N+1 DCLKN tCPDL - tPDL tPDL D0P/N–D7P/N ORP/N N-8 N-7 N-1 N N+1 tCPDL - tPDL ~ 0.4 x tSAMPLE with tSAMPLE = 1 / fSAMPLE NOTE: THE ADC SAMPLES ON THE RISING EDGE OF CLKP. THE RISING EDGE OF DCLKP CAN BE USED TO EXTERNALLY LATCH THE OUTPUT DATA. Figure 4.
PAGE 12
MAX1121 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications Divide-by-2 Clock Control (CLKDIV) The MAX1121 offers a clock control line (CLKDIV), which supports the reduction of clock jitter in a system. Connect CLKDIV to OGND to enable the ADC’s internal divide-by-2 clock divider. Data is now updated at onehalf the ADC’s input clock rate.
PAGE 13
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications Full-Scale Range Adjustments Using the Internal Bandgap Reference MAX1121 Applications Information ADC FULL-SCALE = REFT - REFB The MAX1121 supports a full-scale adjustment range of 10% (±5%). To decrease the full-scale range, an external resistor value ranging from 13kΩ to 1MΩ may be added between REFADJ and AGND. A similar approach can be taken to increase the ADCs full-scale range.
PAGE 14
MAX1121 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications AVCC SINGLE-ENDED INPUT TERMINAL 0.1µF 15Ω ADT1–1WT OVCC INP D0P/N–D7P/N 25Ω 25Ω 15Ω MAX1121 INN 8 0.1µF AGND OGND Figure 8.
PAGE 15
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications OVCC AVCC 0.1µF AGND MAX1121 BYPASSING—BOARD LEVEL AVCC BYPASSING—ADC LEVEL 0.1µF 1µF 10µF 47µF 10µF 47µF ANALOG POWERSUPPLY SOURCE OGND D0P/N–D7P/N OVCC MAX1121 8 1µF AGND DIGITAL/OUTPUTDRIVER POWERSUPPLY SOURCE OGND NOTE: EACH POWER-SUPPLY PIN (ANALOG AND DIGITAL) SHOULD BE DECOUPLED WITH AN INDIVIDUAL 0.1µF CAPACITOR CLOSE TO THE ADC. Figure 10.
PAGE 16
MAX1121 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications Static Parameter Definitions CLKP Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified.
PAGE 17
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications 68L QFN.EPS PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2 PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.