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General Description

The MAX1122 is a monolithic 10-bit, 170Msps analog-

to-digital converter (ADC) optimized for outstanding

dynamic performance at high IF frequencies up to

500MHz. The product operates with conversion rates of

up to 170Msps while consuming only 460mW.

At 170Msps and an input frequency of 100MHz, the

MAX1122 achieves a spurious-free dynamic range

(SFDR) of 72dBc. Its excellent signal-to-noise ratio

(SNR) of 57.5dB at 10MHz remains flat (within 1dB) for

input tones up to 500MHz. This makes the MAX1122

ideal for wideband applications such as digital predis-

tortion in cellular base-station transceiver systems.

The MAX1122 requires a single 1.8V supply. The ana-

log input is designed for either differential or single-

ended operation and can be AC- or DC-coupled. The

ADC also features a selectable on-chip divide-by-2

clock circuit, which allows the user to apply clock fre-

quencies as high as 340MHz. This helps to reduce the

phase noise of the input clock source. A differential

LVDS sampling clock is recommended for best perfor-

mance. The converter’s digital outputs are LVDS com-

patible, and the data format can be selected to be

either two’s complement or offset binary.

The MAX1122 is available in a 68-pin QFN with

exposed paddle (EP) and is specified over the industri-

al (-40°C to +85°C) temperature range.

For pin-compatible, higher speed versions of the

MAX1122, refer to the MAX1123 (210Msps) and the

MAX1124 (250Msps) data sheets. For a higher speed,

pin-compatible 8-bit version of the MAX1122, refer to

the MAX1121 data sheet.

Applications

Wireless and Wired Broadband Communication

Cable-Head End Systems

Digital Predistortion Receivers

Communications Test Equipment

Radar and Satellite Subsystems Antenna Array

Processing

Features

♦ 170Msps Conversion Rate

♦ SNR = 57.1dB/56.5dB at f

= 100MHz/500MHz

♦ SFDR = 72dBc/63.5dBc at f

= 100MHz/500MHz

♦ NPR = 53.7dB at f

NOTCH

= 28.8MHz

♦ Single 1.8V Supply

♦ 460mW Power Dissipation at 170Msps

♦ On-Chip Track-and-Hold and Internal Reference

♦ On-Chip Selectable Divide-by-2 Clock Input

♦ LVDS Digital Outputs with Data Clock Output

♦ Evaluation Kit Available (Order MAX1124EVKIT)

MAX1122

1.8V, 10-Bit, 170Msps Analog-to-Digital Converter

with LVDS Outputs for Wideband Applications

________________________________________________________________ Maxim Integrated Products 1

5859606162 5455565763

AGND

TOP VIEW

OGND

ORP

ORN

D9P

D9N

D8P

D8N

5253

D7P

D7N

AGND

CLKN

CLKP

AGND

OGND

N.C.

D4P

D4N

OGND

DCLKP

DCLKN

D3P

D3N

D2P

D2N

D1P

D1N

AGND

INN

INP

AGND

REFADJ

REFIO

AGND

48 D5N

AGND

656667

AGND

T/B

2322212019 2726252418 2928 323130

D0N

D0P

3433

D6N

D5P

51 D6P

CLKDIV 17

MAX1122

Pin Configuration

Ordering Information

19-3027; Rev 1; 2/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART TEMP RANGE PIN-PACKAGE

MAX1122EGK -40°C to +85°C 68 QFN-EP*

*EP = Exposed paddle.

Summary of content (17 pages)

PAGE 1
9-3027; Rev 1; 2/04 1.8V, 10-Bit, 170Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications Applications Wireless and Wired Broadband Communication Cable-Head End Systems Digital Predistortion Receivers Communications Test Equipment Radar and Satellite Subsystems Antenna Array Processing ♦ SNR = 57.1dB/56.5dB at fIN = 100MHz/500MHz ♦ SFDR = 72dBc/63.5dBc at fIN = 100MHz/500MHz ♦ NPR = 53.7dB at fNOTCH = 28.8MHz ♦ Single 1.
PAGE 2
MAX1122 1.8V, 10-Bit, 170Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications ABSOLUTE MAXIMUM RATINGS AVCC to AGND ......................................................-0.3V to +2.1V OVCC to OGND .....................................................-0.3V to +2.1V AVCC to OVCC .......................................................-0.3V to +2.1V AGND to OGND ....................................................-0.3V to +0.3V Analog Inputs to AGND ...........................-0.
PAGE 3
1.8V, 10-Bit, 170Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications (AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 170MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins differential RL = 100Ω ±1%, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. ≥25°C guaranteed by production test, <25°C guaranteed by design and characterization. Typical values are at TA = +25°C.
PAGE 4
MAX1122 1.8V, 10-Bit, 170Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications ELECTRICAL CHARACTERISTICS (continued) (AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 170MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins differential RL = 100Ω ±1%, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. ≥25°C guaranteed by production test, <25°C guaranteed by design and characterization. Typical values are at TA = +25°C.
PAGE 5
1.8V, 10-Bit, 170Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications -30 -50 -60 HD2 -70 -40 -60 HD3 HD2 -40 -50 -90 -90 -90 -100 -100 20 30 40 50 60 70 80 90 0 ANALOG INPUT FREQUENCY (MHz) HD2 -60 50 60 70 80 90 0 58 -80 30 40 50 60 70 80 90 80 75 70 65 56 55 -70 20 SFDR vs. ANALOG INPUT FREQUENCY (fSAMPLE = 169.984MHz, AIN = -0.
PAGE 6
Typical Operating Characteristics (continued) (AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 170.0057MHz, -0.5dBFS; see TOCs for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins differential RL = 100Ω, TA = +25°C.) HD2/HD3 vs. ANALOG INPUT AMPLITUDE (fSAMPLE = 170.0057MHz, fIN = 60.0374MHz) SNR vs. fSAMPLE (fIN = 60.0374MHz, AIN = -0.
PAGE 7
1.8V, 10-Bit, 170Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications 59 58 75 474 468 462 55 54 PDISS (mW) 70 56 SFDR (dBc) 65 60 53 52 450 444 438 432 55 51 426 50 50 -15 10 35 60 85 420 -15 -40 10 TEMPERATURE (°C) 85 50 20 80 FIGURE 6 1.30 59 AVCC = OVCC 58 RESISTOR VALUE APPLIED BETWEEN REFADJ AND AGND 1.2370 SNR (dB) 1.24 1.22 1.2360 56 55 54 52 1.18 1.2355 1.
PAGE 8
Typical Operating Characteristics (continued) (AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 170.0057MHz, -0.5dBFS; see TOCs for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins differential RL = 100Ω, TA = +25°C.) SINAD vs. CLOCK DUTY CYCLE (fIN = 1.4006MHz, fSAMPLE = 169.984MHz, AIN = -0.
PAGE 9
1.8V, 10-Bit, 170Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications PIN NAME FUNCTION 26, 45, 61 OGND Digital Converter Ground. Ground connection for digital circuitry and output drivers. 27, 28, 41, 44, 60 OVCC Digital Supply Voltage. Bypass with a 0.1µF capacitor for best decoupling results. 29–32 N.C.
PAGE 10
MAX1122 1.8V, 10-Bit, 170Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications CLKDIV CLKP CLOCKDIVIDER CONTROL CLKN INPUT BUFFER INP DCLKP DCLKN CLOCK MANAGEMENT T/H INN LVDS DATA PORT 10-BIT PIPELINE QUANTIZER CORE D0P/N–D9P/N 10 2.2kΩ 2.2kΩ ORP REFERENCE ORN COMMON-MODE BUFFER MAX1122 REFIO REFADJ Figure 1. MAX1122 Block Diagram AVCC ADC FULL-SCALE = REFT - REFB REFT INP INN 2.2kΩ G REFB REFERENCE BUFFER REFERENCESCALING AMPLIFIER REFIO 2.2kΩ 0.
PAGE 11
1.8V, 10-Bit, 170Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications SAMPLING EVENT SAMPLING EVENT MAX1122 SAMPLING EVENT SAMPLING EVENT INN INP tCH tAD tCL CLKN N N+1 N+8 N+9 CLKP tCPDL tLATENCY DCLKP N-8 N-7 N N+1 DCLKN tCPDL - tPDL tPDL D0P/N–D9P/N ORP/N N-8 N-7 N-1 N N+1 tCPDL - tPDL ~ 0.4 x tSAMPLE with tSAMPLE = 1/fSAMPLE NOTE: THE ADC SAMPLES ON THE RISING EDGE OF CLKP. THE RISING EDGE OF DCLKP CAN BE USED TO EXTERNALLY LATCH THE OUTPUT DATA.
PAGE 12
MAX1122 1.8V, 10-Bit, 170Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications Table 1. MAX1122 Digital Output Coding INP ANALOG VOLTAGE LEVEL INN ANALOG VOLTAGE LEVEL OUT-OF-RANGE ORP (ORN) BINARY DIGITAL OUTPUT CODE (D9–D0) TWO’S COMPLEMENT DIGITAL OUTPUT CODE (D9–D0) > VCM + 0.3125V < VCM - 0.3125V 1 (0) 11 1111 1111 (exceeds positive full scale, OR set) 01 1111 1111 (exceeds positive full scale, OR set) VCM + 0.3125V VCM - 0.
PAGE 13
1.8V, 10-Bit, 170Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications ADC FULL-SCALE = REFT - REFB The digital outputs D0P/N–D9P/N, DCLKP/N, and ORP/N are LVDS compatible, and data on D0P/N–D9P/N is presented in either binary or two’s complement format (Table 1). The T/B control line is an LVCMOS-compatible input, which allows the user to select the desired output format.
PAGE 14
MAX1122 1.8V, 10-Bit, 170Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications AVCC SINGLE-ENDED INPUT TERMINAL 0.1µF 15Ω ADT1–1WT OVCC INP D0P/N–D9P/N 25Ω 25Ω 15Ω MAX1122 INN 10 0.1µF AGND OGND Figure 8. Transformer-Coupled Analog Input Configuration with Secondary-Side Termination predetermined resistor value between REFADJ and REFIO increases the full-scale range of the data converter.
PAGE 15
1.8V, 10-Bit, 170Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications AVCC MAX1122 BYPASSING—BOARD LEVEL AVCC BYPASSING—ADC LEVEL OVCC 0.1µF AGND 0.1µF 1µF 10µF 47µF 10µF 47µF ANALOG POWERSUPPLY SOURCE OGND D0P/N–D9P/N OVCC MAX1122 10 1µF AGND DIGITAL/OUTPUTDRIVER POWERSUPPLY SOURCE OGND NOTE: EACH POWER-SUPPLY PIN (ANALOG AND DIGITAL) SHOULD BE DECOUPLED WITH AN INDIVIDUAL 0.1µF CAPACITOR CLOSE TO THE ADC. Figure 10.
PAGE 16
MAX1122 1.8V, 10-Bit, 170Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications Static Parameter Definitions CLKP Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified.
PAGE 17
1.8V, 10-Bit, 170Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications 68L QFN.EPS PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2 PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.