Owner manual

MAX1136–MAX1139
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
14 ______________________________________________________________________________________
BIT 7
(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
BIT 0
(LSB)
REG SCAN1 SCAN0 CS3 CS2 CS1 CS0 SGL/DIF
BIT NAME DESCRIPTION
7 REG Register bit 1= setup byte (see Table 1), 0 = configuration byte
6 SCAN1
5 SCAN0
Scan select bits. Two bits select the scanning configuration
(Table 5). Defaulted to 00 at power-up.
4 CS3
3 CS2
2 CS1
1 CS0
Channel select bits. Four bits select which analog input channels are to be used for conversion
(Tables 3 and 4). Defaulted to 0000 at power-up. For MAX1136/MAX1137, CS3 and CS2 are
internally set to 0.
0SGL/DIF
1 = single-ended, 0 = differential (Tables 3 and 4). Defaulted to 1 at power-up. See the Single-
Ended/Differential Input section.
Table 2. Configuration Byte Format
CS3
1
CS2
1
CS1 CS0 AIN0 AIN1 AIN2 AIN3
2
AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11
2
GND
0000+ -
0001 + -
0010 + -
0011 + -
0100 + -
0101 + -
0110 + -
0111 + -
1000 + -
1001 +-
1010 +-
1011
+
-
1 1 0 0 RESERVED
1 1 0 1 RESERVED
1 1 1 0 RESERVED
1 1 1 1 RESERVED
1. For MAX1136/MAX1137, CS3 and CS2 are internally set to 0.
2. When SEL1 = 1, a single-ended read of AIN3/REF (MAX1136/MAX1137) or AIN11/REF (MAX1138/MAX1139) will be ignored; scan
will stop at AIN2 or AIN10.
Table 3. Channel Selection in Single-Ended Mode (SGL/DIF = 1)