Owner manual

MAX1136–MAX1139
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 2.7V to 3.6V (MAX1137/MAX1139), V
DD
= 4.5V to 5.5V (MAX1136/MAX1138), V
REF
= 2.048V (MAX1137/MAX1139), V
REF
=
4.096V (MAX1136/MAX1138), C
REF
= 0.1µF, f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at
T
A
= +25°C. See Tables 1–5 for programming notation.)
TIMING CHARACTERISTICS (Figure 1)
(V
DD
= 2.7V to 3.6V (MAX1137/MAX1139), V
DD
= 4.5V to 5.5V (MAX1136/MAX1138), V
REF
= 2.048V (MAX1137/MAX1139), V
REF
=
4.096V (MAX1136/MAX1138), C
REF
= 0.1µF, f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at
T
A
= +25°C. See Tables 1–5 for programming notation.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Power-Supply Rejection Ratio PSRR Full-scale input (Note 9)
±0.01 ±0.5
LSB/V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS FOR FAST MODE
Serial Clock Frequency f
SCL
400 kHz
Bus Free Time Between a
STOP (P) and a
START (S) Condition
t
BUF
1.3 µs
Hold Time for START (S) Condition t
HD
,
STA
0.6 µs
Low Period of the SCL Clock t
LOW
1.3 µs
High Period of the SCL Clock t
HIGH
0.6 µs
Setup Time for a Repeated START
Condition (Sr)
t
SU
,
STA
0.6 µs
Data Hold Time t
HD
,
DAT
(Note 10) 0 900 ns
Data Setup Time t
SU
,
DAT
100 ns
Rise Time of Both SDA and SCL
Signals, Receiving
t
R
Measured from 0.3V
DD
to 0.7V
DD
20 + 0.1C
B
300 ns
Fall Time of SDA Transmitting
t
F
Measured from 0.3V
DD
to 0.7V
DD
20 + 0.1C
B
300 ns
Setup Time for STOP (P) Condition t
SU
,
STO
0.6 µs
Capacitive Load for Each Bus Line C
B
400 pF
Pulse Width of Spike Suppressed t
SP
50 ns
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (C
B
= 400pF, Note 11)
Serial Clock Frequency f
SCLH
(Note 12) 1.7 MHz
Hold Time, Repeated START
Condition (Sr)
t
HD
,
STA
160 ns
Low Period of the SCL Clock t
LOW
320 ns
High Period of the SCL Clock t
HIGH
120 ns
Setup Time for a Repeated START
Condition (Sr)
t
SU
,
STA
160 ns
Data Hold Time t
HD
,
DAT
(Note 10) 0 150 ns
Data Setup Time t
SU
,
DAT
10 ns