User Manual

MAX1144/MAX1145
14-Bit ADCs, 150ksps, 3.3V Single Supply
4 _______________________________________________________________________________________
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Hysteresis V
HYST
0.2 V
Input Capacitance C
IN
10 pF
DIGITAL OUTPUTS
Output High Voltage V
OH
I
SOURCE
= 0.5mA
DV
DD
-
0.5
V
I
SINK
= 5mA 0.4
Output Low Voltage V
OL
I
SINK
= 16mA 0.8
V
Three-State Leakage Current I
L
CS = DV
DD
-10 +10 µA
Three-State Output Capacitance CS = DV
DD
10 pF
POWER SUPPLIES
Analog Supply AV
DD
3.135 3.3 3.465 V
Digital Supply DV
DD
3.135 3.3 3.465 V
Unipolar mode 3.9 8
Bipolar mode 7 11
mA
Analog Supply Current I
ANALOG
SHDN = 0, or software power-down mode 0.1 10 µA
Unipolar or bipolar mode 1 2 mA
Digital Supply Current I
DIGITAL
SHDN = 0, or software power-down mode 1.1 10 µA
Power-Supply Rejection Ratio
(Note 8)
PSRR AV
DD
= DV
DD
= 3.135V to 3.465V 65 dB
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= DV
DD
= 3.3V ±5%, f
SCLK
= 3.6MHz, external clock (50% duty cycle), 24 clocks/conversion (150ksps), bipolar input, V
REF
=
2.048V, C
REF
= 4.7µF, C
CREF
= 1µF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
TIMING CHARACTERISTICS (Figures 5 and 6)
(AV
DD
= DV
DD
= 3.3V ±5%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIN to SCLK Setup t
DS
50 ns
DIN to SCLK Hold t
DH
0ns
SCLK to DOUT Valid t
DO
70 ns
CS Fall to DOUT Enable t
DV
C
LOAD
= 50pF 80 ns
CS Rise to DOUT Disable t
TR
C
LOAD
= 50pF 80 ns
CS to SCLK Rise Setup t
CSS
100 ns
CS to SCLK Rise Hold t
CSH
0ns
SCLK High Pulse Width t
CH
120 ns
SCLK Low Pulse Width t
CL
120 ns
SCLK Fall to SSTRB t
SSTRB
C
LOAD
= 50pF 80 ns
CS Fall to SSTRB Enable t
SDV
C
LOAD
= 50pF, external clock mode 80 ns
CS Rise to SSTRB Disable t
STR
C
LOAD
= 50pF, external clock mode 80 ns
SSTRB Rise to SCLK Rise t
SCK
Internal clock mode 0 ns
RST Pulse Width t
RS
278 70 ns