Instruction Manual

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General Description

The MAX1209 is a 3.3V, 12-bit, 80Msps analog-to-digital

converter (ADC) featuring a fully differential wideband

track-and-hold (T/H) input amplifier, driving a low-noise

internal quantizer. The analog input stage accepts sin-

gle-ended or differential signals. The MAX1209 is opti-

mized for low power, small size, and high dynamic

performance. Excellent dynamic performance is main-

tained from baseband to input frequencies of 175MHz

and beyond, making the MAX1209 ideal for intermediate-

frequency (IF) sampling applications.

Powered from a single 3.0V to 3.6V supply, the

MAX1209 consumes only 366mW while delivering a

typical signal-to-noise (SNR) performance of 66.5dB at

an input frequency of 175MHz. In addition to low oper-

ating power, the MAX1209 features a 3µW power-down

mode to conserve power during idle periods.

A flexible reference structure allows the MAX1209 to use

the internal 2.048V bandgap reference or accept an

externally applied reference. The reference structure

allows the full-scale analog input range to be adjusted

from ±0.35V to ±1.15V. The MAX1209 provides a com-

mon-mode reference to simplify design and reduce exter-

nal component count in differential analog input circuits.

The MAX1209 supports both a single-ended and differ-

ential input clock drive. Wide variations in the clock

duty cycle are compensated with the ADC’s internal

duty-cycle equalizer (DCE).

ADC conversion results are available through a 12-bit,

parallel, CMOS-compatible output bus. The digital out-

put format is pin selectable to be either two’s comple-

ment or Gray code. A data-valid indicator eliminates

external components that are normally required for reli-

able digital interfacing. A separate digital power input

accepts a wide 1.7V to 3.6V supply, allowing the

MAX1209 to interface with various logic levels.

The MAX1209 is available in a 6mm x 6mm x 0.8mm,

40-pin thin QFN package with exposed paddle (EP),

and is specified for the extended industrial (-40°C to

+85°C) temperature range.

See the Pin-Compatible Versions table for a complete

family of 14-bit and 12-bit high-speed ADCs.

Applications

IF Communication Receivers

Cellular, Point-to-Point Microwave, HFC, WLAN

Ultrasound and Medical Imaging

Portable Instrumentation

Low-Power Data Acquisition

Features

♦ Direct IF Sampling Up to 400MHz

♦ Excellent Dynamic Performance

68.0dB/66.5dB SNR at f

= 70MHz/175MHz

85.1dBc/85.5dBc SFDR at f

= 70MHz/175MHz

♦ 3.3V Low-Power Operation

366mW (Single-Ended Clock Mode)

393mW (Differential Clock Mode)

3µW (Power-Down Mode)

♦ Differential or Single-Ended Clock

♦ Fully Differential or Single-Ended Analog Input

♦ Adjustable Full-Scale Analog Input Range: ±0.35V

to ±1.15V

♦ Common-Mode Reference

♦ CMOS-Compatible Outputs in Two’s Complement

or Gray Code

♦ Data-Valid Indicator Simplifies Digital Design

♦ Data Out-of-Range Indicator

♦ Miniature, 40-Pin Thin QFN Package with Exposed

Paddle

♦ Evaluation Kit Available (Order MAX1211EVKIT)

MAX1209

12-Bit, 80Msps, 3.3V IF-Sampling ADC

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-1001; Rev 0; 8/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART

TEMP

RANGE

PIN-PACKAGE

PKG

CODE

MAX1209ETL

-40°C to

+85°C

40 Thin QFN

(6mm x 6mm x 0.8mm)

T4066-3

Pin-Compatible Versions

PART

SAMPLING

RATE (Msps)

RESOLUTION

(BITS)

TARGET

APPLICATION

MAX12553 65 14 IF/Baseband

MAX1209 80 12 IF

MAX1211 65 12 IF

MAX1208 80 12 Baseband

MAX1207 65 12 Baseband

MAX1206 40 12 Baseband

Pin Configuration appears at end of data sheet.

Summary of content (27 pages)

PAGE 1
9-1001; Rev 0; 8/04 KIT ATION EVALU E L B AVAILA 12-Bit, 80Msps, 3.3V IF-Sampling ADC Applications IF Communication Receivers Cellular, Point-to-Point Microwave, HFC, WLAN Ultrasound and Medical Imaging Portable Instrumentation Features ♦ Direct IF Sampling Up to 400MHz ♦ Excellent Dynamic Performance 68.0dB/66.5dB SNR at fIN = 70MHz/175MHz 85.1dBc/85.5dBc SFDR at fIN = 70MHz/175MHz ♦ 3.
PAGE 2
MAX1209 12-Bit, 80Msps, 3.3V IF-Sampling ADC ABSOLUTE MAXIMUM RATINGS VDD to GND ...........................................................-0.3V to +3.6V OVDD to GND........-0.3V to the lower of (VDD + 0.3V) and +3.6V INP, INN to GND ...-0.3V to the lower of (VDD + 0.3V) and +3.6V REFIN, REFOUT, REFP, REFN, COM to GND................-0.3V to the lower of (VDD + 0.3V) and +3.6V CLKP, CLKN, CLKTYP, G/T, DCE, PD to GND ........-0.3V to the lower of (VDD + 0.3V) and +3.6V D11 Through D0, I.C.
PAGE 3
12-Bit, 80Msps, 3.3V IF-Sampling ADC (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 80MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN fIN = 70MHz at -0.
PAGE 4
MAX1209 12-Bit, 80Msps, 3.3V IF-Sampling ADC ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 80MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX 2.048 2.
PAGE 5
12-Bit, 80Msps, 3.3V IF-Sampling ADC (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 80MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 6
MAX1209 12-Bit, 80Msps, 3.3V IF-Sampling ADC ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 80MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Analog Power Dissipation Digital Output Supply Current SYMBOL PDISS IOVDD CONDITIONS MIN TYP Normal operating mode, fIN = 175MHz at -0.
PAGE 7
12-Bit, 80Msps, 3.3V IF-Sampling ADC SINGLE-TONE FFT PLOT (4096-POINT DATA RECORD) -10 -20 -10 -50 HD3 HD2 -70 HD4 -40 -50 -60 HD4 -70 HD2 HD3 -80 -40 -50 -60 -90 -90 -100 -100 -110 4 8 12 16 20 24 28 32 36 40 FREQUENCY (MHz) -50 fIN2 - fIN1 -60 fIN2 + fIN1 -70 0.6 0.8 0.6 0.4 0.4 0.2 0.2 0 -0.2 0 -0.2 -0.4 -90 -0.6 -100 -0.8 -0.8 -110 -1.0 4 8 12 16 20 24 28 32 36 40 FREQUENCY (MHz) fCLK = 80MHz fIN1 = 172.4853516MHz AIN1 = -6.976dBFS fIN2 = 177.
PAGE 8
Typical Operating Characteristics (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 80MHz (50% duty cycle), TA = +25°C, unless otherwise noted.) 90 67 66 65 64 85 80 75 70 63 62 40 60 80 100 0 20 fCLK (MHz) 100 MAX1209 toc10 40 60 80 100 SFDR, -THD (dBc) 67 66 65 64 fIN ≈ 175MHz 85 80 75 70 SNR SINAD 63 80 0 20 40 60 80 SNR, SINAD vs. ANALOG INPUT FREQUENCY SFDR, -THD vs.
PAGE 9
12-Bit, 80Msps, 3.3V IF-Sampling ADC SFDR, -THD vs. ANALOG INPUT AMPLITUDE 45 40 70 65 60 55 35 50 SNR SINAD 30 25 40 -35 -30 -25 -20 -15 -10 -5 0 ANALOG INPUT AMPLITUDE (dBFS) -25 -20 -15 -10 -5 100 95 -40 0 fCLK = 80.03584MHz fIN = 32.11399MHz SFDR, -THD (dBc) 66 65 64 63 80 75 2.8 3.0 3.2 fCLK = 80.03584MHz fIN = 32.11399MHz 69 68 300 3.0 3.2 3.6 3.4 64 63 100 fCLK = 80.03584MHz fIN = 32.11399MHz 95 550 SNR SINAD 85 80 75 2.2 2.6 OVDD (V) 3.0 3.4 3.
PAGE 10
Typical Operating Characteristics (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 80MHz (50% duty cycle), TA = +25°C, unless otherwise noted.) 65 89 87 85 83 81 64 79 SNR SINAD 63 SFDR -THD 77 75 62 -40 -15 10 35 60 -15 10 35 60 85 MAX1209 toc27 350 300 250 -40 -15 0.3 35 GAIN ERROR vs. TEMPERATURE 3 MAX1209 toc28 VREFIN = 2.048V 10 TEMPERATURE (°C) OFFSET ERROR vs.
PAGE 11
12-Bit, 80Msps, 3.3V IF-Sampling ADC REFERENCE OUTPUT VOLTAGE LOAD REGULATION 2.03 3.0 2.5 1.99 2.031 0.5 1.96 1.95 -1.5 -1.0 -0.5 0 -40°C 2.029 0 0.5 -3.0 -2.0 IREFOUT SINK CURRENT (mA) -1.0 0 -40 1.0 -15 35 60 85 REFP, COM, REFN SHORT-CIRCUIT PERFORMANCE 3.5 MAX1209 toc33 3.0 3.0 2.0 VCOM VCOM 2.5 VOLTAGE (V) VREFP 1.5 -10 TEMPERATURE (°C) IREFOUT SINK CURRENT (mA) REFP, COM, REFN LOAD REGULATION 2.5 2.033 1.0 +25°C -2.0 1.5 2.035 MAX1209 toc34 1.97 2.
PAGE 12
-Bit, 80Msps, 3.3V IF-Sampling ADC MAX1209 Pin Description PIN NAME FUNCTION REFP Positive Reference I/O. The full-scale analog input range is ±(VREFP - VREFN). Bypass REFP to GND with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP and REFN. Place the 1µF REFP to REFN capacitor as close to the device as possible on the same side of the printed circuit (PC) board. 2 REFN Negative Reference I/O. The full-scale analog input range is ±(VREFP - VREFN).
PAGE 13
12-Bit, 80Msps, 3.3V IF-Sampling ADC PIN NAME 28 D2 CMOS Digital Output, Bit 2 FUNCTION 29 D1 CMOS Digital Output, Bit 1 30 D0 CMOS Digital Output, Bit 0 (LSB) 31, 32 I.C. Internally Connected. Leave I.C. unconnected. 33 DAV Data-Valid Output. DAV is a single-ended version of the input clock that is compensated to correct for any input clock duty-cycle variations. DAV is typically used to latch the MAX1209 output data into an external back-end digital circuit.
PAGE 14
MAX1209 12-Bit, 80Msps, 3.3V IF-Sampling ADC CLKP CLKN DCE CLKTYP CLOCK GENERATOR AND DUTY-CYCLE EQUALIZER MAX1209 VDD GND OVDD INP INN T/H 12-BIT PIPELINE ADC DEC OUTPUT DRIVERS MAX1209 CPAR 2pF *CSAMPLE 1.9pF CPAR 2pF *CSAMPLE 1.9pF D11–D0 DAV DOR BOND WIRE INDUCTANCE 1.5nH VDD INN REFIN COM VDD INP G/T REFOUT REFP BOND WIRE INDUCTANCE 1.5nH REFERENCE SYSTEM POWER CONTROL AND BIAS CIRCUITS PD REFN Figure 2.
PAGE 15
12-Bit, 80Msps, 3.3V IF-Sampling ADC MAX1209 CLKP CLKN tAD ANALOG INPUT tAJ SAMPLED DATA T/H TRACK HOLD TRACK HOLD TRACK HOLD TRACK HOLD Figure 4. T/H Aperture Timing REFOUT sources up to 1.0mA and sinks up to 0.1mA for external circuits with a load regulation of 35mV/mA. Short-circuit protection limits I REFOUT to a 2.1mA source current when shorted to GND and a 0.24mA sink current when shorted to VDD.
PAGE 16
MAX1209 12-Bit, 80Msps, 3.3V IF-Sampling ADC All three modes of reference operation require the same bypass capacitor combinations. Bypass COM with a 2.2µF capacitor to GND. Bypass REFP and REFN each with a 0.1µF capacitor to GND. Bypass REFP to REFN with a 1µF capacitor in parallel with a 10µF capacitor. Place the 1µF capacitor as close to the device as possible on the same side of the PC board. Bypass REFIN and REFOUT to GND with a 0.1µF capacitor. For detailed circuit suggestions, see Figures 13 and 14.
PAGE 17
12-Bit, 80Msps, 3.3V IF-Sampling ADC (VREFP - VREFN) N+5 N+3 N-3 N-2 N-1 N N+1 MAX1209 N+4 DIFFERENTIAL ANALOG INPUT (INP–INN) N+6 N+2 N+7 N+9 N+8 (VREFN - VREFP) tAD CLKN CLKP tDAV tCL tCH DAV tSETUP D11–D0 tHOLD N-3 N-2 N-1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 tSETUP 8.5 CLOCK-CYCLE DATA LATENCY N+8 N+9 tHOLD DOR Figure 6. System Timing Diagram The state of the duty-cycle equalizer input (DCE) changes the waveform at DAV.
PAGE 18
MAX1209 12-Bit, 80Msps, 3.3V IF-Sampling ADC VINP − VINN = (VREFP − VREFN ) × 2 × CODE10 4096 for two’s complement (G/T = 0) where CODE10 is the decimal equivalent of the digital output code as shown in Table 2. Digital outputs D11–D0 are high impedance when the MAX1209 is in power-down (PD = high). D11–D0 transition high 10ns after the rising edge of PD and become active 10ns after PD’s falling edge.
PAGE 19
12-Bit, 80Msps, 3.3V IF-Sampling ADC VREF = VREFP - VREFN 1 LSB = VREF 0x7FF 0x7FE 0x7FD 2 x VREF 4096 VREF VREF = VREFP - VREFN VREF 0x800 0x801 0x803 GRAY OUTPUT CODE (LSB) TWO'S COMPLEMENT OUTPUT CODE (LSB) 2 x VREF 4096 VREF MAX1209 1 LSB = 0x001 0x000 0xFFF 0x803 0x802 0x801 0x800 0xC01 0xC00 0x400 0x002 0x003 0x001 0x000 -2047 -2045 -1 0 +1 +2045 +2047 DIFFERENTIAL INPUT VOLTAGE (LSB) Figure 7.
PAGE 20
MAX1209 12-Bit, 80Msps, 3.3V IF-Sampling ADC BINARY-TO-GRAY CODE CONVERSION GRAY-TO-BINARY CODE CONVERSION 1) THE MOST SIGNIFICANT GRAY-CODE BIT IS THE SAME AS THE MOST SIGNIFICANT BINARY BIT. 1) THE MOST SIGNIFICANT BINARY BIT IS THE SAME AS THE MOST SIGNIFICANT GRAY-CODE BIT.
PAGE 21
12-Bit, 80Msps, 3.3V IF-Sampling ADC T1 N.C. 2 VIN 0.1µF 12pF 6 1 VIN MAX4108 INP 0.1µF INP MAX1209 5 5.6pF 100Ω COM 24.9Ω MAX1209 2.2µF 3 4 MINICIRCUITS TT1-6 OR T1-1T MAX1209 24.9Ω COM 2.2µF 24.9Ω 100Ω INN 24.9Ω 12pF INN 5.6pF Figure 10. Transformer-Coupled Input Drive for Input Frequencies Up to Nyquist Figure 12. Single-Ended, AC-Coupled Input Drive The circuit of Figure 11 converts a single-ended input signal to fully differential just as Figure 10.
PAGE 22
MAX1209 12-Bit, 80Msps, 3.3V IF-Sampling ADC +3.3V 0.1µF 2.2µF 0.1µF +3.3V 1 2 VDD MAX6029EUK21 38 0.1µF 5 REFP REFOUT 0.1µF 1µF* 2.048V 0.1µF REFN 2 0.1µF +3.3V 39 16.2kΩ 1 10µF MAX1209 NOTE: ONE FRONT-END REFERENCE CIRCUIT IS CAPABLE OF SOURCING 15mA AND SINKING 30mA OF OUTPUT CURRENT. 1µF 1 5 MAX4230 4 3 3 REFIN GND COM 2.2µF 2.048V 47Ω +3.3V 2 10µF 6V 330µF 6V 0.1µF 2.2µF 0.1µF 1.
PAGE 23
12-Bit, 80Msps, 3.3V IF-Sampling ADC MAX1209 +3.3V 1 0.1µF MAX6066 2 +3.3V 5 0.1µF +3.3V 2.2µF 3.000V 0.1µF 0.1µF 1 24.3kΩ 1% 5 MAX4230 4 3 1 10µF 6V 330µF 6V 10µF 0.1µF MAX1209 2 0.1µF +3.3V REFN 0.1µF 26.7kΩ 1% 1 26.7kΩ 1% 5 10µF 6V COM REFIN GND 39 2.2µF +3.3V 330µF 6V 2.2µF 0.1µF 20kΩ 1% 20kΩ 1% 1.649V 47Ω 4 3 3 MAX4230 2 20kΩ 1% 38 1µF* 1.47kΩ 0.47µF VDD REFP REFOUT 2 20kΩ 1% 2.157V 47Ω 0.1µF 1.47kΩ 0.1µF +3.3V 1 1 5 38 1.141V 10µF 47Ω 0.
PAGE 24
MAX1209 12-Bit, 80Msps, 3.3V IF-Sampling ADC chain providing 2.157V, 1.649V, and 1.141V to the MAX1209’s REFP, COM, and REFN reference inputs, respectively. The feedback around the MAX4230 op amps provides additional 10Hz lowpass filtering. The 2.157V and 1.141V reference voltages set the full-scale analog input range to ±1.016V. A common power source for all active components removes any concern regarding power-supply sequencing when powering up or down.
PAGE 25
12-Bit, 80Msps, 3.3V IF-Sampling ADC Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset. Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only.
PAGE 26
Aperture Jitter Overdrive Recovery Time Overdrive recovery time is the time required for the ADC to recover from an input transient that exceeds the full-scale limits. The MAX1209 specifies overdrive recovery time using an input transient that exceeds the full-scale limits by ±10%. I.C. I.C.
PAGE 27
12-Bit, 80Msps, 3.3V IF-Sampling ADC QFN THIN 6x6x0.8.EPS D2 D CL D/2 b D2/2 k E/2 E2/2 (NE-1) X e E CL E2 k e L (ND-1) X e e L CL CL L1 L L e A1 A2 e A PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm 21-0141 E 1 2 NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012.