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General Description

The MAX12553 is a 3.3V, 14-bit, 65Msps analog-to-digital

converter (ADC) featuring a fully differential wideband

track-and-hold (T/H) input amplifier, driving a low-noise

internal quantizer. The analog input stage accepts single-

ended or differential signals. The MAX12553 is optimized

for low-power, small size, and high dynamic perfor-

mance. Excellent dynamic performance is maintained

from baseband to input frequencies of 175MHz and

beyond, making the MAX12553 ideal for intermediate-

frequency (IF) sampling applications.

Powered from a single 3.15V to 3.60V supply, the

MAX12553 consumes only 363mW while delivering a

typical signal-to-noise (SNR) performance of 71dB at

an input frequency of 175MHz. In addition to low oper-

ating power, the MAX12553 features a 150µW power-

down mode to conserve power during idle periods.

A flexible reference structure allows the MAX12553 to use

the internal 2.048V bandgap reference or accept an

externally applied reference. The reference structure

allows the full-scale analog input range to be adjusted

from ±0.35V to ±1.10V. The MAX12553 provides a com-

mon-mode reference to simplify design and reduce exter-

nal component count in differential analog input circuits.

The MAX12553 supports both a single-ended and dif-

ferential input clock drive. Wide variations in the clock

duty cycle are compensated with the ADC’s internal

duty-cycle equalizer (DCE).

ADC conversion results are available through a 14-bit,

parallel, CMOS-compatible output bus. The digital out-

put format is pin selectable to be either two’s comple-

ment or Gray code. A data-valid indicator eliminates

external components that are normally required for reli-

able digital interfacing. A separate digital power input

accepts a wide 1.7V to 3.6V supply, allowing the

MAX12553 to interface with various logic levels.

The MAX12553 is available in a 6mm x 6mm x 0.8mm,

40-pin thin QFN package with exposed paddle (EP),

and is specified for the extended industrial (-40°C to

+85°C) temperature range.

See the Pin-Compatible Versions table for a complete

family of 14-bit and 12-bit high-speed ADCs.

Applications

IF and Baseband Communication Receivers

Cellular, Point-to-Point Microwave, HFC, WLAN

Ultrasound and Medical Imaging

Portable Instrumentation

Low-Power Data Acquisition

Features

♦ Direct IF Sampling Up to 400MHz

♦ Excellent Dynamic Performance

74.0dB/71dB SNR at f

= 3MHz/175MHz

90.6dBc/80.7dBc SFDR at f

= 3MHz/175MHz

♦ Low Noise Floor: -76dBFS

♦ 3.3V Low-Power Operation

337mW (Single-Ended Clock Mode)

363mW (Differential Clock Mode)

150µW (Power-Down Mode)

♦ Fully Differential or Single-Ended Analog Input

♦ Adjustable Full-Scale Analog Input Range: ±0.35V

to ±1.10V

♦ Common-Mode Reference

♦ CMOS-Compatible Outputs in Two’s Complement

or Gray Code

♦ Data-Valid Indicator Simplifies Digital Interface

♦ Data Out-of-Range Indicator

♦ Miniature, 40-Pin Thin QFN Package with Exposed

Paddle

♦ Evaluation Kit Available (Order MAX12555EVKIT)

MAX12553

14-Bit, 65Msps, 3.3V ADC

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-3343; Rev 0; 8/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART

TEMP

RANGE

PIN-PACKAGE

PKG

CODE

MAX12553ETL

-40°C to

+85°C

40 Thin QFN

(6mm x 6mm x 0.8mm)

T4066-3

Pin-Compatible Versions

PART

SAMPLING

RATE (Msps)

RESOLUTION

(BITS)

TARGET

APPLICATION

MAX12553 65 14 IF/Baseband

MAX1209 80 12 IF

MAX1211 65 12 IF

MAX1208 80 12 Baseband

MAX1207 65 12 Baseband

MAX1206 40 12 Baseband

Pin Configuration appears at end of data sheet.

Summary of content (28 pages)

PAGE 1
9-3343; Rev 0; 8/04 KIT ATION EVALU LE B A IL A AV 14-Bit, 65Msps, 3.3V ADC Features ♦ Direct IF Sampling Up to 400MHz ♦ Excellent Dynamic Performance 74.0dB/71dB SNR at fIN = 3MHz/175MHz 90.6dBc/80.7dBc SFDR at fIN = 3MHz/175MHz ♦ Low Noise Floor: -76dBFS ♦ 3.3V Low-Power Operation 337mW (Single-Ended Clock Mode) 363mW (Differential Clock Mode) 150µW (Power-Down Mode) ♦ Fully Differential or Single-Ended Analog Input ♦ Adjustable Full-Scale Analog Input Range: ±0.35V to ±1.
PAGE 2
MAX12553 14-Bit, 65Msps, 3.3V ADC ABSOLUTE MAXIMUM RATINGS Continuous Power Dissipation (TA = +70°C) 40-Pin Thin QFN 6mm x 6mm x 0.8mm (derated 26.3mW/°C above +70°C)........................2105.3mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering 10s) ..................................+300°C VDD to GND ...
PAGE 3
14-Bit, 65Msps, 3.3V ADC (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 65MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS fIN = 3MHz at -0.
PAGE 4
MAX12553 14-Bit, 65Msps, 3.3V ADC ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 65MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 2.048 2.
PAGE 5
14-Bit, 65Msps, 3.3V ADC (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 65MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 6
MAX12553 14-Bit, 65Msps, 3.3V ADC ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 65MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Analog Power Dissipation Digital Output Supply Current SYMBOL PDISS IOVDD CONDITIONS MIN TYP MAX UNITS Normal operating mode, fIN = 175MHz at -0.
PAGE 7
14-Bit, 65Msps, 3.3V ADC HD2 HD3 -110 -120 -50 -60 -70 -80 -90 -100 HD2 4 8 HD3 12 16 20 24 28 32 -110 -120 0 4 8 12 16 20 24 28 32 0 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 HD3 HD2 0 -10 -20 -30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) HD5 fCLK = 64.96256MHz fIN = 250.00911MHz AIN = -0.494dBFS SNR = 69.39dB SINAD = 68.67dB THD = -76.8dBc SFDR = 78.6dBc 16 20 24 28 8 12 16 20 24 28 32 0 4 8 12 16 20 24 28 32 0 INTEGRAL NONLINEARITY 12 16 1.
PAGE 8
Typical Operating Characteristics (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK ≈ 65MHz (50% duty cycle), TA = +25°C, unless otherwise noted.) SFDR, -THD vs. SAMPLING RATE 90 72 71 70 69 68 85 80 75 70 67 65 SNR SINAD 66 65 20 40 60 80 ANALOG + DIGITAL POWER ANALOG POWER 200 0 20 40 60 80 20 0 40 60 SFDR, -THD vs. SAMPLING RATE POWER DISSIPATION vs.
PAGE 9
14-Bit, 65Msps, 3.3V ADC SFDR, -THD vs. ANALOG INPUT AMPLITUDE 55 50 45 40 80 70 60 50 450 35 40 SNR SINAD 30 25 30 -35 -30 -25 -20 -15 -10 0 -5 -30 -25 -20 -15 -10 0 -5 -40 -35 -30 -25 -20 -15 -10 POWER DISSIPATION vs. ANALOG SUPPLY VOLTAGE 90 72 71 70 69 85 80 75 70 67 SNR SINAD 66 3.2 3.4 3.6 2.8 3.0 VDD (V) 3.2 3.4 3.6 2.6 73 100 71 70 69 68 fCLK = 65MHz fIN = 174.9007416MHz 95 85 80 75 70 SNR SINAD SFDR -THD 65 2.6 OVDD (V) 3.0 3.4 3.8 3.2 3.
PAGE 10
Typical Operating Characteristics (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK ≈ 65MHz (50% duty cycle), TA = +25°C, unless otherwise noted.
PAGE 11
14-Bit, 65Msps, 3.3V ADC REFERENCE OUTPUT VOLTAGE LOAD REGULATION 2.03 3.0 2.5 1.99 1.97 2.0 1.5 +25°C 2.031 0.5 1.95 -1.5 -1.0 2.033 1.0 1.96 -0.5 0 -40°C 0 0.5 2.029 -2.0 -3.0 IREFOUT SINK CURRENT (mA) -1.0 0 1.0 -15 -40 IREFOUT SINK CURRENT (mA) 35 60 85 REFP, COM, REFN SHORT-CIRCUIT PERFORMACE VREFP 3.5 2.5 MAX12553 toc37 3.0 3.0 VCOM 2.5 VOLTAGE (V) 2.0 1.5 VREFN 10 TEMPERATURE (°C) REFP, COM, REFN LOAD REGULATION MAX12553 toc36 -2.0 2.035 +25°C -40°C 1.
PAGE 12
14-Bit, 65Msps, 3.3V ADC MAX12553 Pin Description PIN NAME FUNCTION REFP Positive Reference I/O. The full-scale analog input range is ±(VREFP - VREFN) x 2/3. Bypass REFP to GND with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP and REFN. Place the 1µF REFP to REFN capacitor as close to the device as possible on the same side of the PC board. 2 REFN Negative Reference I/O. The full-scale analog input range is ±(VREFP - VREFN) x 2/3.
PAGE 13
14-Bit, 65Msps, 3.3V ADC PIN NAME 28 D4 CMOS Digital Output, Bit 4 FUNCTION 29 D3 CMOS Digital Output, Bit 3 30 D2 CMOS Digital Output, Bit 2 31 D1 CMOS Digital Output, Bit 1 32 D0 CMOS Digital Output, Bit 0 (LSB) 33 DAV 37 PD 38 REFOUT 39 REFIN 40 G/T Output Format Select Input. Connect G/T to GND for the two’s complement digital output format. Connect G/T to OVDD or VDD for the Gray code digital output format. — EP Exposed Paddle.
PAGE 14
MAX12553 14-Bit, 65Msps, 3.3V ADC CLKP CLKN DCE CLKTYP CLOCK GENERATOR AND DUTY-CYCLE EQUALIZER MAX12553 VDD GND BOND WIRE INDUCTANCE 1.5nH VDD INP OVDD INP INN T/H 14-BIT PIPELINE ADC DEC OUTPUT DRIVERS DOR *CSAMPLE 4.5pF BOND WIRE INDUCTANCE 1.5nH CPAR 2pF *CSAMPLE 4.5pF VDD INN REFIN COM CPAR 2pF D13–D0 DAV G/T REFOUT REFP MAX12553 REFERENCE SYSTEM POWER CONTROL AND BIAS CIRCUITS PD REFN Figure 2.
PAGE 15
14-Bit, 65Msps, 3.3V ADC MAX12553 CLKP CLKN tAD ANALOG INPUT tAJ SAMPLED DATA T/H TRACK HOLD TRACK HOLD TRACK HOLD TRACK HOLD Figure 4. T/H Aperture Timing REFOUT sources up to 1.0mA and sinks up to 0.1mA for external circuits with a load regulation of 35mV/mA. Short-circuit protection limits I REFOUT to a 2.1mA source current when shorted to GND and a 0.24mA sink current when shorted to VDD.
PAGE 16
MAX12553 14-Bit, 65Msps, 3.3V ADC All three modes of reference operation require the same bypass capacitor combinations. Bypass COM with a 2.2µF capacitor to GND. Bypass REFP and REFN each with a 0.1µF capacitor to GND. Bypass REFP to REFN with a 1µF capacitor in parallel with a 10µF capacitor. Place the 1µF capacitor as close to the device as possible on the same side of the PC board. Bypass REFIN and REFOUT to GND with a 0.1µF capacitor. For detailed circuit suggestions, see Figure 13 and Figure 14.
PAGE 17
14-Bit, 65Msps, 3.3V ADC (VREFP - VREFN) x 2/3 N+5 N+3 N-3 N-2 N-1 N N+1 MAX12553 N+4 DIFFERENTIAL ANALOG INPUT (INP–INN) N+6 N+2 N+7 N+9 N+8 (VREFN - VREFP) x 2/3 tAD CLKN CLKP tDAV tCL tCH DAV tSETUP tHOLD D13–D0 N-3 8.5 CLOCK-CYCLE DATA LATENCY N-2 N-1 N N+1 N+2 N+3 N+4 N+5 tSETUP N+6 N+7 N+8 N+9 tHOLD DOR Figure 6.
PAGE 18
MAX12553 14-Bit, 65Msps, 3.3V ADC Data Out-of-Range Indicator (DOR) The DOR digital output indicates when the analog input voltage is out of range. When DOR is high, the analog input is out of range. When DOR is low, the analog input is within range. The valid differential input range is from (VREFP - VREFN) x 3/4 to (VREFN - VREFP) x 3/4. Signals outside this valid differential range cause DOR to assert high as shown in Table 2 and Figure 6.
PAGE 19
______________________________________________________________________________________ 0 0 0 0 1 01 0000 0000 0000 01 0000 0000 0001 00 0000 0000 0001 00 0000 0000 0000 00 0000 0000 0000 0 11 0000 0000 0011 0 0 10 0000 0000 0001 0 0 10 0000 0000 0000 11 0000 0000 0000 1 10 0000 0000 0000 11 0000 0000 0001 DOR BINARY D13 ➝ D0 0x0000 0x0000 0x0001 0x1001 0x1000 0x3000 0x3001 0x3003 0x2001 0x2000 0x2000 0 0 +1 +8190 +8191 +8192 +8193 +8194 +16382 +16383 +16383 DECIMAL H
PAGE 20
1 LSB = VREFP - VREFN 4 x 3 16384 (VREFP - VREFN) x 2/3 1 LSB = (VREFP - VREFN) x 2/3 0x2000 0x1FFE 0x1FFD 0x2001 0x2003 0x0001 0x0000 0x3FFF 0x3000 0x1000 0x0002 0x0003 0x2001 0x2000 0x0001 0x0000 -1 0 +1 +8189 +8191 DIFFERENTIAL INPUT VOLTAGE (LSB) (VREFP - VREFN) x 2/3 0x3001 0x2003 0x2002 -8191 -8189 VREFP - VREFN 4 x 3 16384 (VREFP - VREFN) x 2/3 0x1FFF GRAY OUTPUT CODE (LSB) TWO'S COMPLEMENT OUTPUT CODE (LSB) MAX12553 14-Bit, 65Msps, 3.
PAGE 21
14-Bit, 65Msps, 3.3V ADC GRAY-TO-BINARY CODE CONVERSION 1) THE MOST SIGNIFICANT BINARY BIT IS THE SAME AS THE MOST SIGNIFICANT GRAY CODE BIT. 1) THE MOST SIGNIFICANT GRAY CODE BIT IS THE SAME AS THE MOST SIGNIFICANT BINARY BIT. D13 D11 D7 D3 0 1 1 0 1 1 0 1 0 0 1 1 0 0 D0 0 BIT POSITION BINARY D13 D11 D7 D3 0 1 0 1 1 0 1 1 1 0 1 0 1 0 GRAY CODE 0 WHERE IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH TABLE BELOW) AND X IS THE BIT POSITION.
PAGE 22
MAX12553 14-Bit, 65Msps, 3.3V ADC MAX4108 24.9Ω 0.1µF INP T1 N.C. 2 0.1µF 12pF 6 1 VIN VIN INP 5.6pF MAX12553 100Ω 5 24.9Ω MAX12553 COM COM 2.2µF 3 4 MINICIRCUITS TT1-6 OR T1-1T 2.2µF 100Ω 24.9Ω 24.9Ω INN INN 12pF 5.6pF Figure 12. Single-Ended, AC-Coupled Input Drive Figure 10. Transformer-Coupled Input Drive for Input Frequencies Up to Nyquist 0Ω* INP 0.1µF 6 1 VIN 75Ω 0.5% T1 N.C. 2 5 75Ω 0.5% 2 5 3 4 MINICIRCUITS ADT1-1WT 5.6pF 110Ω 0.1% T2 N.C.
PAGE 23
14-Bit, 65Msps, 3.3V ADC MAX12553 +3.3V 0.1µF 2.2µF 0.1µF +3.3V 1 2 VDD MAX6029EUK21 38 0.1µF 5 REFP REFOUT 0.1µF 1µF* 2.048V 0.1µF REFN 2 0.1µF +3.3V 39 16.2kΩ 1 10µF MAX12553 NOTE: ONE FRONT-END REFERENCE CIRCUIT IS CAPABLE OF SOURCING 15mA AND SINKING 30mA OF OUTPUT CURRENT. 1µF 1 5 MAX4230 4 3 3 REFIN GND COM 2.2µF 2.048V 47Ω +3.3V 2 10µF 6V 330µF 6V 0.1µF 2.2µF 0.1µF 1.47kΩ VDD 38 *PLACE THE 1µF REFP-to-REFN BYPASS CAPACITOR AS CLOSE TO THE DEVICE AS POSSIBLE.
PAGE 24
MAX12553 14-Bit, 65Msps, 3.3V ADC +3.3V 1 0.1µF MAX6029EUK30 2 +3.3V 5 0.1µF +3.3V 2.2µF 3.000V 0.1µF 0.1µF 1 20kΩ 1% 5 MAX4230 1 10µF 6V 330µF 6V 10µF 0.1µF 1.47kΩ +3.3V 0.1µF MAX12553 REFN 0.1µF 52.3kΩ 1% 1 52.3kΩ 1% 5 2 10µF 6V 20kΩ 1% COM REFIN GND 39 2.2µF +3.3V 330µF 6V 2.2µF 0.1µF 20kΩ 1% 20kΩ 1% 1.647V 47Ω 4 3 3 MAX4230 38 1µF* 2 0.47µF VDD REFP REFOUT 2 20kΩ 1% 47Ω 4 3 2.413V 0.1µF 1.47kΩ 0.1µF +3.3V 1 1 5 REFOUT MAX4230 4 3 38 0.
PAGE 25
14-Bit, 65Msps, 3.3V ADC Grounding, Bypassing, and Board Layout The MAX12553 requires high-speed board layout design techniques. Refer to the MAX12555 evaluation kit. data sheet for a board layout reference. Locate all bypass capacitors as close to the device as possible, preferably on the same side of the board as the ADC, using surface-mount devices for minimum inductance. Bypass VDD to GND with a 0.1µF ceramic capacitor in parallel with a 2.2µF ceramic capacitor. Bypass OVDD to GND with a 0.
PAGE 26
MAX12553 14-Bit, 65Msps, 3.3V ADC fundamental, the first six harmonics (HD2–HD7), and the DC offset. Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset. Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate.
PAGE 27
14-Bit, 65Msps, 3.3V ADC D1 D0 DAV OVDD GND VDD PD REFOUT 1 30 D2 2 29 D3 COM 3 28 D4 GND 4 27 D5 INP 5 26 D6 INN 6 25 D7 GND 7 24 D8 DCE 8 23 D9 CLKN 9 22 D10 CLKP 10 21 D11 MAX12553 EXPOSED PADDLE (GND) D12 D13 DOR OVDD GND VDD 11 12 13 14 15 16 17 18 19 20 VDD Overdrive recovery time is the time required for the ADC to recover from an input transient that exceeds the full-scale limits.
PAGE 28
Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) QFN THIN 6x6x0.8.EPS MAX12553 14-Bit, 65Msps, 3.3V ADC D2 D CL D/2 b D2/2 k E/2 E2/2 (NE-1) X e E CL E2 k e L (ND-1) X e e L CL CL L1 L L e A1 A2 e A PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm 21-0141 E 1 2 NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2.