User Manual

MAX1519/MAX1545
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
24 ______________________________________________________________________________________
LOWER SUSPEND CODES
SUS* S1 S0
OUTPUT
VOLTAGE
(V)
High GND GND 0.675
High GND REF 0.700
High GND OPEN 0.725
High GND V
CC
0.750
High REF GND 0.775
High REF REF 0.800
High REF OPEN 0.825
High REF V
CC
0.850
High OPEN GND 0.875
High OPEN REF 0.900
High OPEN OPEN 0.925
High OPEN V
CC
0.950
High V
CC
GND 0.975
High V
CC
REF 1.000
High V
CC
OPEN 1.025
High V
CC
V
CC
1.050
Table 5. Suspend Mode DAC Codes
*Connect the three-level SUS input to a 2.7V or greater supply (3.3V or V
CC
) for an input logic level high.
troller ramps down to the 0V DAC code setting, it forces
the DL_ low-side gate-driver high, and pulls the DH_
high-side gate-driver low. Toggle SHDN or cycle the
V
CC
power supply below 1V to clear the fault latch and
reactivate the controller after the junction temperature
cools by 15°C.
Thermal shutdown can be disabled through the “no-fault”
test mode (see the No-Fault Test Mode section).
No-Fault Test Mode
The latched-fault protection features and overlap mode
can complicate the process of debugging prototype
breadboards since there are (at most) a few milliseconds
in which to determine what went wrong. Therefore, a “no-
fault” test mode is provided to disable the fault protection
(overvoltage protection, undervoltage protection, and
thermal shutdown) and overlap mode. Additionally, the
test mode clears the fault latch if it has been set. The no-
fault test mode is entered by forcing 12V to 15V
on SHDN.
Multiphase Quick-PWM
5V Bias Supply (V
CC
and V
DD
)
The Quick-PWM controller requires an external 5V bias
supply in addition to the battery. Typically, this 5V bias
supply is the notebook’s 95%-efficient 5V system sup-
ply. Keeping the bias supply external to the IC
improves efficiency and eliminates the cost associated
with the 5V linear regulator that would otherwise be
needed to supply the PWM circuit and gate drivers. If
stand-alone capability is needed, the 5V bias supply
can be generated with an external linear regulator.
The 5V bias supply must provide V
CC
(PWM controller)
and V
DD
(gate-drive power), so the maximum current
drawn is:
I
BIAS
= I
CC
+ f
SW
(Q
G(LOW)
+ Q
G(HIGH)
)
where I
CC
is provided in the Electrical Characteristics,
f
SW
is the switching frequency, and Q
G(LOW)
and Q
G(HIGH)
are the MOSFET data sheet’s total gate-charge specifi-
cation limits at V
GS
= 5V. V+ and V
DD
can be tied
together if the input power source is a fixed 4.5V to 5.5V
supply. If the 5V bias supply is powered up prior to the
battery supply, the enable signal (SHDN going from low
to high) must be delayed until the battery voltage is pre-
sent to ensure startup.
Free-Running, Constant On-Time PWM
Controller with Input Feed Forward
The Quick-PWM control architecture is a pseudo-fixed-
frequency, constant-on-time, current-mode regulator
UPPER SUSPEND CODES
SUS* S1 S0
OUTPUT
VOLTAGE
(V)
REF GND GND 1.075
REF GND REF 1.100
REF GND OPEN 1.125
REF GND V
CC
1.150
REF REF GND 1.175
REF REF REF 1.200
REF REF OPEN 1.225
REF REF V
CC
1.250
REF OPEN GND 1.275
REF OPEN REF 1.300
REF OPEN OPEN 1.325
REF OPEN V
CC
1.350
REF V
CC
GND 1.375
REF V
CC
REF 1.400
REF V
CC
OPEN 1.425
REF V
CC
V
CC
1.450