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12-Channel/8-Channel, Flash-Configurable System

Managers with Nonvolatile Fault Registers

MAX16065/MAX16066

General Description

The MAX16065/MAX16066 flash-configurable system

managers monitor and sequence multiple system volt-

ages. The MAX16065/MAX16066 can also accurately

monitor (±2.5%) one current channel using a dedicated

high-side current-sense amplifier. The MAX16065 man-

ages up to twelve system voltages simultaneously, and

the MAX16066 manages up to eight supply voltages.

These devices integrate a selectable differential or sin-

gle-ended analog-to-digital converter (ADC) and con-

figurable outputs for sequencing power supplies. Device

configuration information, including overvoltage and

undervoltage limits, timing settings, and the sequenc-

ing order is stored in nonvolatile flash memory. During a

fault condition, fault flags and channel voltages can be

automatically stored in the nonvolatile flash memory for

later read-back.

The internal 1% accurate 10-bit ADC measures each

input and compares the result to one overvoltage, one

undervoltage, and one early warning limit that can be

configured as either undervoltage or overvoltage. A fault

signal asserts when a monitored voltage falls outside the

set limits. Up to three independent fault output signals

are configurable to assert under various fault conditions.

Because the MAX16065/MAX16066 support a power-

supply voltage of up to 14V, they can be powered

directly from the 12V intermediate bus in many systems.

The integrated sequencer provides precise control over

the power-up and power-down order of up to twelve

(MAX16065) or up to eight (MAX16066) power supplies.

Eight outputs (EN_OUT1–EN_OUT8) are configurable

with charge-pump outputs to directly drive external

n-channel MOSFETs.

The MAX16065/MAX16066 include eight/six programma-

ble general-purpose inputs/outputs (GPIO_s). GPIO_s

are flash configurable as dedicated fault outputs, as a

watchdog input or output, or as a manual reset.

The MAX16065/MAX16066 feature nonvolatile fault mem-

ory for recording information during system shutdown

events. The fault logger records a failure in the internal

flash and sets a lock bit protecting the stored fault data

from accidental erasure. An SMBus™ or a JTAG serial

interface configures the MAX16065/MAX16066. The

MAX16065 is available in a 48-pin, 7mm x 7mm, TQFN

package, and the MAX16066 is available in a 40-pin,

6mm x 6mm, TQFN package. Both devices are fully

specified from -40NC to +85NC.

Features

S Operate from 2.8V to 14V

S ±2.5% Current-Monitoring Accuracy

S 1% Accurate 10-Bit ADC Monitors 12/8 Voltage

Inputs

S Single-Ended or Differential ADC for System

Voltage/Current Monitoring

S Integrated High-Side Current-Sense Amplifier

S 12/8 Monitored Inputs with Overvoltage/

Undervoltage/Early Warning Limit

S Nonvolatile Fault Event Logger

S Power-Up and Power-Down Sequencing

Capability

S Independent Secondary Sequence Block

S 12/8 Outputs for Sequencing/Power-Good

Indicators

S Two Programmable Fault Outputs and One Reset

Output

S Eight General-Purpose Inputs/Outputs

Configurable as:

Dedicated Fault Outputs

Watchdog Timer Function

Manual Reset

Margin Enable

S SMBus (with Timeout) or JTAG Interface

S Flash Configurable Time Delays and Thresholds

S -40NC to +85NC Operating Temperature Range

Applications

Networking Equipment

Telecom Equipment (Base Stations, Access)

Storage/Raid Systems

Servers

19-4717; Rev 0; 7/09

Ordering Information

+Denotes a lead(Pb)-free/RoHS-compliant package.

*EP = Exposed pad.

SMBus is a trademark of Intel Corp.

Pin Configuration and Typical Operating Circuits appear at

end of data sheet.

PART TEMP RANGE PIN-PACKAGE

MAX16065ETM+

-40NC to +85NC

48 TQFN-EP*

MAX16066ETL+

-40NC to +85NC

40 TQFN-EP*

Summary of content (61 pages)

PAGE 1
9-4717; Rev 0; 7/09 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers The MAX16065/MAX16066 flash-configurable system managers monitor and sequence multiple system voltages. The MAX16065/MAX16066 can also accurately monitor (±2.5%) one current channel using a dedicated high-side current-sense amplifier. The MAX16065 manages up to twelve system voltages simultaneously, and the MAX16066 manages up to eight supply voltages.
PAGE 2
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers ABSOLUTE MAXIMUM RATINGS VCC, CSP, CSM to GND.........................................-0.3V to +15V CSP to CSM...........................................................-0.7V to +0.7V MON_, GPIO_, SCL, SDA, A0, RESET, EN_OUT9–EN_OUT12 to GND (programmed as open-drain outputs).........-0.3V to +6V EN, TCK, TMS, TDI to GND.....................................-0.3V to +4V DBP, ABP to GND....-0.
PAGE 3
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers (VCC = 2.8V to 14V, TA = -40NC to +85NC, unless otherwise specified. Typical values are at ABP = DBP = VCC = 3.3V, TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Bits LSB ADC DC ACCURACY Resolution Gain Error ADCGAIN Offset Error ADCOFF 10 0.35 0.
PAGE 4
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers ELECTRICAL CHARACTERISTICS (continued) (VCC = 2.8V to 14V, TA = -40NC to +85NC, unless otherwise specified. Typical values are at ABP = DBP = VCC = 3.3V, TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS OUTPUTS (EN_OUT_, RESET, GPIO_) ISINK = 2mA 0.4 ISINK = 10mA, GPIO_ only 0.7 VCC = 1.2V, ISINK = 100μA (RESET only) 0.
PAGE 5
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers (VCC = 2.8V to 14V, TA = -40NC to +85NC, unless otherwise specified. Typical values are at ABP = DBP = VCC = 3.3V, TA = +25NC.) (Note 1) PARAMETER SYMBOL Output Fall Time tOF Data Hold Time tHD:DAT Pulse Width of Spike Suppressed CONDITIONS MIN TYP CBUS = 10pF to 400pF From 50% SCL falling to SDA change 0.3 tSP MAX UNITS 250 ns 0.
PAGE 6
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers SDA tSU:DAT tHD:DAT tLOW tBUF tSU:STA tHD:STA tSU:STO SCL tHIGH tHD:STA tR tF START CONDITION STOP CONDITION REPEATED START CONDITION Figure 1. SMBus Timing Diagram t1 t2 t3 TCK t4 t5 TDI, TMS t6 t7 TDO Figure 2.
PAGE 7
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers VCC SUPPLY CURRENT vs. VCC SUPPLY VOLTAGE TA = -40NC ABP AND DBP REGULATORS ACTIVE 2 FOR LOW-VOLTAGE APPLICATIONS VCC < 3.6V CONNECT ABP AND DBP TO VCC 1 0 2 4 6 8 10 0.6 0.4 0.2 MAX16065 toc03 1.002 1.000 0.998 0.996 0.994 0.992 -40 14 -20 0 20 40 60 80 -40 -20 0 20 40 60 VCC (V) TEMPERATURE (NC) TEMPERATURE (NC) TRANSIENT DURATION vs.
PAGE 8
Typical Operating Characteristics (continued) (Typical values are at VCC = 3.3V, TA = +25°C, unless otherwise noted.) 0.8 0.6 0.8 0.6 0.4 3.0 0.2 0.2 GPIO_ EN_OUT_ 2.7 2.6 2.5 RESET 2.4 500 0 1000 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 1500 128 256 384 512 640 768 896 1024 IOUT (µA) 0 CURRENT-SENSE TRANSIENT DURATION vs. CSP-CSM OVERDRIVE MAX16065 toc14 1.0 MAX16065 toc13 1.03 200mV CODE (LSB) CURRENT-SENSE ACCURACY vs. CSP-CSM VOLTAGE 1.05 0.8 0.6 0.
PAGE 9
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers PIN NAME FUNCTION MAX16065 MAX16066 1–6, 43–46 1–5, 36–40 MON1– MON10 Monitor Voltage Inputs. Set monitor voltage range through configuration registers. Measured value written to ADC register can be read back through the SMBus or JTAG interface. 47, 48 — MON11, MON12 Monitor Voltage Inputs. Set monitor voltage range through configuration registers.
PAGE 10
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Functional Diagram ABP VCC DBP OVERC RESET MAX16065 RESET ANYFAULT FAULT1 DECODE LOGIC FAULT2 MR C O N T R O L MARGIN WATCHDOG TIMER EN WDI WDO GPIO1–GPIO8 PRIMARY SEQUENCE BLOCK 1.
PAGE 11
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers The MAX16065 manages up to twelve system power supplies and the MAX16066 can manage up to eight system power supplies. After boot-up, if EN is high and the software enable bit is set to ‘1,’ a power-up sequence begins based on the configuration stored in flash and the EN_OUT_s are controlled accordingly. When the power-up sequence is successfully completed, the monitoring phase begins.
PAGE 12
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 1.
PAGE 13
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers To initiate secondary sequencing and monitoring set the software enable r73h[1] bit to 1. Additionally, if GPIO_ is configured as EN2 then both the software enable 2 bit and EN2 must be high. To power-down and disable monitoring, either drive EN2 low or set the Software Enable2 bit to ‘0.’ See Table 2 for the software enable bit configurations.
PAGE 14
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 4. Power-Up/Power-Down Slot Delays CODE VALUE 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 25Fs 500Fs 1ms 2ms 3ms 4ms 6ms 8ms 10ms 12ms 1010 1011 25ms 100ms 1100 1101 200ms 400ms 1110 1111 800ms 1.6s sequence delay is then counted before moving to the next slot. Slot 0 does not monitor any MON_ input and does not control any EN_OUT_.
PAGE 15
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers SLOT 1 SLOT 2 (PRIMARY SEQUENCE) tFAULT SLOT1-SLOT2 DELAY EN_OUT1 FINAL SLOT SLOT1-SLOT2 DELAY OV BOTH ARE ASSIGNED TO SLOT 1 MON4 UV EN_OUT2 UV/OV MONITORING BEGINS WHEN MON4 REACHES UV THRESHOLD MON4 MUST REACH UV THRESHOLD BY THIS TIME BOTH ARE ASSIGNED TO SLOT 2 RESET TIMEOUT MON3 MON5 RESET EN Figure 3. Delay and Reset Timing Table 5.
PAGE 16
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 5. MON_ and EN_OUT_ Assignment Registers (continued) REGISTER ADDRESS FLASH ADDRESS 84h 284h 85h 86h 87h 88h 89h 285h 286h 287h 288h 289h BIT RANGE DESCRIPTION [3:0] EN_OUT1 [7:4] EN_OUT2 [3:0] EN_OUT3 [7:4] EN_OUT4 [3:0] EN_OUT5 [7:4] EN_OUT6 [3:0] EN_OUT7 [7:4] EN_OUT8 [3:0] EN_OUT9 [7:4] EN_OUT10 [3:0] EN_OUT11 [7:4] EN_OUT12 Table 6.
PAGE 17
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers CODE DELAY 0000 0001 0010 0011 0100 0101 0110 0111 1000 120Fs 150Fs 1001 6ms 1010 1011 1100 1101 1110 1111 10ms 15ms 25ms 40ms 60ms 100ms When the secondary sequence group is already powered down and EN or the Software Enable bit is set to ‘0’, the reverse power-down sequence is similar to above, but starts from the last slot assigned to the primary sequence r7Dh[7:4].
PAGE 18
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers are MON1/MON2, MON3/MON4, MON5/MON6, MON7/ MON8, MON9/MON10, MON11/MON12 with the first input always being at a higher voltage than the second. Use differential voltage sensing to eliminate voltage offsets or measure supply current. See Figure 4.
PAGE 19
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers REGISTER ADDRESS 47h FLASH ADDRESS BIT RANGE [0] 1 = Current sense is enabled 0 = Current sense is disabled [1] 1 = CSP full-scale range is 14V 0 = CSP full-scale range is 7V 247h 73h 273h DESCRIPTION [3:2] Overcurrent Primary Threshold and Current-Sense Gain Setting: 00 = 200mV threshold, AV = 6V/V 01 = 100mV threshold, AV = 12V/V 10 = 50mV threshold, AV = 24V/V 11 = 25mV threshold, AV = 48V/V [6:5] Over
PAGE 20
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 9. ADC Configuration Registers (continued) REGISTER ADDRESS 44h 45h FLASH ADDRESS BIT RANGE DESCRIPTION [1:0] ADC5 Full-Scale Range: 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = Channel not converted [3:2] ADC6 Full-Scale Range: 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = Channel not converted [5:4] ADC7 Full-Scale Range: 00 = 5.6V 01 = 2.8V 10 = 1.
PAGE 21
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers REGISTER ADDRESS 46h FLASH ADDRESS BIT RANGE DESCRIPTION [0] Differential Conversion ADC1–ADC2: 0 = Disabled 1 = Enabled [1] Differential Conversion ADC3–ADC4: 0 = Disabled 1 = Enabled [2] Differential Conversion ADC5–ADC6: 0 = Disabled 1 = Enabled [3] Differential Conversion ADC7–ADC8: 0 = Disabled 1 = Enabled [4] Differential Conversion ADC9–ADC10: 0 = Disabled 1 = Enabled [5] Differential Conversion
PAGE 22
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers When GPIO1–GPIO8 are configured as general-purpose inputs/outputs, read values from the GPIO_ ports through r1Eh and write values to GPIO_s through r3Eh. Note that r3Eh has a corresponding flash register, which programs the default state of a general-purpose output. See Table 11 for more information on reading and writing to the GPIO_.
PAGE 23
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers REGISTER ADDRESS FLASH ADDRESS 41h 241h BIT RANGE GPIO6 configuration (MSB) [4:2] GPIO7 configuration [7:5] GPIO8 configuration [1] [2] [3] 42h DESCRIPTION [1:0] [0] 242h [4] [5] [6] [7] MAX16065/MAX16066 Table 12.
PAGE 24
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers ANY_FAULT GPIO1, GPIO3, GPIO4, GPIO5, and GPIO7 are configurable to assert low during any fault condition. This includes power-up, power-down fault conditions as well as conditions where Fault1 or Fault2 assert. Second Enable (EN2) GPIO5 and GPIO7 are configurable as the enable input for the secondary sequence. See the Multiple Sequencing Groups section for more details. Table 14.
PAGE 25
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers REGISTER ADDRESS 39h 3Ah FLASH ADDRESS BIT RANGE [0] 1 = Fault2 depends on MON9 [1] 1 = Fault2 depends on MON10 [2] 1 = Fault2 depends on MON11 [3] 1 = Fault2 depends on MON12 [4] 1 = Fault2 depends on the overvoltage thresholds of the inputs selected by r38h and r39h[3:0] [5] 1 = Fault2 depends on the undervoltage thresholds of the inputs selected by r38h and r39h[3:0] [6] 1 = Fault2 depends on the ea
PAGE 26
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers External Fault (EXTFAULT) GPIO4 and GPIO8 are configurable as the external fault input/output. When configured as push-pull, EXTFAULT signals that a critical fault has occurred on one or more monitored voltages or current. When configured as open-drain, EXTFAULT can be asserted low by an external circuit to trigger a critical fault. This signal can be used to cascade multiple MAX16065/MAX16066s.
PAGE 27
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers REGISTER ADDRESS FLASH ADDRESS BIT RANGE 48h 248h [7:0] MON1 secondary threshold 49h 249h [7:0] MON1 overvoltage threshold 4Ah 24Ah [7:0] MON1 undervoltage threshold 4Bh 24Bh [7:0] MON2 secondary threshold 4Ch 24Ch [7:0] MON2 overvoltage threshold 4Dh 24Dh [7:0] MON2 undervoltage threshold 4Eh 24Eh [7:0] MON3 secondary threshold 4Fh 24Fh [7:0] MON3 overvoltage threshold 50h 250h [7:
PAGE 28
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 16.
PAGE 29
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers REGISTER ADDRESS BIT RANGE 1Ch 1Dh DESCRIPTION [0] MON9 [1] MON10 [2] MON11 [3] MON12 [4] Overcurrent [5] External fault (EXTFAULT) [6] SMB alert [4:0] Slot where failure occurred during secondary sequence [7:5] Reserved Table 18.
PAGE 30
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 18.
PAGE 31
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers FLASH ADDRESS BIT RANGE 202h DESCRIPTION [0] Fault log triggered on MON9 [1] Fault log triggered on MON10 [2] Fault log triggered on MON11 [3] Fault log triggered on MON12 [4] Fault log triggered on overcurrent [5] Fault log triggered on EXTFAULT [7:6] Not used 203h [7:0] MON1 ADC output bits 9–2 204h [7:0] MON2 ADC output bits 9–2 205h [7:0] MON3 ADC output bits 9–2 206h [7:0] MON4 ADC out
PAGE 32
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Set r74h[4:3] to a value other than ‘00’ to select autoretry mode (see Table 20). In this configuration, the device shuts down after a critical fault event then restarts following a configurable delay. Use r74h[2:0] to select an autoretry delay from 20ms to 1.6s. See Table 20 for more information on setting the autoretry delay.
PAGE 33
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers REGISTER ADDRESS 31h FLASH ADDRESS BIT RANGE [1:0] EN_OUT5 Configuration: 00 = Active-low, open drain 01 = Active-high, open drain 10 = Active-low, push-pull 11 = Active-high, push-pull [3:2] EN_OUT6 Configuration: 00 = Active-low, open drain 01 = Active-high, open drain 10 = Active-low, push-pull 11 = Active-high, push-pull [5:4] EN_OUT7 Configuration: 00 = Active-low, open drain 01 = Active-high, open drain
PAGE 34
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 21.
PAGE 35
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers REGISTER ADDRESS FLASH ADDRESS 1Fh BIT RANGE — 34h 234h DESCRIPTION [0] EN_OUT9 input state [1] EN_OUT10 input state [2] EN_OUT11 input state [3] EN_OUT12 input state [0] 1 = Assert EN_OUT9 [1] 1 = Assert EN_OUT10 [2] 1 = Assert EN_OUT11 [3] 1 = Assert EN_OUT12 MAX16065 fig06 MAX16065 fig07 VCC 2V/div UVLO VCC 2V/div 0V 0V RESET 2V/div 0V RESET 2V/div 0V EN_OUT_ 2V/div 0V 20ms/div ASSERTE
PAGE 36
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 23.
PAGE 37
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers The watchdog can be configured to control the RESET output as well as the WDO output. RESET asserts for the reset timeout, tRP, when the watchdog timer expires and the Watchdog Reset Output Enable bit (r76h[7]) is set to ‘1.’ When RESET is asserted, the watchdog timer is cleared and WDO is deasserted, therefore, WDO pulses low for a short time (approximately 1Fs) when the watchdog timer expires.
PAGE 38
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers VCC < tWDI WDI tWDI tRP < tWDI_STARTUP 0V VCC RESET 0V VCC WDO 0V 1µs Figure 10. Watchdog Startup Sequence with Watchdog Reset Enable Bit Set to ‘1’ Table 24.
PAGE 39
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers REGISTER ADDRESS 8Ch FLASH ADDRESS BIT RANGE DESCRIPTION 0 Configuration Register Lock: 1 = Locked 0 = Unlocked 1 Flash Fault Register Lock: 1 = Locked 0 = Unlocked 2 Flash Configuration Lock: 1 = Locked 0 = Unlocked 3 User Flash Lock: 1 = Locked 0 = Unlocked 28Ch Independent Watchdog Timer Operation When r73h[3] is ‘1’ the watchdog timer operates in independent mode.
PAGE 40
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers SDA SDA SCL SCL DATA LINE STABLE, CHANGE OF DATA ALLOWED DATA VALID S P START CONDITION STOP CONDITION Figure 11. Bit Transfer Figure 12. START and STOP Conditions over the bus is 8 bits long and is always followed by an acknowledge pulse. SCL is a logic input, while SDA is an open-drain input/output. SCL and SDA both require external pullup resistors to generate the logic-high voltage.
PAGE 41
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers REGISTER ADDRESS FLASH ADDRESS 8Bh 28Bh BIT RANGE DESCRIPTION [6:0] SMBus Slave Address Register. Set to 00h to use A0 pin address setting. [7] 1 = Enable PEC (packet error check). Table 27. Setting the SMBus Slave Address SLAVE ADDRESSES A0 SLAVE ADDRESS 0 1010 000R 1 1010 001R SCL 1010 010R SDA 1010 011R R = Read/Write select bit. Table 28.
PAGE 42
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers 5) The addressed slave asserts an ACK (or NACK) on SDA. Restrictions When Writing to Flash Flash must be written to 8 bytes at a time. The initial address must be aligned to 8-byte boundaries—the 3 LSBs of the initial address must be ‘000’. Write the 8 bytes using a single block-write command or using 8 successive Write Byte commands. 6) The master sends a STOP condition.
PAGE 43
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers 6) The master sends a REPEATED START condition. 7) The master sends the 7-bit slave address and a read bit (high). 2) The master sends the 7-bit slave address and a write bit (low). 8) The addressed slave asserts an ACK on SDA. 9) The slave sends an 8-bit data byte. 3) The addressed slave asserts an ACK on SDA. 10) The master asserts a NACK on SDA. 4) The master sends an 8-bit memory address.
PAGE 44
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers The block write procedure is the following: the configuration register or configuration flash or FFh in user flash, the address pointer stays at 8Fh or FFh, respectively. The block read procedure is the following: 1) The master sends a START condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA.
PAGE 45
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers JTAG Serial Interface The MAX16065/MAX16066 feature a JTAG port that complies with a subset of the IEEE 1149.1 specification. Either the SMBus or the JTAG interface can be used to access internal memory; however, only one interface is allowed to run at a time. The MAX16065/MAX16066 do not support IEEE 1149.1 boundary-scan functionality.
PAGE 46
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Send Byte Format S ADDRESS Receive Byte Format R/W ACK 7 bits 0 COMMAND ACK 8 bits 0 0 Slave Address: Address of the slave on the serial interface bus. S P ADDRESS Data Byte: Presets the internal address pointer or represents a command. ADDRESS 7 bits SLAVE ADDRESS 0 DATA NACK 8 bits 1 P Data Byte: Data is read from the location pointed to by the internal address pointer.
PAGE 47
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers 01100 01011 01010 01001 01000 00111 MEMORY WRITE REGISTER [LENGTH = 8 BITS] 00110 MEMORY READ REGISTER [LENGTH = 8 BITS] 00101 MEMORY ADDRESS REGISTER [LENGTH = 8 BITS] 00100 USER CODE REGISTER [LENGTH = 32 BITS] 00011 IDENTIFICATION REGISTER [LENGTH = 32 BITS] BYPASS REGISTER [LENGTH = 1 BIT] MUX 1 00000 11111 COMMAND DECODER 01001 SETFLSHADD 01010 RSTFLSHADD 01011 SETUSRFLSH 01100 RSTUSRFLSH 01000
PAGE 48
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers exit1-IR state. If TMS is low on the rising edge of TCK, the controller enters the shift-IR state. Shift-IR: In this state, the shift register in the instruction register connects between TDI and TDO and shifts data one stage for every rising edge of TCK toward the TDO serial output while TMS is low.
PAGE 49
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers TEST-LOGIC-RESET 0 RUN-TEST/IDLE MAX16065/MAX16066 1 0 1 SELECT-DR-SCAN 1 SELECT-IR-SCAN 0 1 0 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 1 1 1 1 EXIT1-IR 0 0 PAUSE-DR PAUSE-IR 0 1 0 1 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR 1 0 SHIFT-IR 0 EXIT1-DR 0 1 UPDATE-IR 1 0 0 Figure 16. Tap Controller State Diagram Table 30.
PAGE 50
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 32. 32-Bit User-Code Data MSB LSB Don’t Care 00000000000000000 SMBus slave id See Table 27 SAVE: This is an extension to the standard IEEE 1149.1 instruction set that triggers a fault log. The current ADC conversion results along with fault information are saved to flash depending on the configuration of the Critical Fault Log Control register (r6Dh).
PAGE 51
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers R6Dh[1:0] VALUE MAXIMUM WRITE TIME (ms) DESCRIPTION 00 Save flags and ADC readings 244 01 Save flags 77 10 Save ADC readings 153 11 Do not save anything VIN VOUT R MON_ EN_OUT_ — MAX16065 MAX16066 VIN VCC C MAX16065 MAX16066 GND Figure 17. Power Circuit for Shutdown During Fault Conditions required, tFAULT_SAVE.
PAGE 52
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Figure 19. Graphical User Interface Screenshot slot on different devices will not come up in the desired order even if the sequence delays are identical. U Consider using an external FP to control the EN inputs or the software enable bits of cascaded devices, monitoring the RESET outputs as a power-good signal.
PAGE 53
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Figure 20 shows how to connect a current-sense resistor to a pair of MON_ inputs for monitoring both current and voltage. For best accuracy, set the voltage range on the evennumbered MON_ to 1.4V. Since the ADC conversion results are 10 bits, the monitoring precision is 1.4/1024 = 1.4mV. For more accurate current measurements, use larger current-sense resistors.
PAGE 54
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Register Map FLASH ADDRESS REGISTER ADDRESS READ/ WRITE DESCRIPTION ADC VALUES, FAULT REGISTERS, GPIO_s AS INPUT PORTS—NOT IN FLASH — 000 R MON1 ADC output, MSBs — 001 R MON1 ADC output, LSBs — 002 R MON2 ADC output, MSBs — 003 R MON2 ADC output, LSBs — 004 R MON3 ADC output, MSBs — 005 R MON3 ADC output, LSBs — 006 R MON4 ADC output, MSBs — 007 R MON4 ADC output, L
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12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers FLASH ADDRESS REGISTER ADDRESS READ/ WRITE DESCRIPTION GPIO AND OUTPUT DEPENDENCIES/CONFIGURATIONS 230 030 R/W OUT configuration 231 031 R/W OUT configuration 232 032 R/W OUT configuration 233 033 R/W Charge-pump configuration, bits 234 034 R/W EN_OUT_ as GPIO data out 235 035 R/W SMBALERT pin configuration 236 036 R/W Fault1 dependencies 237 037 R/W Fault1 dependencies 238 038 R/W
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MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Register Map (continued) FLASH ADDRESS REGISTER ADDRESS READ/ WRITE 254 054 R/W MON5 secondary selectable UV/OV 255 055 R/W MON5 primary OV 256 056 R/W MON5 primary UV 257 057 R/W MON6 secondary selectable UV/OV 258 058 R/W MON6 primary OV 259 059 R/W MON6 primary UV 25A 05A R/W MON7 secondary selectable UV/OV DESCRIPTION 25B 05B R/W MON7 primary OV 25C 05C R/W
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12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers FLASH ADDRESS REGISTER ADDRESS READ/ WRITE 278 078 R/W Sequence delay for Slot 2 and Slot 3 279 079 R/W Sequence delay for Slot 4 and Slot 5 27A 07A R/W Sequence delay for Slot 6 and Slot 7 27B 07B R/W Sequence delay for Slot 8 and Slot 9 27C 07C R/W Sequence delay for Slot 10 and Slot 11 27D 07D R/W Primary sequence final slot, sequence delay for Slot 12 27E 07E R/W MON1/MON2 slot assignm
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MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Register Map (continued) USER FLASH 300 39F R/W User flash 3A0 3AF — Reserved 3B0 3FF R/W User flash Typical Operating Circuits VSUPPLY +3.
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12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers VSUPPLY +3.
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GPIO6 EN_OUT12 EN_OUT11 EN_OUT10 EN_OUT9 EN_OUT8 EN_OUT7 EN_OUT6 EN_OUT5 EN_OUT4 TOP VIEW EN_OUT3 EN_OUT2 Pin Configurations 36 35 34 33 32 31 30 29 28 27 26 25 EN_OUT1 37 24 GPIO5 EN 38 23 GPIO4 DBP 39 22 GPIO3 VCC 40 21 GPIO2 ABP 41 20 GPIO1 GND 42 19 GPIO8 MON7 43 18 GPIO7 MON8 44 17 GND MON9 45 16 SCL MON10 46 15 AO 14 SDA 13 TDO 9 10 11 12 TDI 8 TCK 7 TMS 6 RESET MON4 5 CSM 4 CSP 3 MON6 2 MON5 1 MON3 48 MON2 47 MON12 *EP
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12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers PROCESS: BiCMOS Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 48 TQFN-EP* T4877-6 21-0144 40 TQFN-EP* T4066-5 21-0141 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.