User guide

MAX1800
Digital Camera Step-Up
Power Supply
16 ______________________________________________________________________________________
To determine the compensation components:
1) Find the frequency of the right-half-plane zero:
where V
POUT
is the output voltage, I
LOAD(MAX)
is the
maximum load current, L is the inductor value, and
D
M
is the duty-cycle under maximum load,
specifically:
where I
LIM
is the average inductor current under
maximum load, ESR
L
is the equivalent series resis-
tance of the inductor, R
PCH
and R
NCH
are the on-
state drain-source resistance of the P-channel switch
(200mΩ typ) and N-channel switch (100mΩ typ),
respectively.
2) Specify the control-loop crossover frequency (the
frequency at which the loop gain drops to unity) at
one-fifth the frequency of the right-half-plane zero:
f
CROSS
= f
RHPZ
/ 5
3) Find the DC open-loop voltage gain:
where V
REF
is the 1.25V reference voltage, A
VCOMP
is the DC voltage gain of the internal error amplifier
(2000), A
VCS
is the transresistance gain of the
internal current-sense amplifier (0.375), and D
M
is
the maximum duty cycle determined in step 1 above.
With these parameter values, the open-loop voltage
gain is:
4) Set the dominant pole so that the loop crossover
occurs at the frequency specified in step 2 above:
where G
M
is the transconductance of the error ampli-
fier (typically 100µS), and C
C
is the compensation
capacitor. Subject to this condition, the compensa-
tion capacitor is:
5) Determine the pole due to the output capacitor
(f
OUT
), and set the compensation zero (f
COMPZ
) at
the same frequency. The pole occurs at:
where C
OUT
is the total output capacitance at POUT,
and the zero occurs at:
Thus, setting f
OUT
to f
COMZ
:
The compensation resistor R
C
(positioned in series
with the compensation capacitor) is:
6) Find the frequency of the zero (f
ESRZ
) due to the out-
put capacitance equivalent series resistance (ESR),
and set the POUT-to-OUT RC filter pole (f
FILTER
) at
the same frequency. The zero occurs at:
and the pole occurs at:
where R
F
and C
F
are the filter resistor and capacitor,
respectively. Thus:
C
OUT
ESR = R
F
C
F
To ensure that noise is reduced at OUT, choose CF ≥
1µF. Then determine RF:
R
C ESR
C
F
OUT
F
=
f
RC
FILTER
FF
=
1
2π
f
C ESR
ESRZ
OUT
=
1
2π
R
CV
CI
C
OUT POUT
C LOAD MAX
=
()
I
CV RC
LOAD MAX
OUT POUT C C
()
=
1
f
RC
COMPZ
CC
=
1
2π
f
I
CV
OUT
LOAD MAX
OUT POUT
=
()
2π
C
xA
f
C
VLOOP
CROSS
=
−
50 10
2
9
π
f
f
A
G
AC
DOM
CROSS
VLOOP
M
VCOMP C
==
()2π
A
D
I
VLOOP
M
LOAD
=
−6666 1 ( )
A
VDA
AI
VLOOP
REF M VCOMP
VCS LOAD
=
−( )1
D
V V I R ESR
VIRR
M
POUT IN LIM PCH L
POUT LIM PCH NCH
=
−+ +
()
[]
++
()
f
VD
IL
RHPZ
POUT M
LOAD MAX
=
−( )
()
1
2
2
π