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_______________General Description

The MAX186/MAX188 are 12-bit data-acquisition sys-

tems that combine an 8-channel multiplexer, high-band-

width track/hold, and serial interface together with high

conversion speed and ultra-low power consumption.

The devices operate with a single +5V supply or dual

±5V supplies. The analog inputs are software config-

urable for unipolar/bipolar and single-ended/differential

operation.

The 4-wire serial interface directly connects to SPI™,

QSPI™ and Microwire™ devices without external logic. A

serial strobe output allows direct connection to TMS320

family digital signal processors. The MAX186/MAX188

use either the internal clock or an external serial-interface

clock to perform successive-approximation A/D conver-

sions. The serial interface can operate beyond 4MHz

when the internal clock is used.

The MAX186 has an internal 4.096V reference while the

MAX188 requires an external reference. Both parts

have a reference-buffer amplifier that simplifies gain

trim .

The MAX186/MAX188 provide a hard-wired SHDN pin

and two software-selectable power-down modes.

Accessing the serial interface automatically powers up

the devices, and the quick turn-on time allows the

MAX186/MAX188 to be shut down between every

conversion. Using this technique of powering down

between conversions, supply current can be cut to

under 10µA at reduced sampling rates.

The MAX186/MAX188 are available in 20-pin DIP and

SO packages, and in a shrink small-outline package

(SSOP), that occupies 30% less area than an 8-pin DIP.

For applications that call for a parallel interface, see the

MAX180/MAX181 data sheet. For anti-aliasing filters,

consult the MAX274/MAX275 data sheet.

________________________Applications

Portable Data Logging

Data-Acquisition

High-Accuracy Process Control

Automatic Testing

Robotics

Battery-Powered Instruments

Medical Instruments

____________________________Features

♦ 8-Channel Single-Ended or 4-Channel

Differential Inputs

♦ Single +5V or ±5V Operation

♦ Low Power: 1.5mA (operating mode)

2µA (power-down mode)

♦ Internal Track/Hold, 133kHz Sampling Rate

♦ Internal 4.096V Reference (MAX186)

♦ SPI-, QSPI-, Microwire-, TMS320-Compatible

4-Wire Serial Interface

♦ Software-Configurable Unipolar or Bipolar Inputs

♦ 20-Pin DIP, SO, SSOP Packages

♦ Evaluation Kit Available

______________Ordering Information

Ordering Information continued on last page.

†

NOTE: Parts are offered in grades A, B, C and D (grades defined

in Electrical Characteristics). When ordering, please specify grade.

Contact factory for availability of A-grade in SSOP package.

* Dice are specified at +25°C, DC parameters only.

* * Contact factory for availability and processing to MIL-STD-883.

TEMP. RANGE

MAX186/MAX188

Low-Power, 8-Channel,

Serial 12-Bit ADCs

________________________________________________________________ Maxim Integrated Products

PART

†

PIN-PACKAGE

MAX186_CPP 20 Plastic DIP

MAX186_CWP 20 SO

20 SSOP

MAX186DC/D Dice*

MAX186_EPP 20 Plastic DIP

MAX186_CAP

TOP VIEW

DIP/SO/SSOP



SCLK

DIN

SSTRB

DOUT

DGND

AGND

REFADJ

VREFSHDN

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

MAX186

MAX188

____________________Pin Configuration

0°C to +70°C

MAX186_EWP 20 SO

MAX186_EAP -40°C to +85°C 20 SSOP

MAX186_MJP -55°C to +125°C 20 CERDIP**

SPI and QSPI are registered trademarks of Motorola.

Microwire is a registered trademark of National Semiconductor.

-40°C to +85°C

19-0123; Rev. 4; 8/96

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800

EVALUATION KIT

AVAILABLE

Summary of content (24 pages)

PAGE 1
9-0123; Rev. 4; 8/96 KIT ATION EVALU E L B A AVAIL Low-Power, 8-Channel, Serial 12-Bit ADCs ____________________________Features The MAX186/MAX188 are 12-bit data-acquisition systems that combine an 8-channel multiplexer, high-bandwidth track/hold, and serial interface together with high conversion speed and ultra-low power consumption. The devices operate with a single +5V supply or dual ±5V supplies.
PAGE 2
MAX186/MAX188 Low-Power, 8-Channel, Serial 12-Bit ADCs ABSOLUTE MAXIMUM RATINGS VDD to AGND............................................................-0.3V to +6V VSS to AGND ............................................................+0.3V to -6V VDD to VSS ..............................................................-0.3V to +12V AGND to DGND.....................................................-0.3V to +0.3V CH0–CH7 to AGND, DGND .............(VSS - 0.3V) to (VDD + 0.3V) CH0–CH7 Total Input Current ...
PAGE 3
Low-Power, 8-Channel, Serial 12-Bit ADCs (VDD = 5V ±5%; VSS = 0V or -5V; fCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186— 4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL Small-Signal Bandwidth CONDITIONS MIN -3dB rolloff Full-Power Bandwidth TYP MAX UNITS 4.
PAGE 4
MAX186/MAX188 Low-Power, 8-Channel, Serial 12-Bit ADCs ELECTRICAL CHARACTERISTICS (continued) (VDD = 5V ±5%; VSS = 0V or -5V; fCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186— 4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; TA = TMIN to TMAX, unless otherwise noted.
PAGE 5
Low-Power, 8-Channel, Serial 12-Bit ADCs (VDD = 5V ±5%; VSS = 0V or -5V; fCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186— 4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS Positive Supply Rejection (Note 8) PSR Negative Supply Rejection (Note 8) PSR MIN TYP MAX UNITS VDD = 5V ±5%; external reference, 4.096V; full-scale input ±0.06 ±0.
PAGE 6
__________________________________________Typical Operating Characteristics POWER-SUPPLY REJECTION vs. TEMPERATURE INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE CHANNEL-TO-CHANNEL OFFSET MATCHING vs. TEMPERATURE 0.30 0.16 VDD = +5V ±5% 0.25 2.456 0.14 OFFSET MATCHING (LSBs) VSS = 0V or -5V 0.20 2.455 VREFADJ (V) PSR (LSBs) 0.15 0.10 2.454 2.453 0.05 0.00 -0.05 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 0.12 0.10 0.08 0.06 0.04 0.02 2.
PAGE 7
Low-Power, 8-Channel, Serial 12-Bit ADCs PIN NAME FUNCTION 12 REFADJ 13 AGND Analog Ground. Also IN- Input for single-ended conversions. 14 DGND Digital Ground 15 DOUT Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CS is high. 16 SSTRB Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX186/MAX188 begin the A/D conversion and goes high when the conversion is done.
PAGE 8
MAX186/MAX188 Low-Power, 8-Channel, Serial 12-Bit ADCs _______________Detailed Description The MAX186/MAX188 use a successive-approximation conversion technique and input track/hold (T/H) circuitry to convert an analog signal to a 12-bit digital output. A flexible serial interface provides easy interface to microprocessors. No external hold capacitors are required. Figure 3 shows the block diagram for the MAX186/MAX188.
PAGE 9
Low-Power, 8-Channel, Serial 12-Bit ADCs MAX186/MAX188 VDD +5V OSCILLOSCOPE 0.1µF DGND AGND 0V TO 4.096V ANALOG 0.01µF INPUT CH7 SCLK VSS MAX186 MAX188 SSTRB CS DOUT* SCLK +5V DIN +5V CH1 CH2 CH3 CH4 DOUT D1 1N4148 SSTRB REFADJ C2 0.01µF 2MHz OSCILLATOR SHDN VREF N.C. C1 4.7µF +2.5V +2.5V REFERENCE ** * FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX) **REQUIRED FOR MAX188 ONLY. A POTENTIOMETER MAY BE USED IN PLACE OF THE REFERENCE FOR TEST PURPOSES. Figure 5.
PAGE 10
MAX186/MAX188 Low-Power, 8-Channel, Serial 12-Bit ADCs single-ended unipolar conversions on CH7 in external clock mode without powering down between conversions. In external clock mode, the SSTRB output pulses high for one clock period before the most significant bit of the 12-bit conversion result comes out of DOUT. Varying the analog input to CH7 should alter the sequence of bits from DOUT. A total of 15 clock cycles is required per conversion.
PAGE 11
Low-Power, 8-Channel, Serial 12-Bit ADCs SEL2 SEL1 SEL0 CH0 0 0 0 + 1 0 0 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 1 1 1 CH1 CH2 CH3 CH4 CH5 CH6 CH7 AGND – + – + – + – + – + – + – + – Table 4.
PAGE 12
MAX186/MAX188 Low-Power, 8-Channel, Serial 12-Bit ADCs CS tACQ SCLK 1 4 8 12 16 20 24 SCL/ START SEL2 SEL1 SEL0 UNI/ BIP DIFF PD1 PD0 DIN RB3 RB2 SSTRB RB1 B11 MSB B10 DOUT ACQUISITION IDLE A/D STATE B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 LSB FILLED WITH ZEROS CONVERSION IDLE 1.5µs (CLK = 2MHz) Figure 6. 24-Bit External Clock Mode Conversion Timing (SPI, QSPI and Microwire Compatible) ••• CS tCSH tCSS tCL tCH SCLK tCSH ••• tDS tDH ••• DIN tDV tDO tTR ••• DOUT Figure 7.
PAGE 13
Low-Power, 8-Channel, Serial 12-Bit ADCs ••• tSTR tSDV SSTRB ••• ••• tSSTRB SCLK MAX186/MAX188 ••• CS tSSTRB •• • • •••• PD0 CLOCKED IN Figure 8. External Clock Mode SSTRB Detailed Timing CS SCLK DIN 1 2 3 4 5 6 7 8 9 10 11 12 18 19 20 21 22 23 24 SCL/ START SEL2 SEL1 SEL0 UNI/ DIP DIFF PD1 PD0 SSTRB tCONV B11 MSB B10 DOUT A/D STATE IDLE CONVERSION 10µs MAX 1.5µs (CLK = 2MHz) ACQUISITION B9 B2 B1 B0 LSB FILLED WITH ZEROS IDLE Figure 9.
PAGE 14
MAX186/MAX188 Low-Power, 8-Channel, Serial 12-Bit ADCs CS • • • tCONV tCSS tSCK tCSH SSTRB • • • tSSTRB SCLK • • • PD0 CLOCK IN NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION. Figure 10. Internal Clock Mode SSTRB Detailed Timing Data Framing The falling edge of CS does not start a conversion on the MAX186/MAX188. The first logic high clocked into DIN is interpreted as a start bit and defines the first bit of the control byte.
PAGE 15
Low-Power, 8-Channel, Serial 12-Bit ADCs 1 8 1 8 1 SCLK S DIN CONTROL BYTE 0 S B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 DOUT S CONTROL BYTE 1 CONTROL BYTE 2 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 CONVERSION RESULT 1 CONVERSION RESULT 0 SSTRB Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing CS ••• SCLK ••• DIN DOUT S S CONTROL BYTE 0 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 CONVERSION RESULT 0 ••• CONTROL BYTE 1 B11 B10 B9 B8 ••• CONVERSION RESULT 1 Figure 11b.
PAGE 16
MAX186/MAX188 Low-Power, 8-Channel, Serial 12-Bit ADCs CLOCK MODE INTERNAL EXTERNAL EXTERNAL SHDN SETS FAST POWER-DOWN MODE SETS EXTERNAL CLOCK MODE DIN S X X X X X 1 1 SETS EXTERNAL CLOCK MODE SX X XX X 0 1 DOUT DATA VALID (12 DATA BITS) MODE POWERED UP S XX XXX 1 1 DATA VALID (12 DATA BITS) VALID DATA INVALID FAST POWER-DOWN POWERED UP FULL POWER DOWN POWERED UP Figure 12a. Timing Diagram Power-Down Modes, External Clock Table 5.
PAGE 17
Low-Power, 8-Channel, Serial 12-Bit ADCs MAX186/MAX188 CLOCK MODE INTERNAL CLOCK MODE SETS FULL POWER-DOWN SETS INTERNAL CLOCK MODE DIN S X X X X X 1 0 SX X XX X 0 0 DOUT S DATA VALID DATA VALID CONVERSION SSTRB CONVERSION FULL POWER-DOWN POWERED UP MODE POWERED UP Figure 12b. Timing Diagram Power-Down Modes, Internal Clock Hardware Power-Down The SHDN pin places the converter into the full power-down mode. Unlike with the software shut-down modes, conversion is not completed.
PAGE 18
MAX186/MAX188 Low-Power, 8-Channel, Serial 12-Bit ADCs MAX186/MAX188 FAST POWER-DOWN 2ms FASTPD WAIT 400kHz EXTERNAL CLOCK INTERNAL COMPENSATION 8 CHANNELS 100 1 CHANNEL 10 1 10,000 AVG. SUPPLY CURRENT (µA) AVG. SUPPLY CURRENT (µA) 1000 MAX186-14A MAX186 FULL POWER-DOWN 8 CHANNELS 1000 1 CHANNEL 100 2MHz EXTERNAL CLOCK EXTERNAL COMPENSATION 50µs WAIT 10 0 50 100 150 200 250 300 350 400 450 500 0 CONVERSIONS PER CHANNEL PER SECOND Figure 14a. MAX186 Supply Current vs.
PAGE 19
Low-Power, 8-Channel, Serial 12-Bit ADCs MAX186/MAX188 OUTPUT CODE FULL-SCALE TRANSITION 11 . . . 111 011 . . . 111 11 . . . 110 011 . . . 110 FS = +4.096 2 1LSB = +4.096 4096 11 . . . 101 000 . . . 010 000 . . . 001 FS = +4.096V 1LSB = FS 4096 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101 00 . . . 011 00 . . . 010 100 . . . 001 00 . . . 001 100 . . . 000 00 . . . 000 0 1 2 3 FS 0V -FS +FS - 1LSB INPUT VOLTAGE (LSBs) INPUT VOLTAGE (LSBs) FS - 3/2LSB Figure 15.
PAGE 20
Low-Power, 8-Channel, Serial 12-Bit ADCs MAX186/MAX188 High-Speed Digital Interfacing with QSPI The MAX186/MAX188 can interface with QSPI at high throughput rates using the circuit in Figure 19. This QSPI circuit can be programmed to do a conversion on each of the eight channels. The result is stored in memory without taxing the CPU since QSPI incorporates its own micro-sequencer.
PAGE 21
Low-Power, 8-Channel, Serial 12-Bit ADCs INITQSPI: ;This routine sets up the QSPI microsequencer to operate on its own. ;The sequencer will read all eight channels of a MAX186/MAX188 each time ;it is triggered. The A/D converter results will be left in the ;receive data RAM. Each 16 bit receive data RAM location will ;have a leading zero, 12 bits of conversion result and three zeros.
PAGE 22
MAX186/MAX188 Low-Power, 8-Channel, Serial 12-Bit ADCs ;set delay between transfers LDD #$0800 STD SPCR2 ;set ENDQP to $8 for 9 transfers ***** Initialize QSPI Command RAM ***** LDAA #$80 ;CONT=1,BITSE=0,DT=0,DSCK=0,PCS0=ACTIVE STAA $FD40 ;store first byte in COMMAND RAM LDAA #$C0 ;CONT=1,BITSE=1,DT=0,DSCK=0,PCS0=ACTIVE STAA $FD41 STAA $FD42 STAA $FD43 STAA $FD44 STAA $FD45 STAA $FD46 STAA $FD47 LDAA #$40 ;CONT=0,BITSE=1,DT=0,DSCK=0,PCS0=ACTIVE STAA $FD48 ***** Initialize QSPI Transmit RAM ***** LDD #$008
PAGE 23
Low-Power, 8-Channel, Serial 12-Bit ADCs MAX186/MAX188 CS •••• •••• SCLK •••• SSTRB DIN •••• Figure 21. QSPI Assembly-Code Timing TMS320C3x to MAX186 Interface Figure 22 shows an application circuit to interface the MAX186/MAX188 to the TMS320 in external clock mode. The timing diagram for this interface circuit is shown in Figure 23.
PAGE 24
MAX186/MAX188 Low-Power, 8-Channel, Serial 12-Bit ADCs CS SCLK DIN START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0 HIGH IMPEDANCE SSTRB DOUT MSB B10 B1 HIGH IMPEDANCE LSB Figure 23. TMS320 Serial Interface Timing Diagram __________Typical Operating Circuit ___________________Chip Topography CH1 CH0 VDD +5V VDD VDD CH0 0V to 4.096V ANALOG INPUTS DGND CH7 MAX186 C1 4.7µF C2 0.01µF DIN C4 0.