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MAX3107

SPI/I

C UART with 128-Word FIFOs

and Internal Oscillator

19-5014; Rev 0; 10/09

+Denotes a lead(Pb)-free/RoHS-compliant package.

*EP = Exposed pad.

Functional Diagram appears at end of data sheet.

General Description

The MAX3107 is an advanced universal asynchronous

receiver-transmitter (UART) with 128 words each of

receive and transmit first-in/first-out (FIFO) that can be

controlled through I

C or high-speed SPI™. An internal

oscillator reduces the need for an external crystal or

clock source. The 2x and 4x rate modes allow a maxi-

mum of 24Mbps data rates. A phase-locked loop (PLL),

prescaler, and fractional baud-rate generator allow for

high-resolution baud-rate programming and minimize

the dependency of baud rate on reference clock fre-

quency.

Autosleep and shutdown modes help reduce power

consumption during periods of inactivity. A low 640µA

(typ) supply current and tiny 24-pin TQFN (3.5mm x

3.5mm) package make the MAX3107 ideal for low-power

portable devices.

Integrated logic-level translation on the controller and

transceiver (RX/TX and RTS/CTS) interfaces enable use

with a wide selection of RS-232/RS-485 transceivers.

Automatic hardware and software flow control with

selectable FIFO interrupt triggering offloads low-level

activity from the host controller. Automatic half-duplex

transceiver control with programmable setup and hold

times allow the MAX3107 to be used in high-speed appli-

cations, for example Profibus-DP.

The MAX3107 is ideal for use in portable devices,

industrial applications, and automotive applications. The

MAX3107 is available in a 24-pin SSOP package and a

24-pin TQFN package. It is specified over the -40NC to

+85NC extended ambient temperature range.

Applications

Portable Devices

Industrial Control Systems

Fieldbus Networks

Automotive Infotainment Systems

Medical Systems

Point-of-Sale Systems

HVAC or Building Control

Features

S Tiny 24-Pin, Lead-Free TQFN (3.5mm x 3.5mm)

and 24-Pin, Lead-Free SSOP Packages

S Integrated Internal Oscillator

S 24Mbps (max) Data Rate

S Integrated PLL and Divider

S Fractional Baud-Rate Generator

S SPI Up to 26MHz Clock Rate

S Autotransceiver Direction Control

S Half-Duplex Echo Suppression

S Automatic RTS/CTS and XON/XOFF Flow Control

S Special Character Detection

S GPIO-Based Character Detection

S 9-Bit Multidrop-Mode Data Filtering

S SIR- and MIR-Compliant IrDA Encoder/Decoder

S +2.35V to +3.6V Supply Range

S Logic-Level Translation on the Controller and

Transceiver Interfaces (Down to 1.7V)

S Four Flexible GPIOs

S Line Noise Indication

S Shutdown and Autosleep Modes

S Low 640µA (typ) Supply Current at 1Mbaud and

20MHz Clock

S Low 20µA (typ) Shutdown Power

Ordering Information

SPI is a trademark of Motorola, Inc.

PART TEMP RANGE PIN-PACKAGE

MAX3107EAG+

-40NC to +85NC

24 SSOP

MAX3107ETG+

-40NC to +85NC

24 TQFN-EP*

Summary of content (51 pages)

PAGE 1
9-5014; Rev 0; 10/09 SPI/I2C UART with 128-Word FIFOs and Internal Oscillator Features The MAX3107 is an advanced universal asynchronous receiver-transmitter (UART) with 128 words each of receive and transmit first-in/first-out (FIFO) that can be controlled through I2C or high-speed SPI™. An internal oscillator reduces the need for an external crystal or clock source. The 2x and 4x rate modes allow a maximum of 24Mbps data rates.
PAGE 2
MAX3107 SPI/I2C UART with 128-Word FIFOs and Internal Oscillator TABLE OF CONTENTS Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
SPI/I2C UART with 128-Word FIFOs and Internal Oscillator Power-Up and IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Interrupt Enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
MAX3107 SPI/I2C UART with 128-Word FIFOs and Internal Oscillator LIST OF FIGURES Figure 1. I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 2. SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 3. Transmit FIFO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 5
SPI/I2C UART with 128-Word FIFOs and Internal Oscillator RHR—Receiver Hold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 THR—Transmit Hold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 IRQEn—IRQ Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 6
MAX3107 SPI/I2C UART with 128-Word FIFOs and Internal Oscillator ABSOLUTE MAXIMUM RATINGS (Voltages referenced to AGND.) VL, VA, VEXT, XIN................................................. -0.3V to +4.0V V18, XOUT................................................... -0.3V to (VA + 0.3V) RST, IRQ, DIN/A1, CS/A0, SCLK/SCL, DOUT/SDA, LDOEN, I2C/SPI................... -0.3V to (VL + 0.3V) TX, RX, RTS/CLKOUT, CTS, GPIO_........ -0.3V to (VEXT + 0.3V) DGND............................................................
PAGE 7
SPI/I2C UART with 128-Word FIFOs and Internal Oscillator (VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, VEXT = +1.71V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VA = +2.8V, VL = +1.8V, VEXT = +2.5V, TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ILOAD = -3mA, VL > 2V 0.4 V ILOAD = -3mA, VL < 2V 0.2 x VL V SCLK/SCL, DOUT/SDA DOUT/SDA Output Low Voltage in I2C Mode VOL,I2C DOUT/SDA Output Low Voltage in SPI Mode VOL,SPI ILOAD = -2mA 0.
PAGE 8
MAX3107 SPI/I2C UART with 128-Word FIFOs and Internal Oscillator DC ELECTRICAL CHARACTERISTICS (continued) (VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, VEXT = +1.71V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VA = +2.8V, VL = +1.8V, VEXT = +2.5V, TA = +25NC.
PAGE 9
SPI/I2C UART with 128-Word FIFOs and Internal Oscillator (VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, VEXT = +1.71V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VA = +2.8V, VL = +1.8V, VEXT = +2.5V, TA = +25NC.
PAGE 10
MAX3107 SPI/I2C UART with 128-Word FIFOs and Internal Oscillator Test Circuits/Timing Diagrams START CONDITION (S) REPEATED START CONDITION (Sr) tR STOP CONDITION (P) tF SDA tBUF tHD:DAT tHD:STA tHD:STA tSU:DAT tSU:STO tSU:STA SCL tHIGH tR tF START CONDITION (S) tLOW Figure 1. I2C Timing Diagram CS tCSH tCSS tCL tCH tCSH SCLK tDS tDH DIN tDO DOUT Figure 2.
PAGE 11
SPI/I2C UART with 128-Word FIFOs and Internal Oscillator (VA = 2.5V, VL = 2.5V, VEXT = 2.5V, LDOEN = VL, TA = +25NC, unless otherwise noted.) LDOEN = VL 3.7 3.0 LDOEN = AGND 1.8V APPLIED TO V18 2.8 2.6 LDOEN = AGND 1.8V APPLIED TO V18 2.2 2.85 3.10 3.35 3.60 2.35 2.60 2.85 VA (V) LDOEN = AGND 1.8V APPLIED TO V18 VA = 3.3V 120 80 60 VA = 2.5V 40 0.950 3.686MHz EXT. CRYSTAL BAUD RATE = 115kbps 6x PLL MULT.FACTOR 2.35 2.60 2.85 2.85 3.10 3.35 20 EXTERNAL 3.
PAGE 12
SPI/I2C UART with 128-Word FIFOs and Internal Oscillator GPIO3 GPIO2 GPIO1 18 RTS/CLKOUT RX TOP VIEW CTS MAX3107 Pin Configurations 17 16 15 14 13 TX 19 12 GPIO0 VEXT 20 11 DGND XOUT 21 10 VL MAX3107 XIN 22 AGND 23 *EP + 5 6 CS/A0 4 SCLK/SCL 3 DOUT/SDA I2C/SPI 2 V18 1 LDOEN VA 24 TQFN (3.5mm × 3.
PAGE 13
SPI/I2C UART with 128-Word FIFOs and Internal Oscillator PIN NAME FUNCTION 10 DIN/A1 Serial-Data and Address 1 Input. When I2C/SPI is high, DIN/A1 functions as the DIN SPI serial-data input. When I2C/SPI is low, DIN/A1 functions as the A1 I2C device address programming input and connects to DIN/A1 DGND or VL. 8 11 IRQ Active-Low Interrupt Open-Drain Output. IRQ is asserted when an interrupt is pending. 9 12 RST Active-Low Reset Input. Drive RST low to force the UART into hardware reset mode.
PAGE 14
MAX3107 SPI/I2C UART with 128-Word FIFOs and Internal Oscillator Register Map (All default reset values are 0x00, unless otherwise noted. All registers are R/W, unless otherwise noted.
PAGE 15
SPI/I2C UART with 128-Word FIFOs and Internal Oscillator The MAX3107 UART is a bridge between an SPI/ MICROWIRE™ or I2C microprocessor bus and an asynchronous serial-data communication link, such as RS-485, RS-232, or IrDA. The MAX3107 contains an advanced UART, a fractional baud-rate generator, and four GPIOs. The MAX3107 is configured and monitored, and data is written and read from 8-bit registers through SPI or I2C. These registers are organized by related function as shown in the Register Map.
PAGE 16
MAX3107 SPI/I2C UART with 128-Word FIFOs and Internal Oscillator LSB RECEIVED DATA START MSB D0 D1 D2 D3 D4 D5 D6 D7 PARITY STOP STOP MIDDATA SAMPLING Figure 4. Receive Data Format ONE BIT PERIOD RX BAUD BLOCK A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MAJORITY CENTER SAMPLER Figure 5. Midbit Sampling To halt transmission, set MODE1[1]: TxDisabl to 1. After MODE1[1] is set, the transmitter completes transmission of the current character and then ceases transmission.
PAGE 17
SPI/I2C UART with 128-Word FIFOs and Internal Oscillator LSR[1] ISR[3] OVERRUN TRIGGER WORD ExtClock to 0 and CLKSource[0]: IntOscEn to 1 to select and enable the internal oscillator. RX ERROR 128 FIFOTrgLvl[7:4] RECEIVE FIFO CURRENT FILL LEVEL LSR[0] ISR[6] LSR[5:2] External Oscillator When an external clock signal is used, this should be connected to XIN. Leave XOUT unconnected. Set CLKSource[4]: ExtClock to 1 and CLKSource[1]: CrystalEn to 0 to select external clocking.
PAGE 18
MAX3107 SPI/I2C UART with 128-Word FIFOs and Internal Oscillator The integer and fractional divisors are calculated through the divisor, D: fREF D= 16 × BaudRate where fREF is the reference frequency input to the baudrate generator and D is the ideal divisor. fREF must be less than 96MHz. In 2x and 4x rate modes, replace the divisor 16 by 8 or 4, respectively.
PAGE 19
SPI/I2C UART with 128-Word FIFOs and Internal Oscillator It is up to the host processor to filter out the data intended for its address. Alternatively, the autodata-filtering mode can be used to automatically filter out the data intended for the station’s specific 9-bit mode address. Autodata Filtering in Multidrop Mode In multidrop mode, the MAX3107 can be configured to automatically filter out data that is not meant for its address.
PAGE 20
MAX3107 SPI/I2C UART with 128-Word FIFOs and Internal Oscillator RTS/CLKOUT SETUP HOLD TX FIRST CHARACTER LAST CHARACTER Figure 10. Setup and Hold Times in Autotransceiver Direction Control Echo Suppression The MAX3107 can suppress echoed data, sometimes found in half-duplex communication (e.g., RS-485 and IrDA). If the transceiver’s receiver is not turned off while the transceiver is transmitting, copies (echoes) are received by the UART.
PAGE 21
SPI/I2C UART with 128-Word FIFOs and Internal Oscillator HOLD DELAY DI TO RO PROPAGATION DELAY RX RTS/CLKOUT Figure 12. Echo Suppression Timing RESUME are programmed in FlowLvl. With differing HALT and RESUME levels, hysteresis can be defined for the RTS/CLKOUT transitions. When the RxFIFO fill level reaches the HALT level (FlowLvl[3:0]), the MAX3107 deasserts RTS/CLKOUT. RTS/CLKOUT remains deasserted until the RxFIFO is emptied and the number of words falls to the RESUME level.
PAGE 22
MAX3107 SPI/I2C UART with 128-Word FIFOs and Internal Oscillator Transmitter Control If autotransmitter control (FlowCtrl[5:4]) is enabled, the receiver compares all received words with the XOFF and XON characters. If a XOFF is received, the MAX3107 halts its transmitter from sending further data. The receiver is not affected and continues reception. Upon receiving an XON, the transmitter restarts sending data.
PAGE 23
SPI/I2C UART with 128-Word FIFOs and Internal Oscillator enable register bit. These are the IRQEn, LSRIntEn, SpclChrIntEn and STSIntEn registers. Interrupt Clearing When an ISR interrupt is pending (i.e., any bit in ISR is set) and the ISR is subsequently read, the ISR bits and IRQ are cleared. Both the SpclCharInt and the STSInt registers also are clear on read (COR). The LSR bits are only cleared when the source of the interrupt is removed, not when LSR is read.
PAGE 24
MAX3107 SPI/I2C UART with 128-Word FIFOs and Internal Oscillator THR—Transmit Hold Register ADDRESS: MODE: 0x00 W BIT 7 6 5 4 3 2 1 0 NAME TData7 TData6 TData5 TData4 TData3 TData2 TData1 TData0 RESET 0 0 0 0 0 0 0 0 Bits 7–0: TData[7:0] The THR is the register that the host controller writes data to for subsequent UART transmission. This data is deposited in the transmit FIFO. THR[0] is the LSB.
PAGE 25
SPI/I2C UART with 128-Word FIFOs and Internal Oscillator The LSRErrIEn bit enables IRQ interrupt generation when the LSRErrInt interrupt bit is set in the ISR[0]. Set LSRErrIEn low to disable IRQ generation from LSRErrInt. ISR—Interrupt Status Register ADDRESS: MODE: 0x02 COR BIT 7 6 5 4 3 2 1 0 NAME CTSInt RxEmptyInt TxEmptyInt TFifoTrigInt RFifoTrigInt STSInt SpCharInt LSRErrInt RESET 0 1 1 0 0 0 0 0 The ISR provides an overview of all interrupts generated in the MAX3107.
PAGE 26
MAX3107 SPI/I2C UART with 128-Word FIFOs and Internal Oscillator LSRIntEn—Line Status Register Interrupt Enable ADDRESS: MODE: 0x03 R/W BIT 7 6 5 4 3 2 1 0 NAME — — NoiseIntEn RBreakIEn FrameErrIEn ParityIEn ROverrIEn RTimoutIEn RESET 0 0 0 0 0 0 0 0 The LSRIntEn allows routing of LSR interrupt bits to the ISR[0]. Bits 7 and 6: No Function Bit 5: NoiseIntEn Set the NoiseIntEn bit high to enable routing the RxNoise interrupt to LSR[0].
PAGE 27
SPI/I2C UART with 128-Word FIFOs and Internal Oscillator ADDRESS: MODE: 0x04 R BIT 7 6 5 4 3 2 1 0 NAME CTSbit X — RxNoise RxBreak FrameErr RxParityErr RxOverrun RTimeout 0 0 0 0 0 0 0 RESET The LSR shows all errors related to the oldest word in the RxFIFO, waiting to be read out of the RHR. The LSR bits are not cleared upon a read; these bits stay set until the character with errors is read out of the RHR. The LSR also reflects the current state of the CTS input.
PAGE 28
MAX3107 SPI/I2C UART with 128-Word FIFOs and Internal Oscillator Bit 0: RTimeout The RTimeout bit indicates that stale data is present in the receive FIFO. RTimeout is set when the youngest character resides in the RxFIFO for longer than the period programmed into the RxTimeOut register. The timeout counter restarts when at least one character is read out of the RxFIFO or a new character is received by the RxFIFO. If the value in RxTimeOut is zero, RTimeout is disabled.
PAGE 29
SPI/I2C UART with 128-Word FIFOs and Internal Oscillator ADDRESS: MODE: 0x06 COR BIT 7 6 5 4 3 2 1 0 NAME — — MultiDropInt BREAKInt XOFF2Int XOFF1Int XON2Int XON1Int RESET 0 0 0 0 0 0 0 0 Bits 7 and 6: No Function Bit 5: MultiDropInt The MultiDropInt interrupt is set when the MAX3107 receives an address character in 9-bit multidrop mode (MODE2[6] is 1). This bit is cleared when SpclCharInt is read. The SpclCharInt bit can be routed to ISR[1] by enabling SpclChrIntEn[5].
PAGE 30
MAX3107 SPI/I2C UART with 128-Word FIFOs and Internal Oscillator STSIntEn—STS Interrupt Enable Register ADDRESS: MODE: 0x07 R/W BIT 7 6 5 4 3 2 1 0 NAME — SleepIntEn ClkRdyIntEn — GPI3IntEn GPI2IntEn GPI1IntEn GPI0IntEn RESET 0 0 0 0 0 0 0 0 Bits 7 and 4: No Function Bit 6: SleepIntEn Set the SleepIntEn bit high to route the SleepInt status bit to the ISR[2]: STSInt. If set low, the STSIntEn masks the ISR[2] bit from SleepInt.
PAGE 31
SPI/I2C UART with 128-Word FIFOs and Internal Oscillator ADDRESS: MODE: 0x09 R/W BIT 7 6 5 4 3 2 1 0 NAME IRQSel AutoSleep ForcedSleep TrnscvCtrl RTSHiZ TxHiZ TxDisabl RxDisabl RESET 0 0 0 0 0 0 0 0 Bit 7: IRQSel Depending on the logic level of the IRQSel bit, IRQ has different meanings. After a hardware or software (MODE2[0]) reset, the IRQSel bit is set low and after a short delay, the IRQ output signals the end of the MAX3107’s power-up sequence.
PAGE 32
MAX3107 SPI/I2C UART with 128-Word FIFOs and Internal Oscillator MODE2 Register ADDRESS: MODE: 0x0A R/W BIT 7 6 5 4 3 2 1 0 NAME EchoSuprs MultiDrop Loopback SpecialChr RxEmtyInv RxTrigInv FIFORst RST RESET 0 0 0 0 0 0 0 0 Bit 7: EchoSuprs Set the EchoSuprs bit high so that the MAX3107’s receiver gates any data it receives when its transmitter is busy transmitting. In half-duplex communication (like IrDA and RS-485) this allows blocking of the locally echoed data.
PAGE 33
SPI/I2C UART with 128-Word FIFOs and Internal Oscillator ADDRESS: MODE: 0x0B R/W BIT 7 6 5 4 3 2 1 0 NAME RTS 0 TxBreak ForceParity EvenParity ParityEn StopBits Length1 Length0 0 0 0 0 1 0 1 RESET Bit 7: RTS The RTS bit gives direct control of the RTS/CLKOUT output logic. If the RTS bit is set high, then RTS/CLKOUT is set to logic-high. The RTS bit only works if the CLKSource[7]:CLKtoRTS is not set high.
PAGE 34
MAX3107 SPI/I2C UART with 128-Word FIFOs and Internal Oscillator RxTimeOut—Receiver Timeout Register ADDRESS: MODE: 0x0C R/W BIT 7 6 5 4 3 2 1 0 NAME TimOut7 TimOut6 TimOut5 TimOut4 TimOutO3 TimOut2 TimOut1 TimOut0 RESET 0 0 0 0 0 0 0 0 Bits 7–0: TimOut[7:0] The receive data timeout bits allow programming a time delay after the last (newest) character in the receive FIFO was received until a receive data timeout LSR[0] interrupt is generated.
PAGE 35
SPI/I2C UART with 128-Word FIFOs and Internal Oscillator ADDRESS: MODE: 0x0E R/W BIT 7 6 5 4 3 2 1 0 NAME — — TxInv RxInv MIR ShortIR SIR IrDAEn RESET 0 0 0 0 0 0 0 0 The IrDA allows selection of IrDA SIR and MIR-compliant pulse shaping at the TX and RX interfaces. It also allows inversion of the TX and RX logic, independently of whether IrDA is enabled or not. Bits 7 and 6: No Function Bit 5: TxInv Set the TxInv bit high to invert the logic at the TX output.
PAGE 36
MAX3107 SPI/I2C UART with 128-Word FIFOs and Internal Oscillator FIFOTrgLvl—FIFO Interrupt Trigger Level Register ADDRESS: MODE: 0x10 R/W BIT 7 6 5 4 3 2 1 0 NAME RxTrig3 RxTrig2 RxTrig1 RxTrig0 TxTrig3 TxTrig2 TxTrig1 TxTrig0 RESET 1 1 1 1 1 1 1 1 Bits 7–4: RxTrig[3:0] These 4 bits allow definition of the receive FIFO threshold level at which an ISR[3] interrupt is generated.
PAGE 37
SPI/I2C UART with 128-Word FIFOs and Internal Oscillator ADDRESS: MODE: 0x13 R/W BIT 7 6 5 4 3 2 1 0 NAME SwFlow3 SwFlow2 SwFlow1 SwFlow0 SwFlowEn GPIAddr AutoCTS AutoRTS RESET 0 0 0 0 0 0 0 0 Bits 7–4: SwFlow[3:0] The SwFlow[3:0] bits configure auto software flow control and/or special character detection in combination with the characters defined in the XON1, XON2, XOFF1 and/or XOFF2 registers. See Table 3.
PAGE 38
MAX3107 SPI/I2C UART with 128-Word FIFOs and Internal Oscillator Table 3. SwFlow[3:0] Truth Table SwFlow3 SwFlow2 SwFlow1 SwFlow0 TRANSMITTER FLOW CONTROL/SPECIAL CHARACTER DETECTION RECEIVER FLOW CONTROL DESCRIPTION 0 0 0 0 No flow control/no character detection. 0 0 X X No receiver flow control. 1 0 X X Transmitter generates XON1, XOFF1. 0 1 X X Transmitter generates XON2, XOFF2. 1 1 X X Transmitter generates XON1, XON2, XOFF1, and XOFF2.
PAGE 39
SPI/I2C UART with 128-Word FIFOs and Internal Oscillator ADDRESS: MODE: 0x15 R/W BIT 7 6 5 4 3 2 1 0 NAME Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RESET 0 0 0 0 0 0 0 0 The XON1 and XON2 register contents define the XON characters for automatic XON/XOFF flow control and/or the special characters used in special character detection. See details in the FlowCtrl register description.
PAGE 40
MAX3107 SPI/I2C UART with 128-Word FIFOs and Internal Oscillator XOFF2 Register ADDRESS: MODE: 0x17 R/W BIT 7 6 5 4 3 2 1 0 NAME Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RESET 0 0 0 0 0 0 0 0 The XOFF1 and XOFF2 register contents define the XOFF characters for automatic XON/XOFF flow control and/or special characters used in special character detection. See details in the FlowCtrl register description.
PAGE 41
SPI/I2C UART with 128-Word FIFOs and Internal Oscillator ADDRESS: MODE: 0x1A R/W BIT 7 6 5 4 3 2 1 0 NAME PLLFactor1 PLLFactor0 PreDiv5 PreDiv4 PreDiv3 PreDiv2 PreDiv1 PreDiv0 RESET 0 0 0 0 0 0 0 1 Bits 7 and 6: PLLFactor[1:0] The two PLLFactor[1:0] bits allow programming with select PLL’s multiplication factor. The input and output frequencies of the PLL have to be limited to the ranges shown in Table 4. Enable the PLL through CLKSource[2].
PAGE 42
MAX3107 SPI/I2C UART with 128-Word FIFOs and Internal Oscillator BRGConfig—Baud-Rate Generator Configuration Register ADDRESS: MODE: 0x1B R/W BIT 7 6 5 4 3 2 1 0 NAME — — 4xMode 2xMode FRACT3 FRACT2 FRACT1 FRACT0 RESET 0 0 0 0 0 0 0 0 Bits 7 and 6: No Function Bit 5: 4xMode When the 4xMode bit is set high, the MAX3107 baud rate is quadruple the regular (16x sampling) baud rate. The 2xMode bit should be set low if 4xMode is enabled.
PAGE 43
SPI/I2C UART with 128-Word FIFOs and Internal Oscillator ADDRESS: MODE: 0x1E R/W BIT 7 6 5 4 3 2 1 0 NAME CLKtoRTS — — ExtClock PLLBypass PLLEn CrystalEn IntOscEn RESET 0 0 0 0 1 0 0 0 Bit 7: CLKtoRTS Set the CLKtoRTS bit to 1 to route the baud-rate generator (16x baud rate) output clock to RTS/CLKOUT. The clock frequency is a factor of 16x, 8x, or 4x of the baud rate, depending on the BRGConfig[5:4] settings.
PAGE 44
MAX3107 SPI/I2C UART with 128-Word FIFOs and Internal Oscillator Serial Controller Interface The MAX3107 can be controlled through SPI or I2C as defined by the logic on I2C/SPI. See the Pin Configurations for further details. SPI Interface The SPI supports both single-cycle and burst-read/write access. The SPI master must generate clock and data signals in SPI MODE0 (i.e., with clock polarity CPOL = 0 and clock phase CPHA = 0).
PAGE 45
SPI/I2C UART with 128-Word FIFOs and Internal Oscillator Sr P SCL SDA Figure 17. I2C START, STOP, and Repeated START Conditions WRITE SINGLE BYTE S DEVICE SLAVE ADDRESS - W A 8 DATA BITS A FROM MASTER TO STAVE REGISTER ADDRESS A P FROM SLAVE TO MASTER Figure 18. Write Byte Sequence Table 5. I2C Address Map DIN/A1 CS/A0 0 0 0 1 1 0 1 1 READ/ WRITE I2C ADDRESS W 0x58 (see the START, STOP, and Repeated START Conditions section).
PAGE 46
MAX3107 SPI/I2C UART with 128-Word FIFOs and Internal Oscillator BURST WRITE S DEVICE SLAVE ADDRESS - W A REGISTER ADDRESS A 8 DATA BITS - 1 A 8 DATA BITS - 2 A 8 DATA BITS - N A FROM MASTER TO STAVE P FROM SLAVE TO MASTER Figure 19. Burst Write Sequence READ SINGLE BYTE S DEVICE SLAVE ADDRESS - W A REGISTER ADDRESS A Sr DEVICE SLAVE ADDRESS - R A 8 DATA BITS NA FROM MASTER TO STAVE P FROM SLAVE TO MASTER Figure 20.
PAGE 47
SPI/I2C UART with 128-Word FIFOs and Internal Oscillator MAX3107 BURST READ S DEVICE SLAVE ADDRESS - W A REGISTER ADDRESS A Sr DEVICE SLAVE ADDRESS - R A 8 DATA BITS - 1 A 8 DATA BITS - 2 A 8 DATA BITS - 3 A 8 DATA BITS - N A FROM MASTER TO STAVE P FROM SLAVE TO MASTER Figure 21. Burst Read Sequence 11) Repeat steps 9 and 10 N - 1 times. S SCL 1 2 8 9 NOT ACKNOWLEDGE SDA ACKNOWLEDGE Figure 22.
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MAX3107 SPI/I2C UART with 128-Word FIFOs and Internal Oscillator ENABLE INTERRUPTS POWER-UP/ RST INPUT PULLED HIGH/ RST BIT SET LOW CONFIGURE FIFO CONTROL IS IRQ HIGH? OR RevID READ SUCCESSFULLY N CONFIGURE FLOW CONTROL Y CONFIGURE CLOCKING CONFIGURE GPIOs CONFIGURE MODES START COMMUNICATION Figure 23. Startup and Initialization Flowchart To reduce the power consumption during normal operation, the following techniques can be adopted: • D o not use the internal PLL.
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SPI/I2C UART with 128-Word FIFOs and Internal Oscillator 3.3V 2.5V VL VDD VA VEXT RST MICROCONTROLLER TX DI RX RO RTS/CLKOUT DE MAX3107 SPI/I2C IRQ AGND VCC MAX3078 TRANSCEIVER DGND Figure 24. Logic-Level Translation RS-232 5x3 Application TX MAX3107 RX SHARED CONNECTOR TX/D+ RX/D- D+ OE MAX13481E D- Figure 25. Connector Sharing with a USB Transceiver Connector Pin Sharing The TX and RTS/CLKOUT outputs can be programmed to be high impedance.
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MAX3107 SPI/I2C UART with 128-Word FIFOs and Internal Oscillator MAX3078 SPI/I2C MAX3107 TX T1IN RX R1OUT RTS/CLKOUT RST CTS MICROCONTROLLER IRQ LDOEN Tx Rx T2IN RTS R2OUT GPIO1 T3IN GPIO2 R3OUT GPIO3 R4OUT GPIO4 R5OUT CTS DTR DSR DCD RI Figure 26. RS-232 Application 3.3V 0.1µF VA LDOEN VEXT VL TX I2C/SPI RTS/CLKOUT 10kΩ MAX3107 RX IRQ MICROCONTROLLER DI A DE B RO RE XOUT SPI MAX14840 RST AGND V18 XIN DGND 0.1µF Figure 27.
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SPI/I2C UART with 128-Word FIFOs and Internal Oscillator VA V18 VL LDOEN VEXT LDO I2C/SPI TX AND FIFO DIN/A1 TX SPI/I2C DOUT/SDA CS/A0 SCLK/SCL REGISTERS AND CONTROL LOGIC-LEVEL TRANSLATION RX Rx AND FIFO IRQ XIN RTS/CLKOUT LOGIC-LEVEL TRANSLATION RST XOUT CTS FLOW CONTROL CRYSTAL OSCILLATOR GPIO0 DIVIDER FRACTIONAL BAUD-RATE GENERATOR PLL INTERNAL OSCILLATOR GPIO1 GPIO GPIO2 GPIO3 MAX3107 AGND DGND Package Information For the latest package outline information and land patte