Owner manual

MAX5099
ON/OFF
The MAX5099 provide an input (ON/OFF) to turn on and
off the external load-dump protection MOSFET. Drive
ON/OFF high for normal operation. Drive ON/OFF low to
turn off the external n-channel load-dump protection
MOSFET and reduce the supply current to 7μA (typ).
When ON/OFF is driven low, both converters are also
turned off, and the PGOOD_ outputs are driven, low. V+
will be self-discharged through the converters’ output
currents and the IC supply current.
Internal Oscillator/
Out-of-Phase Operation
The internal oscillator generates the 180° out-of-phase
clock signal required by each regulator. The switching
frequency of each converter (f
SW
) is programmable
from 200kHz to 2.2MHz using a single 1% resistor at
R
OSC
. See the Setting the Switching Frequency section.
With dual-synchronized out-of-phase operation, the
MAX5099’s internal MOSFETs turn on 180° out-of-
phase. The instantaneous input current peaks of both
regulators do not overlap, resulting in reduced RMS rip-
ple current and input-voltage ripple. This reduces the
required input capacitor ripple current rating, allows for
fewer or less expensive capacitors, and reduces
shielding requirements for EMI.
Synchronization (SYNC)
The main oscillator can be synchronized to the system
clock by applying an external clock (f
SYNC
) at SYNC.
The f
SYNC
frequency must be twice the required operat-
ing frequency of an individual converter. Use a TTL logic
signal for the external clock with at least a 100ns pulse
width. R
OSC
is still required when using external syn-
chronization. Program the internal oscillator frequency to
have f
SW
= 1/2 f
SYNC
. The device is properly synchro-
nized if the SYNC frequency f
SYNC
varies within the
range ±20%.
Short SYNC to SGND if unused.
Input Voltage (V+)/
Internal Linear Regulator (V
L
)
All internal control circuitry operates from an internally
regulated nominal voltage of 5.2V (V
L
). At higher input
voltages (V+) of 5.2V to 19V, V
L
is regulated to 5.2V. At
5.2V or below, the internal linear regulator operates in
dropout mode, where V
L
follows V+. Depending on the
load on V
L
, the dropout voltage can be high enough to
reduce V
L
below the undervoltage-lockout (UVLO)
threshold. Do not use V
L
to power external circuitry.
For input voltages less than 5.5V, connect V+ and V
L
together. The load on V
L
is proportional to the switching
frequency of converter 1 and converter 2. See the V
L
Output Voltage vs. Converter Switching Frequency
graph in the
Typical Operating Characteristics . For
input voltage ranges higher than 5.5V, disconnect V
L
from V+.
Bypass V+ to SGND with a 1μF or greater ceramic
capacitor placed close to the MAX5099. Bypass V
L
with
a low-ESR 4.7μF ceramic capacitor to SGND.
Undervoltage Lockout/
Soft-Start/Soft-Stop
The MAX5099 includes an undervoltage lockout with
hysteresis and a power-on-reset circuit for converter
turn-on and monotonic rise of the output voltage. The
falling UVLO threshold is internally set to 4.1V (typ) with
180mV hysteresis. Hysteresis at UVLO eliminates “chat-
tering” during startup. When V
L
drops below UVLO, the
internal MOSFET switches are turned off.
The MAX5099 digital soft-start reduces input inrush
currents and glitches at the input during turn-on. When
UVLO is cleared and EN_ is high, digital soft-start slow-
ly ramps up the internal reference voltage in 64 steps.
The total soft-start period is 4096 internal oscillator
switching cycles.
Driving EN_ low initiates digital soft-stop that slowly
ramps down the internal reference voltage in 64 steps.
The total soft-stop period is equal to the soft-start period.
To calculate the soft-start/soft-stop period, use the fol-
lowing equation:
where f
OSC
is the internal oscillator and f
OSC
is twice
each converter’s switching frequency (FSEL_1 = V
L
).
tms
f kHz
SS
OSC
()
()
=
4096
Dual, 2.2MHz, Automotive Synchronous Buck
Converter with 80V Load-Dump Protection
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