Owner manual

MAX5132/MAX5133
+5V/+3V, 13-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
14 ______________________________________________________________________________________
__________Applications Information
Definitions
Integral Nonlinearity (INL)
Integral nonlinearity (Figure 8a) is the deviation of the
values on an actual transfer function from a straight
line. This straight line can be either a best-straight-line
fit (closest approximation to the actual transfer curve) or
a line drawn between the endpoints of the transfer func-
tion, once offset and gain errors have been nullified. For
a DAC, the deviations are measured at every single
step.
Differential Nonlinearity (DNL)
Differential nonlinearity (Figure 8b) is the difference
between an actual step height and the ideal value of
1LSB. If the magnitude of the DNL is less than or equal to
1LSB, the DAC guarantees no missing codes and is
monotonic.
Offset Error
The offset error (Figure 8c) is the difference between
the ideal and the actual offset point. For a DAC, the off-
set point is the step value when the digital input is zero.
This error affects all codes by the same amount and
can usually be compensated for by trimming.
Table 3. Detailed SSPCON Register Contents
X = Don’t care
Table 4. Detailed SSPSTAT Register Contents
X = Don’t care
SSPM3 0
Synchronous Serial-Port Mode Select Bit. Sets SPI master mode
and selects f
CLK
= f
OSC
/ 16.
MAX5132/MAX5133
SETTINGS
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER
(SSPCON)
WCOL X Write-Collision Detection Bit
SSPM1 0
CONTROL BIT
BIT1
BIT0SSPM0 1
BIT3
BIT2SSPM2 0
SSPEN 1
Synchronous Serial Port Enable Bit
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI as seri-
al-port pins.
BIT5
BIT4CKP 0 Clock-Polarity Select Bit. CKP = 0 for SPI master-mode selection.
BIT7
BIT6SSPOV X Receive-Overflow Detection Bit
S X Start Bit
MAX5132/MAX5133
SETTINGS
SYNCHRONOUS SERIAL-PORT STATUS REGISTER
(SSPSTAT)
SMP 0
SPI Data-Input Sample Phase. Input data is sampled at the mid-
dle of the data-output time.
UA X
CONTROL BIT
BIT1
BIT0BF X
BIT3
BIT2R/W X
D/A X Data-Address BitBIT5
BIT4P X Stop Bit
Read/Write Bit Information
Update Address
BIT7
Buffer Full-Status Bit
BIT6CKE 1
SPI Clock-Edge Select Bit. Data will be transmitted on the rising
edge of the serial clock.