Owner manual

MAX5132/MAX5133
+5V/+3V, 13-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS—MAX5133 (+3V) (continued)
(V
DD
= +3V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, R
L
= 5kΩ, C
L
= 100pF, output amplifier
connected in unity-gain, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
To ±0.5LSB, V
STEP
= 1.25V
CS = V
DD
, f
SCLK
= 100kHz,
V
SCLK
= 3Vp-p
CONDITIONS
µA320I
SHDN
Power-Supply Current in Shutdown
µA500 600I
DD
Power-Supply Current (Note 5)
V2.7 3.6V
DD
Power-Supply Voltage (Note 5)
nV-s5Digital Feedthrough
ms2Time Required to Exit Shutdown
µA-0.1 0 0.1Current into FB
µs20Output Settling Time
V0 to V
DD
Output Voltage Swing (Note 4)
UNITSMIN TYP MAXSYMBOLPARAMETER
I
SINK
= 2mA V0.13 0.4V
OL
Output Low Voltage
I
SOURCE
= 2mA VV
DD
- 0.5V
OH
Output High Voltage
V
IN
= 0 or V
DD
µA-1 0.001 1I
IN
Input Leakage Current
pF8C
IN
Input Capacitance
V/µs0.6SRVoltage Output Slew Rate
TIMING CHARACTERISTICS—MAX5132 (+5V)
(V
DD
= +5V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, R
L
= 5kΩ, C
L
= 100pF, output amplifier connect-
ed in unity-gain, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
ns40t
CSS
CS Fall to SCLK Rise Setup Time
ns40t
CL
SCLK Pulse Width Low
CONDITIONS
ns100t
CP
SCLK Clock Period
ns40t
CH
SCLK Pulse Width High
ns0t
CSH
SCLK Rise to CS Rise Hold Time
ns10t
CS0
SCLK Rise to CS Fall Delay Time
ns40t
DS
SDI Setup Time
ns0t
DH
SDI Hold Time
UNITSMIN TYP MAXSYMBOLPARAMETER
ns100t
CSW
CS Pulse Width High
ns40t
CS1
CS Rise to SCLK Rise Hold Time
C
LOAD
= 200pF ns80t
DO1
SCLK Rise to DOUT Valid
Propagation Delay Time
C
LOAD
= 200pF ns80t
DO2
SCLK Fall to DOUT Valid
Propagation Delay Time
DIGITAL OUTPUTS
POWER REQUIREMENTS
DYNAMIC PERFORMANCE