Instruction Manual

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_______________General Description

The MAX534 serial-input, voltage-output, 8-bit quad dig-

ital-to-analog converter (DAC) operates from a single

+4.5V to +5.5V supply. Internal precision buffers swing

rail to rail, and the reference input range includes both

ground and the positive rail. The MAX534 features a

2.5µA shutdown mode.

The serial interface is double buffered: a 12-bit input

shift register is followed by four 8-bit buffer registers and

four 8-bit DAC registers. The 12-bit serial word consists

of eight data bits and four control bits (for DAC selection

and special programming commands). Both the input

and DAC registers can be updated independently or

simultaneously with a single software command. Two

additional asynchronous control pins, LDAC and CLR,

provide simultaneous updating or clearing of the input

and DAC registers.

The interface is compatible with SPI™, QSPI™ (CPOL =

CPHA = 0 or CPOL = CPHA = 1), and Microwire™. A

buffered data output allows daisy chaining of serial

devices.

In addition to 16-pin DIP and CERDIP packages, the

MAX534 is available in a 16-pin QSOP that occupies the

same area as an 8-pin SO.

For operation guaranteed to 2.7V, see the MAX533

data sheet.

________________________Applications

Digital Gain and Offset Adjustments

Programmable Attenuators

Programmable Current Sources

Portable Instruments

____________________________Features

♦ +4.5V to +5.5V Single-Supply Operation

♦ Ultra-Low Supply Current:

0.8mA while Operating

2.5µA in Shutdown Mode

♦ Ultra-Small 16-Pin QSOP Package

♦ Ground to V

Reference Input Range

♦ Output Buffer Amplifiers Swing Rail to Rail

♦ 10MHz Serial Interface Compatible with SPI, QSPI

(CPOL = CPHA = 0 or CPOL = CPHA = 1), and

Microwire

♦ Double-Buffered Registers for Synchronous

Updating

♦ Serial Data Output for Daisy Chaining

♦ Power-On Reset Clears Serial Interface and Sets

All Registers to Zero

♦ Software Shutdown

♦ Software-Programmable Logic Output (µC I/O

Extender)

♦ Asynchronous Hardware Clear Resets All Internal

Registers to Zero

MAX534

+5V, Low-Power, 8-Bit Quad DAC

with Rail-to-Rail Output Buffers

________________________________________________________________

Maxim Integrated Products

OUTC

OUTD

AGND



DGND

DIN

SCLK

OUTB

OUTA

REF

UPO

PDE

LDAC

CLR

DOUT

TOP VIEW

MAX534

DIP/QSOP

__________________Pin Configuration

19-1105; Rev 0; 8/96

PART

MAX534ACPE

MAX534BCPE

MAX534ACEE 0°C to +70°C

0°C to +70°C

TEMP. RANGE PIN-PACKAGE

16 Plastic DIP

16 QSOP

______________Ordering Information

*Dice are tested at T

= +25°C.

**Contact factory for availability and processing to MIL-STD-883.

SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.

Functional Diagram appears at end of data sheet.

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800

MAX534BCEE 0°C to +70°C 16 QSOP

MAX534BC/D 0°C to +70°C Dice*

MAX534AEPE -40°C to +85°C 16 Plastic DIP

MAX534BEPE -40°C to +85°C 16 Plastic DIP

MAX534AEEE -40°C to +85°C 16 QSOP

MAX534BEEE -40°C to +85°C 16 QSOP

MAX534AMJE -55°C to +125°C 16 CERDIP**

MAX534BMJE -55°C to +125°C 16 CERDIP**

INL

(LSB)

±1

±2

±1

±2

±1

±2

±1

±2

±1

±2

Summary of content (16 pages)

PAGE 1
9-1105; Rev 0; 8/96 +5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers ________________________Applications ____________________________Features ♦ +4.5V to +5.5V Single-Supply Operation ♦ Ultra-Low Supply Current: 0.8mA while Operating 2.
PAGE 2
MAX534 +5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers ABSOLUTE MAXIMUM RATINGS VDD to DGND ..............................................................-0.3V, +6V VDD to AGND...............................................................-0.3V, +6V Digital Input Voltage to DGND ....................................-0.3V, +6V Digital Output Voltage to DGND....................-0.3V, (VDD + 0.3V) AGND to DGND ..................................................................±0.3V REF .........
PAGE 3
+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers (VDD = +4.5V to +5.5V, VREF = 4.096V, AGND = DGND = 0V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V and TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS Input High Voltage VIH Input Low Voltage VIL 0.7VDD Input Current IIN VIN = 0V or VDD Input Capacitance CIN (Note 4) Output High Voltage VOH ISOURCE = 0.2mA Output Low Voltage VOL ISINK = 1.
PAGE 4
MAX534 +5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers TIMING CHARACTERISTICS (continued) (VDD = +4.5V to +5.5V, VREF = 4.096V, AGND = DGND = 0V, CDOUT = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V and TA = +25°C.
PAGE 5
+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers 0.75 0.50 0.25 0 800 4.0 3.5 3.0 VREF = 5V DAC CODE = FF HEX LOAD TO GND 2.5 1 2 4 3 5 6 7 8 600 DAC CODE = 00 HEX 400 200 VREF = 4.5V 0 2.0 0 DAC OUTPUT SINK CURRENT (mA) 2 4 6 8 12 10 SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE 5 -55 -35 -15 5 25 65 85 105 125 45 TEMPERATURE (°C) DAC OUTPUT SOURCE CODE (mA) SUPPLY CURRENT vs.
PAGE 6
MAX534 +5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers ______________________________________________________________Pin Description 6 PIN NAME 1 OUTB DAC B Voltage Output FUNCTION 2 OUTA DAC A Voltage Output 3 REF Reference-Voltage Input 4 UPO Software-Programmable Logic Output 5 PDE Power-Down Enable. Must be high to allow software shutdown mode. 6 LDAC Load DAC Input (active low).
PAGE 7
+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers MAX534 INSTRUCTION EXECUTED CS ••• ••• SCLK ••• DIN A1 A0 C1 C0 A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 MSB D7 D6 D5 D4 D3 D2 MSB LSB LSB DACD DACA ••• DOUT MODE 1 A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1 A1 A0 C1 C0 DATA FROM PREVIOUS DATA INPUT DOUT MODE 0 (DEFAULT) D1 D0 D6 D5 D4 D3 D2 D1 D0 D7 A1 DATA FROM PREVIOUS DATA INPUT ••• A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1 A1 A0 C1 C0 D6 D5 D4 D3 D2 D1 D0 D7 A1 Fig
PAGE 8
MAX534 +5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers _______________Detailed Description Serial Interface At power-on, the serial interface and all digital-toanalog converters (DACs) are cleared and set to code zero. The serial data output (DOUT) is set to transition on SCLK’s falling edge. The MAX534 communicates with microprocessors through a synchronous, full-duplex, 3-wire interface (Figure 1).
PAGE 9
+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers MAX534 Table 1. Serial-Interface Programming Commands 12-BIT SERIAL WORD A1 A0 C1 C0 D7 . . . . . . . . D0 LDAC 0 0 1 1 0 1 0 1 0 0 0 0 1 1 1 1 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data 1 1 1 1 Load input register A; all DAC outputs unchanged. Load input register B; all DAC outputs unchanged. Load input register C; all DAC outputs unchanged. Load input register D; all DAC outputs unchanged.
PAGE 10
MAX534 +5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers For this command, the data bits are “Don't Cares.” As an example, three MAX534s are daisy chained (A, B, and C), and devices A and C need to be updated. The 36-bit-wide command would consist of one 12-bit word for device C, followed by an NOP instruction for device B and a third 12-bit word with data for device A. At CS’s rising edge, device B will not change state.
PAGE 11
+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers Daisy-Chaining Devices Any number of MAX534s can be daisy-chained by connecting DOUT of one device to DIN of the following device in the chain. The NOP instruction (Table 1) allows data to be passed from DIN to DOUT without changing the input or DAC registers of the passing device. A 3-wire interface updates daisy-chained or individual MAX534s simultaneously by bringing CS high (Figure 6).
PAGE 12
MAX534 +5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers DIN SCLK LDAC CS1 TO OTHER SERIAL DEVICES CS2 CS3 CS CS CS LDAC MAX534 LDAC MAX534 LDAC MAX534 SCLK SCLK SCLK DIN DIN DIN Figure 7. Multiple MAX534s sharing one DIN line. Simultaneously update by strobing LDAC, or specifically update by enabling an individual CS.
PAGE 13
+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers DAC Linearity and Voltage Offset The output buffer can have a negative input offset voltage that would normally drive the output negative, but since there is no negative supply the output stays at 0V (Figure 9). When linearity is determined using the endpoint method, it is measured between zero code (all inputs 0) and full-scale code (all inputs 1) after offset and gain error are calibrated out.
PAGE 14
MAX534 +5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers Table 2.
PAGE 15
+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers TRANSISTOR COUNT: 6821 ________________________________________________________Package Information DIM A A1 A2 B C D E e H h L N S α D A e A1 B S E INCHES MILLIMETERS MAX MIN MIN MAX 0.068 0.061 1.55 1.73 0.004 0.0098 0.127 0.25 0.061 0.055 1.40 1.55 0.012 0.008 0.20 0.31 0.0075 0.0098 0.19 0.25 SEE VARIATIONS 0.157 0.150 3.81 3.99 0.25 BSC 0.635 BSC 0.244 0.230 5.84 6.20 0.016 0.010 0.25 0.41 0.035 0.016 0.41 0.
PAGE 16
MAX534 +5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers ________________________________________________________Package Information DIM E1 D A A B B1 C E E1 e L L1 Q S S1 E 0°-15° Q L L1 e C B1 B S1 S CERDIP CERAMIC DUAL-IN-LINE PACKAGE (0.300 in.) INCHES MIN MAX – 0.200 0.014 0.023 0.038 0.065 0.008 0.015 0.220 0.310 0.290 0.320 0.100 0.125 0.200 0.150 – 0.015 0.070 – 0.098 0.005 – DIM PINS D D D D D D 8 14 16 18 20 24 MILLIMETERS MIN MAX – 5.08 0.36 0.58 0.97 1.65 0.20 0.