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General Description

The MAX555 is an advanced, monolithic, 12-bit digital-

to-analog converter (DAC) with complementary 50Ω

outputs. Fabricated using an oxide-isolated bipolar

process, the MAX555 is designed for signal-reconstruc-

tion applications at an output update rate of 300Msps.

It incorporates an analog multiplying function with

10MHz useable input bandwidth. The voltage-output

DAC uses precision laser trimming to achieve 12-bit

accuracy with ±1/2LSB integral and differential linearity

(±0.012% FS). Absolute gain error is a low 1% of full

scale. Full-scale transitions occur in less than 0.5ns.

Internal registers and a unique decoder reduce glitch-

ing and allow the MAX555 to achieve precise RF perfor-

mance with over 73dBc of spurious-free dynamic range

at 50Msps with f

OUT

= 3.1MHz, or 62dBc at 300Msps

with f

OUT

= 18.6MHz.

The MAX555 operates from a single -5.2V supply and

dissipates 980mW (nominal). It comes in a 64-pin TQFP

package with exposed paddle for enhanced thermal

dissipation.

________________________Applications

Direct Digital Synthesis

Arbitrary Waveform Generation

HDTV/High-Resolution Graphics

Instrumentation

Communications Local Oscillators

Automated Tester Applications

____________________________Features

♦ 12-Bit Resolution

♦ ±1/2LSB Integral and Differential Nonlinearity

♦ Capable of 300Msps (min) Update Rate

♦ Complementary 50Ω Outputs

♦ Multiplying Reference Input

♦ Low Glitch Energy (5.6pVs)

♦ Single -5.2V Power Supply

♦ On-Chip Data Registers

♦ ECL-Compatible Inputs with Differential Clock

Ordering Information

MAX555

300Msps, 12-Bit DAC with

Complementary Voltage Outputs

________________________________________________________________ Maxim Integrated Products 1

-20mA

LGND

VOUT

CLKCLK

ROFFSET

REF

50Ω

800Ω

50Ω

BYPASS

DECODED

BIT

LINES

12-BIT

ECL

LINES

LEVEL-SENSITIVE TRANSPARENT LATCH

MAX555

___________________________________________________Simplified Block Diagram

19-0297; Rev 3; 6/02

PART

MAX555CCB 0°C to +70°C

TEMP RANGE PIN-PACKAGE

64 TQFP-EP*

Pin Configuration appears at end of data sheet.

EVALUATION KIT MANUAL

AVAILABLE

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

*EP = Exposed pad.

Summary of content (12 pages)

PAGE 1
9-0297; Rev 3; 6/02 ANUAL N KIT M IO T A U EVAL BLE AVAILA 300Msps, 12-Bit DAC with Complementary Voltage Outputs ____________________________Features The MAX555 is an advanced, monolithic, 12-bit digitalto-analog converter (DAC) with complementary 50Ω outputs. Fabricated using an oxide-isolated bipolar process, the MAX555 is designed for signal-reconstruction applications at an output update rate of 300Msps. It incorporates an analog multiplying function with 10MHz useable input bandwidth.
PAGE 2
MAX555 300Msps, 12-Bit DAC with Complementary Voltage Outputs ABSOLUTE MAXIMUM RATINGS Analog Supply Voltage (AVEE) .................................-7V to +0.3V Digital Supply Voltage (DVEE) ..................................-7V to +0.3V Digital Input Voltage (D0–D11) ...................................-5.5V to 0V Reference Input Voltage (VIN) .................................0V to +1.25V Reference Input Current....................................0mA to +1.56mA Output Compliance Voltage (VOC).............
PAGE 3
00Msps, 12-Bit DAC with Complementary Voltage Outputs (AVEE = DVEE = -5.2V, VREF = 1.000V, TMIN to TMAX = 0°C to +70°C, unless otherwise noted.) (Note 2.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 10 200 µA DIGITAL INPUTS Input Current, Logic High IIH VIH = -0.75V Input Current, Logic Low IIL VIL = -1.95V 1 2 µA Logic "1" Voltage VIH -1.1 -0.75 0 V Logic "0" Voltage VIL -2.0 -1.95 -1.
PAGE 4
__________________________________________Typical Operating Characteristics (AVEE = DVEE = -5.2V, VREF = 0.75V, TA = +25°C, unless otherwise noted.) SPURIOUS-FREE DYNAMIC RANGE vs. fOUT (fCLK = 50MHz) 66 68 66 SFDR (dBc) 70 SFDR (dBc) 68 66 62 58 64 54 64 62 62 50 60 0 4 8 12 16 20 0 4 8 12 16 20 24 0 28 18 24 30 fOUT (MHz) SPURIOUS-FREE DYNAMIC RANGE vs. fOUT (fCLK = 200MHz) SPURIOUS-FREE DYNAMIC RANGE vs. fOUT (fCLK = 250MHz) SPURIOUS-FREE DYNAMIC RANGE vs.
PAGE 5
300Msps, 12-Bit DAC with Complementary Voltage Outputs PIN NAME 1, 14, 16–19, 27, 28, 29, 31–38, 48, 49, 64 AGND 2, 6, 54, 60 DGND 3 D8 Data Bit 8 (ECL Input) 4 D9 Data Bit 9 (ECL Input) 5 D10 7, 53 DVEE 8 D11 Data Bit 11 (ECL Input)—MSB 9, 10, 11, 13, 39, 46, 58 N.C. No Connection 12 LBIAS 15 ALTCOMPC 20 ROFFSET FUNCTION Analog Ground. Note: Exposed pad on the back of the package must be connected to AGND. Digital Ground Data Bit 10 (ECL Input) -5.
PAGE 6
MAX555 300Msps, 12-Bit DAC with Complementary Voltage Outputs RESISTOR-DIVIDER NETWORK DIGITAL SECTION I1 3 CURRENT I2 SOURCES AND I3 SWITCHING NETWORK 3 17 I3 17 I2 3 I1 3 LSB (D0) MASTER REGISTER SLAVE REGISTER 8 8 12 INPUTS 4 MSB (D11) CLK 4 TO 15 15 DECODER 15 ÷8 ÷8 IO VOUT 50Ω LGND 2 50Ω ÷8 ÷8 IO VOUT MAX555 CLK BYPASS LOOPCRNT ALTCOMPC I = VIN/RIN REF/2 400Ω 400Ω REF (1V FS) ALTCOMPIB 800Ω ROFFSET 800Ω CONTROL AMPLIFIER AVEE LBIAS DVEE AVEE AGND DGND Fig
PAGE 7
300Msps, 12-Bit DAC with Complementary Voltage Outputs In clocked mode (BYPASS = 0), when the clock line is low, the slave register is locked out and information on the digital inputs is permitted to enter the master register. The clock transition from low to high locks the master register in its present state and ignores further changes on the digital inputs. This transition simultane- The MAX555 has separate pins for analog and digital supplies.
PAGE 8
MAX555 300Msps, 12-Bit DAC with Complementary Voltage Outputs possible latchup. Appropriate decoupling is needed to prevent digital-section current spikes from affecting the analog section (Figure 4). It is recommended that a multilayer PC board be used, containing a solid ground and power planes. All analog and digital ground pins must be connected directly to the analog ground plane at the MAX555, preferably with a “star connection” at the LGND pins (15 and 16).
PAGE 9
300Msps, 12-Bit DAC with Complementary Voltage Outputs -1 -11 -11 -21 -21 -31 -31 dBm dBm -1 -41 -41 -51 -51 -61 -61 -71 -71 -81 -81 4.5MHz/div 2.3MHz/div OUTPUT SPECTRUM (fOUT = 9.3MHz, fCLK = 150MHz) OUTPUT SPECTRUM (fOUT = 30MHz, fCLK = 200MHz) -1 -11 -11 -21 -21 -31 -31 -41 dBm dBm -1 -41 -51 -51 -61 -61 -71 -71 -81 -81 7MHz/div 9.
PAGE 10
MAX555 300Msps, 12-Bit DAC with Complementary Voltage Outputs VREF 1.000V POWER SUPPLY -5.2V 0.1µF IREF 1.25mA 0.1µF 0.1µF 0.1µF 0.
PAGE 11
300Msps, 12-Bit DAC with Complementary Voltage Outputs AGND DGND BYPASS D1 D2 DVEE D3 CLK CLK N.C. D4 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 D5 64 D6 AGND D7 DGND TOP VIEW AGND 1 48 AGND DGND 2 47 D0 D8 3 D9 4 45 VOUT D10 5 44 VOUT DGND 6 43 LGND DVEE 7 42 LGND D11 8 41 VOUT N.C. 9 46 N.C. * MAX555 40 VOUT N.C. 10 39 N.C. N.C. 11 38 AGND LBIAS 12 37 AGND N.C.
PAGE 12
Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 64L, TQFP.EPS MAX555 250Msps, 12-Bit DAC with Complementary Voltage Outputs Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.