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General Description

The MAX5556–MAX5559 stereo audio sigma-delta

digital-to-analog converters (DACs) offer a simple and

complete stereo digital-to-analog solution for media

servers, set-top boxes, video-game hardware, automo-

tive rear-seat entertainment and other general consumer

audio applications. These DACs feature built-in digital

interpolation/filtering, sigma-delta digital-to-analog con-

version and analog output filtering. Control logic and

mute circuitry minimize audible pops and clicks during

power-up, power-down, clock changes, or when invalid

clock conditions occur.

The MAX5556–MAX5559 receive input data over a flexi-

ble 3-wire interface, supporting I

S-compatible, left-jus-

tified, right-justified 16-bit, and right-justified 18-bit

audio data. Data can be clocked by either an external

or internal serial clock. The internal serial clock frequen-

cy is programmable by selection of a master clock

(MCLK) and sample clock (LRCLK) ratio. Sampling

rates from 2kHz to 50kHz are supported.

The MAX5556–MAX5559 operate from a single +4.75V

to +5.5V analog supply with total harmonic distortion

plus noise below -87dB. These devices are available in

8-pin SO packages and are specified over the -40°C to

+85°C industrial temperature range.

Applications

Digital Video Recorders and Media Servers

Set-Top Boxes

Video-Game Hardware

Automotive Rear-Seat Entertainment

Features

♦ Simple and Complete Stereo Audio DAC

Solutions, No Controls to Set

♦ Sigma-Delta Stereo DACs with Built-In

Interpolation and Analog Output Filters

♦ I

S-Compatible Digital Audio Interface (MAX5556)

♦ Clickless/Popless Operation

♦ Output Voltage Swing: 3.5V

P-P

♦ -87dB THD+N

♦ +87dB Dynamic Range

♦ Sample Frequencies (f

) from 2kHz to 50kHz

♦ Master Clock (MCLK) up to 25MHz

♦ Automatic Detection of Clock Ratio (MCLK/

LRCLK)

MAX5556–MAX5559

Ordering Information

Typical Operating Circuit

19-0550; Rev 0; 5/06

Low-Cost Stereo Audio DACs

________________________________________________________________

Maxim Integrated Products

For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Note:

All devices are specified over the -40°C to +85°C oper-

ating temperature range. Contact factory for +105°C operation.

Future product—contact factory for availability.

SERIAL

INTERFACE

MCLK

LRCLK

SCLK

SDATA

GND

OUTR

OUTL

CLOCK

DAC

+5V

LEFT

OUTPUT

RIGHT

OUTPUT

LINE-LEVEL

BUFFER

LINE-LEVEL

BUFFER

AUDIO

DECOMPRESSION

MAX5556–MAX5559

Pin Configuration

GND

OUTRMCLK

OUTL

SCLK

LRCLK

SDATA

TOP VIEW

MAX5556–

MAX5559

PART

PIN -

PA C K A G E

PKG

CODE

DATA FORMAT

MAX5556ESA 8 SO S8-5 Left-justified I

S data

M A X5 5 5 7 E S A* 8 SO S8-5 Left-justified data

M A X5 5 5 8 E S A* 8 SO S8-5 Ri g ht- j usti fi ed 16- Bi t d ata

M A X5 5 5 9 E S A* 8 SO S8-5 Ri g ht- j usti fi ed 18- Bi t d ata

Summary of content (19 pages)

PAGE 1
9-0550; Rev 0; 5/06 Low-Cost Stereo Audio DACs The MAX5556–MAX5559 stereo audio sigma-delta digital-to-analog converters (DACs) offer a simple and complete stereo digital-to-analog solution for media servers, set-top boxes, video-game hardware, automotive rear-seat entertainment and other general consumer audio applications. These DACs feature built-in digital interpolation/filtering, sigma-delta digital-to-analog conversion and analog output filtering.
PAGE 2
MAX5556–MAX5559 Low-Cost Stereo Audio DACs ABSOLUTE MAXIMUM RATINGS VDD to GND ...........................................................-0.3V to +6.0V OUTL, OUTR, SDATA to GND................... -0.3V to (VDD + 0.3V) Current Into Any Pin (excluding VDD and GND)...............±10mA OUTL, OUTR Shorted to GND....................................Continuous SCLK, LRCLK, MCLK to GND ...............................-0.3V to +6.0V Continuous Power Dissipation (TA = +70°C) 8-Pin SO (derate 5.88mW above +70°C)......
PAGE 3
Low-Cost Stereo Audio DACs (VDD = +4.75V to +5.5V, GND = 0V, ROUT_ = 10kΩ, COUT_ = 10pF, 0dBFS sine-wave signal at 997Hz, fLRCLK (fS) = 48kHz, fMCLK = 12.288MHz, measurement bandwidth 10Hz to 20kHz, unless otherwise specified. TA = -40°C to +85°C, unless otherwise noted. Outputs are unloaded, unless otherwise noted. Typical values at VDD = +5V, TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.1 0.
PAGE 4
ELECTRICAL CHARACTERISTICS (continued) (VDD = +4.75V to +5.5V, GND = 0V, ROUT_ = 10kΩ, COUT_ = 10pF, 0dBFS sine-wave signal at 997Hz, fLRCLK (fS) = 48kHz, fMCLK = 12.288MHz, measurement bandwidth 10Hz to 20kHz, unless otherwise specified. TA = -40°C to +85°C, unless otherwise noted. Outputs are unloaded, unless otherwise noted. Typical values at VDD = +5V, TA = +25°C.
PAGE 5
Low-Cost Stereo Audio DACs (VDD = +5V, GND = 0V, ROUT_ = 10kΩ, COUT_ = 10pF, TA = +25°C, unless otherwise noted.) -20 -30 AMPLITUDE (dB) -40 -50 -60 -2 -40 -50 -60 -3 -4 -5 -6 -70 -70 -7 -80 -80 -8 -90 -90 -9 -100 -100 -10 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.40 0.44 FREQUENCY (NORMALIZED TO fS) 0.48 0.05 0 -0.05 -0.10 -0.15 -0.20 -0.25 0.4 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 0.
PAGE 6
Typical Operating Characteristics (continued) (VDD = +5V, GND = 0V, ROUT_ = 10kΩ, COUT_ = 10pF, TA = +25°C, unless otherwise noted.) UNWEIGHTED THD+N vs. FREQUENCY -80 -90 50 40 30 20 14 13 -100 0 INPUT = 1kHz, 0dBFS SIGNAL NORMAL OPERATION 11 10 9 STATIC DIGITAL INPUT MUTE OPERATION 8 6 2 4 6 8 10 12 14 16 18 20 5 0 10 20 30 40 FREQUENCY (kHz) SAMPLE FREQUENCY (kHz) SUPPLY CURRENT vs. DIGITAL INPUT VOLTAGE (VDIG) CLOCK-LOSS MUTE RECOVERY 50 4.75 VDIG < VIH MUTE ENGAGED 5.05 5.
PAGE 7
Low-Cost Stereo Audio DACs PIN NAME FUNCTION 1 SDATA 2 SCLK 3 LRCLK Left-/Right-Channel Select Clock. For the MAX5556, drive LRCLK low to direct data to OUTL or LRCLK high to direct data to OUTR. For the MAX5557/MAX5558/MAX5559, drive LRCLK high to direct data to OUTL or LRCLK low to direct data to OUTR. 4 MCLK Master Clock Input. The MCLK/LRCLK ratio must equal to 256, 384, or 512. 5 OUTR Right-Channel Analog Output 6 GND Ground 7 VDD Power-Supply Input. Bypass VDD to GND with a 0.
PAGE 8
MAX5556–MAX5559 Low-Cost Stereo Audio DACs VDD SIGMA-DELTA MODULATOR INTERPOLATOR ANALOG LOWPASS FILTER DAC SDATA OUTL BUFFER SCLK INTERNAL REFERENCE SERIAL INTERFACE LRCLK MCLK SIGMA-DELTA MODULATOR INTERPOLATOR ANALOG LOWPASS FILTER DAC OUTR BUFFER MAX5556–MAX5559 GND Figure 2. Functional Diagram 125 LOAD CAPACITANCE CL (pF) 100 75 50 SAFE OPERATING REGION 25 3 5 10 15 20 25 LOAD RESISTANCE RL (kΩ) Figure 3.
PAGE 9
Low-Cost Stereo Audio DACs SDATA Input The serial interface strobes data (SDATA) in on the rising edge of SCLK, MSB first. The MAX5556–MAX5559 support four different data formats, as detailed in Figures 4–7.
PAGE 10
MAX5556–MAX5559 Low-Cost Stereo Audio DACs LRCLK DATA DIRECTED TO OUTR DATA DIRECTED TO OUTL SCLK SDATA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 MSB 0 15 LSB MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSB INTERNAL SERIAL CLOCK MODE EXTERNAL SERIAL CLOCK MODE • RIGHT-JUSTIFIED, 16-BIT DATA • INTERNAL SCLK = 32 x fS IF MCLK / LRCLK = 256 OR 512 • INTERNAL SCLK = 48 x fS IF MCLK / LRCLK = 384 • RIGHT-JUSTIFIED, 16-BIT DATA • DATA VALID ON RISING EDGE OF SCLK • SCLK MUST HAVE
PAGE 11
Low-Cost Stereo Audio DACs MAX5556–MAX5559 LRCLK tSCLK tSLRH tSLRS tSCLKL tSCLKH SCLK tSDH tSDS SDATA Figure 8. External SCLK Serial Timing Diagram LRCLK tISCLKR SDATA tISDS tISDH tISCLK INTERNAL SCLK Figure 9. Internal SCLK Serial Timing Diagram LRCLK MCLK 1 N / 2* N* INTERNAL SCLK SDATA *N = MCLK / SCLK. Figure 10.
PAGE 12
MAX5556–MAX5559 Low-Cost Stereo Audio DACs Left/Right Clock Input (LRCLK) LRCLK is the left/right clock input signal for the 3-wire interface and sets the sample frequency (fS). On the MAX5556, drive LRCLK low to direct data to OUTL or LRCLK high to direct data to OUTR (Figure 4). On the MAX5557/MAX5558/MAX5559, drive LRCLK high to direct data to OUTL or LRCLK low to direct data to OUTR (Figures 5, 6, 7). LRCLK is internally resampled on each SCLK rising edge.
PAGE 13
Low-Cost Stereo Audio DACs MAX5559 18-Bit Right-Justified Data Format The MAX5559 accepts data with an 18-bit right-justified data format. The LSB is valid on the final SCLK rising edge prior to LRCLK transitioning low to high or high to low (Figure 7). In external serial clock mode, the MAX5559 requires a minimum of 36 SCLK cycles per LRCLK period (18 SCLK cycles with LRCLK low and 18 SCLK cycles with LRCLK high). Drive LRCLK high to direct data to OUTL. Drive LRCLK low to direct data to OUTR.
PAGE 14
MAX5556–MAX5559 Low-Cost Stereo Audio DACs 56pF +5V 5.23kΩ 24.3kΩ OUTR 33pF 10kΩ 59kΩ VBIAS MAX5556–MAX5559 56pF +5V 5.23kΩ 24.3kΩ OUTL 33pF 10kΩ 59kΩ VBIAS Figure 12.
PAGE 15
Low-Cost Stereo Audio DACs MAX5556–MAX5559 NO POWER APPLIED POWER-UP OUTPUTS HELD AT GROUND OUTPUTS HELD AT CURRENT LEVELS VALID CLOCK RATIO ESTABLISHED LofC OUTPUTS LINEARLY RAMPED TO DC QUIESCENT LEVELS (< 1 SECOND) VALID CLOCK RATIO RE-ESTABLISHED VALID CLOCK RATIO RE-ESTABLISHED INTERNAL REGISTERS INITIALIZED (MUTE) LofC LOSSOFPOWER EVENT OUTPUTS IMMEDIATELY RETURNED TO DC QUIESCENT LEVELS LofC LofC LofC = LOSS OF CLOCK EVENT SOFT-START VOLUME RAMPING NORMAL OPERATION (FULL VOLUME) INVALID
PAGE 16
MAX5556–MAX5559 Low-Cost Stereo Audio DACs Pop and Click Suppression Power-Down The MAX5556–MAX5559 feature a pop and click supression routine to reduce the unwanted audible effects of system transients. This routine produces glitch-free operation at the outputs during power-on, loss of clock, or invalid clock conditions. See Figure 13 for a detailed state diagram during transient conditions. When the positive supply is removed from the MAX5556–MAX5559, the outputs discharge to ground.
PAGE 17
Low-Cost Stereo Audio DACs MAX5556–MAX5559 VOUT_ SETTLES AT QUIESCENT VOLTAGE (2.4V) VOUT_ RAMPS UP TO QUIESCENT VOLTAGE AT 5V/s (TYP) OUTPUT VOLTAGE (OUTR OR OUTL) VALID MCLK/LRCLK RATIO DETECTED VOUT_ BEGINS TO FOLLOW THE DATA. THE AMPLITUDE IS RAMPED TO FULL SCALE (20ms TYP) TIME Figure 14. Power-Up Sequence INVALID CLOCK CONDITION MUTE: VOUT_ IMMEDIATELY FORCED TO DC QUIESCENT LEVEL (2.
PAGE 18
MAX5556–MAX5559 Low-Cost Stereo Audio DACs Power-Supply Connections and Ground Management Proper layout and grounding are essential for optimum performance. Use large traces for the power-supply inputs and analog outputs to minimize losses due to parasitic trace resistance. Large traces also aid in moving heat away from the package. Proper grounding improves audio performance, minimizes crosstalk between channels, and prevents any switching noise from coupling into the audio signal.
PAGE 19
Low-Cost Stereo Audio DACs N E H INCHES MILLIMETERS MAX MIN 0.069 0.053 0.010 0.004 0.014 0.019 0.007 0.010 0.050 BSC 0.150 0.157 0.228 0.244 0.016 0.050 MAX MIN 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 1.27 BSC 3.80 4.00 5.80 6.20 0.40 SOICN .EPS DIM A A1 B C e E H L 1.27 VARIATIONS: 1 INCHES TOP VIEW DIM D D D MIN 0.189 0.337 0.386 MAX 0.197 0.344 0.394 MILLIMETERS MIN 4.80 8.55 9.80 MAX 5.00 8.75 10.